diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/fs | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/fs')
14 files changed, 18302 insertions, 18157 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 401e8a630..9abb1e987 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,123 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884209 # Number of seconds simulated -sim_ticks 1884208734500 # Number of ticks simulated -final_tick 1884208734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.883224 # Number of seconds simulated +sim_ticks 1883223940000 # Number of ticks simulated +final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147223 # Simulator instruction rate (inst/s) -host_op_rate 147223 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4942377286 # Simulator tick rate (ticks/s) -host_mem_usage 320260 # Number of bytes of host memory used -host_seconds 381.24 # Real time elapsed on the host -sim_insts 56126572 # Number of instructions simulated -sim_ops 56126572 # Number of ops (including micro ops) simulated +host_inst_rate 180615 # Simulator instruction rate (inst/s) +host_op_rate 180615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6060637883 # Simulator tick rate (ticks/s) +host_mem_usage 316396 # Number of bytes of host memory used +host_seconds 310.73 # Real time elapsed on the host +sim_insts 56122642 # Number of instructions simulated +sim_ops 56122642 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914048 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28566400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7560448 # Number of bytes written to this memory -system.physmem.bytes_written::total 7560448 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404907 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446350 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118132 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118132 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1407674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15160953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4012532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4012532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4012532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1407674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19173485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446350 # Number of read requests accepted -system.physmem.writeReqs 118132 # Number of write requests accepted -system.physmem.readBursts 446350 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118132 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28559040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7558400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28566400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7560448 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 405186 # Number of read requests accepted +system.physmem.writeReqs 118157 # Number of write requests accepted +system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue +system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28089 # Per bank write bursts -system.physmem.perBankRdBursts::1 28219 # Per bank write bursts -system.physmem.perBankRdBursts::2 28571 # Per bank write bursts -system.physmem.perBankRdBursts::3 28273 # Per bank write bursts -system.physmem.perBankRdBursts::4 27775 # Per bank write bursts -system.physmem.perBankRdBursts::5 27529 # Per bank write bursts -system.physmem.perBankRdBursts::6 27274 # Per bank write bursts -system.physmem.perBankRdBursts::7 26987 # Per bank write bursts -system.physmem.perBankRdBursts::8 27827 # Per bank write bursts -system.physmem.perBankRdBursts::9 27514 # Per bank write bursts -system.physmem.perBankRdBursts::10 28065 # Per bank write bursts -system.physmem.perBankRdBursts::11 27430 # Per bank write bursts -system.physmem.perBankRdBursts::12 27510 # Per bank write bursts -system.physmem.perBankRdBursts::13 28401 # Per bank write bursts -system.physmem.perBankRdBursts::14 28311 # Per bank write bursts -system.physmem.perBankRdBursts::15 28460 # Per bank write bursts -system.physmem.perBankWrBursts::0 7814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25480 # Per bank write bursts +system.physmem.perBankRdBursts::1 25741 # Per bank write bursts +system.physmem.perBankRdBursts::2 25855 # Per bank write bursts +system.physmem.perBankRdBursts::3 25788 # Per bank write bursts +system.physmem.perBankRdBursts::4 25233 # Per bank write bursts +system.physmem.perBankRdBursts::5 24956 # Per bank write bursts +system.physmem.perBankRdBursts::6 24811 # Per bank write bursts +system.physmem.perBankRdBursts::7 24586 # Per bank write bursts +system.physmem.perBankRdBursts::8 25127 # Per bank write bursts +system.physmem.perBankRdBursts::9 25280 # Per bank write bursts +system.physmem.perBankRdBursts::10 25532 # Per bank write bursts +system.physmem.perBankRdBursts::11 24857 # Per bank write bursts +system.physmem.perBankRdBursts::12 24547 # Per bank write bursts +system.physmem.perBankRdBursts::13 25588 # Per bank write bursts +system.physmem.perBankRdBursts::14 25870 # Per bank write bursts +system.physmem.perBankRdBursts::15 25740 # Per bank write bursts +system.physmem.perBankWrBursts::0 7812 # Per bank write bursts system.physmem.perBankWrBursts::1 7677 # Per bank write bursts -system.physmem.perBankWrBursts::2 8054 # Per bank write bursts -system.physmem.perBankWrBursts::3 7732 # Per bank write bursts -system.physmem.perBankWrBursts::4 7319 # Per bank write bursts -system.physmem.perBankWrBursts::5 6955 # Per bank write bursts +system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6954 # Per bank write bursts system.physmem.perBankWrBursts::6 6788 # Per bank write bursts system.physmem.perBankWrBursts::7 6406 # Per bank write bursts system.physmem.perBankWrBursts::8 7235 # Per bank write bursts -system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 7390 # Per bank write bursts +system.physmem.perBankWrBursts::9 6889 # Per bank write bursts +system.physmem.perBankWrBursts::10 7393 # Per bank write bursts system.physmem.perBankWrBursts::11 6865 # Per bank write bursts -system.physmem.perBankWrBursts::12 7046 # Per bank write bursts -system.physmem.perBankWrBursts::13 8008 # Per bank write bursts -system.physmem.perBankWrBursts::14 7991 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts +system.physmem.perBankWrBursts::12 7045 # Per bank write bursts +system.physmem.perBankWrBursts::13 8007 # Per bank write bursts +system.physmem.perBankWrBursts::14 7989 # Per bank write bursts +system.physmem.perBankWrBursts::15 7937 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1884200137500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1883215178500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 446350 # Read request sizes (log2) +system.physmem.readPktSize::6 405186 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118132 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2519 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118157 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -144,283 +147,274 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65499 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 551.419716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 340.219574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.619626 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14326 21.87% 21.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10638 16.24% 38.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5049 7.71% 45.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3016 4.60% 50.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2484 3.79% 54.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2116 3.23% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1384 2.11% 59.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1595 2.44% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24891 38.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65499 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.074383 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.502018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2530.928651 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6961 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6964 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6964 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.958644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.733261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.741198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5665 81.35% 81.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.52% 81.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 854 12.26% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 55 0.79% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.14% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 13 0.19% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 23 0.33% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 94 1.35% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.17% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 41 0.59% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 13 0.19% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.24% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.19% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.17% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 21 0.30% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 7 0.10% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.03% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 8 0.11% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 7 0.10% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.01% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.01% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 4 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 9 0.13% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 8 0.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6964 # Writes before turning the bus around for reads -system.physmem.totQLat 7297586750 # Total ticks spent queuing -system.physmem.totMemAccLat 15664493000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2231175000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16353.69 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads +system.physmem.totQLat 2131293750 # Total ticks spent queuing +system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35103.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.97 # Average write queue length when enqueuing -system.physmem.readRowHits 402726 # Number of row buffer hits during reads -system.physmem.writeRowHits 96110 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.36 # Row buffer hit rate for writes -system.physmem.avgGap 3337927.76 # Average gap between requests -system.physmem.pageHitRate 88.39 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774702818500 # Time in different power states -system.physmem.memoryStateTime::REF 62917660000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364467 # Number of row buffer hits during reads +system.physmem.writeRowHits 95695 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes +system.physmem.avgGap 3598433.87 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states +system.physmem.memoryStateTime::REF 62884900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46582219000 # Time in different power states +system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19215856 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295757 # Transaction distribution -system.membus.trans_dist::ReadResp 295741 # Transaction distribution -system.membus.trans_dist::WriteReq 9619 # Transaction distribution -system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 158094 # Transaction distribution -system.membus.trans_dist::ReadExResp 158094 # Transaction distribution +system.membus.throughput 17814330 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295751 # Transaction distribution +system.membus.trans_dist::ReadResp 295735 # Transaction distribution +system.membus.trans_dist::WriteReq 9618 # Transaction distribution +system.membus.trans_dist::WriteResp 9618 # Transaction distribution +system.membus.trans_dist::Writeback 76605 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 157 # Transaction distribution +system.membus.trans_dist::UpgradeResp 157 # Transaction distribution +system.membus.trans_dist::ReadExReq 116539 # Transaction distribution +system.membus.trans_dist::ReadExResp 116539 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044827 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30817728 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30862044 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36171164 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36171164 # Total data (bytes) -system.membus.snoop_data_through_bus 35520 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29834000 # Layer occupancy (ticks) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33538260 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1588295250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825084824 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376625999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.295855 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026399000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.295855 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080991 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080991 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 375533 # Number of tag accesses +system.iocache.tags.data_accesses 375533 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12414876231 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12414876231 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12436010364 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12436010364 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12436010364 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12436010364 # number of overall miss cycles +system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122162.618497 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122162.618497 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 298779.270095 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 298779.270095 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298046.982960 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298046.982960 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298046.982960 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 364154 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28275 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.879010 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10251971233 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10251971233 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10264108366 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10264108366 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10264108366 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10264108366 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70156.838150 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70156.838150 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246726.300371 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 246726.300371 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 245994.208892 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 245994.208892 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -434,36 +428,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14968340 # Number of BP lookups -system.cpu.branchPred.condPredicted 12984271 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 377638 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10101234 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5190890 # Number of BTB hits +system.cpu.branchPred.lookups 14964215 # Number of BP lookups +system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.388672 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808188 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32062 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9240282 # DTB read hits -system.cpu.dtb.read_misses 17901 # DTB read misses +system.cpu.dtb.read_hits 9238395 # DTB read hits +system.cpu.dtb.read_misses 17814 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766280 # DTB read accesses -system.cpu.dtb.write_hits 6385567 # DTB write hits -system.cpu.dtb.write_misses 2310 # DTB write misses +system.cpu.dtb.read_accesses 766068 # DTB read accesses +system.cpu.dtb.write_hits 6385066 # DTB write hits +system.cpu.dtb.write_misses 2311 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298488 # DTB write accesses -system.cpu.dtb.data_hits 15625849 # DTB hits -system.cpu.dtb.data_misses 20211 # DTB misses +system.cpu.dtb.write_accesses 298441 # DTB write accesses +system.cpu.dtb.data_hits 15623461 # DTB hits +system.cpu.dtb.data_misses 20125 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064768 # DTB accesses -system.cpu.itb.fetch_hits 4001359 # ITB hits -system.cpu.itb.fetch_misses 6809 # ITB misses -system.cpu.itb.fetch_acv 657 # ITB acv -system.cpu.itb.fetch_accesses 4008168 # ITB accesses +system.cpu.dtb.data_accesses 1064509 # DTB accesses +system.cpu.itb.fetch_hits 4000795 # ITB hits +system.cpu.itb.fetch_misses 6874 # ITB misses +system.cpu.itb.fetch_acv 703 # ITB acv +system.cpu.itb.fetch_accesses 4007669 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -476,39 +470,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 176815826 # number of cpu cycles simulated +system.cpu.numCycles 176776474 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56126572 # Number of instructions committed -system.cpu.committedOps 56126572 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2538059 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5497 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593513250 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.150305 # CPI: cycles per instruction -system.cpu.ipc 0.317430 # IPC: instructions per cycle +system.cpu.committedInsts 56122642 # Number of instructions committed +system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.149825 # CPI: cycles per instruction +system.cpu.ipc 0.317478 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211465 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105856 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148872 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833844528000 97.33% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80077500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673181000 0.04% 97.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49609971000 2.63% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884207757500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693584 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814956 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -544,35 +538,35 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175516 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192403 # number of callpals executed +system.cpu.kern.callpal::total 192390 # number of callpals executed system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches -system.cpu.kern.mode_switch::user 1735 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1735 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324587 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080952 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36214076000 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4058025000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843935646500 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.tickCycles 85802593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 91013233 # Total number of cycles that the object has spent stopped +system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -604,12 +598,13 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1436106 # Throughput (bytes/s) +system.iobus.throughput 1436853 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51171 # Transaction distribution -system.iobus.trans_dist::WriteResp 51171 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51169 # Transaction distribution +system.iobus.trans_dist::WriteResp 51170 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -621,11 +616,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +632,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705924 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705916 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -664,66 +659,66 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380105365 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43180001 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1458006 # number of replacements -system.cpu.icache.tags.tagsinuse 509.628197 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18953120 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458517 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.994789 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31559763000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.628197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995368 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995368 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1458007 # number of replacements +system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21870509 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21870509 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18953123 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18953123 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18953123 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18953123 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18953123 # number of overall hits -system.cpu.icache.overall_hits::total 18953123 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458693 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458693 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458693 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458693 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458693 # number of overall misses -system.cpu.icache.overall_misses::total 1458693 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20024605540 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20024605540 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20024605540 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20024605540 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20024605540 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20024605540 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20411816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20411816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20411816 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20411816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20411816 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20411816 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.772424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13727.772424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13727.772424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.772424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13727.772424 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits +system.cpu.icache.overall_hits::total 18950163 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses +system.cpu.icache.overall_misses::total 1458695 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,142 +727,143 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458693 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458693 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458693 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458693 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458693 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458693 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17099831460 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17099831460 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17099831460 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17099831460 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17099831460 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17099831460 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071463 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071463 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071463 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071463 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.707561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.707561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.707561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.707561 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 125457945 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2557417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557383 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304222 # Transaction distribution +system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143032604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 236385052 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 236375068 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 13888 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2697678498 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 232500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191733540 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2191719796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194708666 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194901157 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 339421 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65326.541432 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.369830 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339412 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65326.749870 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2981869 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404575 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54488.510247 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10838.031185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996804 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30250697 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30250697 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261599 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838210 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838210 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1459 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 30252211 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30252211 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2261673 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2261673 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 838282 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838282 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 187541 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187541 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2449140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2449140 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18918477985 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8091487855 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8091487855 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27009965840 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27009965840 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27009965840 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27009965840 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550253 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2550253 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838210 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304221 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304221 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2854474 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2854474 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2854474 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2854474 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113186 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113186 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818182 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383537 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383537 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.142000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.142000 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65540.328507 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65540.328507 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 11916.500000 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11916.500000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69347.684736 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69347.684736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66636.319282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66636.319282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66636.319282 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 187588 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187588 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2449261 # 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number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113181 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.113181 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.833333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383470 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383470 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141991 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141991 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65512.016366 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,54 +872,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76620 # number of writebacks -system.cpu.l2cache.writebacks::total 76620 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288654 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116680 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116680 # 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miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133388 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093282 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093282 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086492 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086492 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117117 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117117 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117117 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117117 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25813.836117 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25813.836117 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36165.857085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36165.857085 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13393.216371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13393.216371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29159.126433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29159.126433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29159.126433 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1019,64 +1015,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838210 # number of writebacks -system.cpu.dcache.writebacks::total 838210 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127240 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127240 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269470 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks +system.cpu.dcache.writebacks::total 838282 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127187 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127187 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269448 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269448 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396710 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074353 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074353 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304205 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304205 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17306 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17306 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378558 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378558 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378558 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378558 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26912219745 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26912219745 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10275413589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10275413589 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196866500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196866500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37187633334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37187633334 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37187633334 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37187633334 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423283000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423283000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003033000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003033000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426316000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426316000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119244 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049460 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086522 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086522 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090932 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090932 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090932 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25049.699442 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25049.699442 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33777.924719 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33777.924719 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11375.621172 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.621172 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26975.748089 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26975.748089 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.inst 396635 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396635 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 396635 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396635 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074429 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074429 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304251 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304251 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17296 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17296 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1378680 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378680 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1378680 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378680 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26906996250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26906996250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10272860843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10272860843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196930250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196930250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179857093 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 2b53a578a..683e407e9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,138 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906207 # Number of seconds simulated -sim_ticks 1906207240000 # Number of ticks simulated -final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.903124 # Number of seconds simulated +sim_ticks 1903123778500 # Number of ticks simulated +final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147655 # Simulator instruction rate (inst/s) -host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5021061637 # Simulator tick rate (ticks/s) -host_mem_usage 308576 # Number of bytes of host memory used -host_seconds 379.64 # Real time elapsed on the host -sim_insts 56056069 # Number of instructions simulated -sim_ops 56056069 # Number of ops (including micro ops) simulated +host_inst_rate 103415 # Simulator instruction rate (inst/s) +host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3505224116 # Simulator tick rate (ticks/s) +host_mem_usage 322696 # Number of bytes of host memory used +host_seconds 542.94 # Real time elapsed on the host +sim_insts 56148221 # Number of instructions simulated +sim_ops 56148221 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451755 # Number of read requests accepted -system.physmem.writeReqs 122625 # Number of write requests accepted -system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory +system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411673 # Number of read requests accepted +system.physmem.writeReqs 123979 # Number of write requests accepted +system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28097 # Per bank write bursts -system.physmem.perBankRdBursts::1 28602 # Per bank write bursts -system.physmem.perBankRdBursts::2 29043 # Per bank write bursts -system.physmem.perBankRdBursts::3 27571 # Per bank write bursts -system.physmem.perBankRdBursts::4 27384 # Per bank write bursts -system.physmem.perBankRdBursts::5 27564 # Per bank write bursts -system.physmem.perBankRdBursts::6 27744 # Per bank write bursts -system.physmem.perBankRdBursts::7 27694 # Per bank write bursts -system.physmem.perBankRdBursts::8 27865 # Per bank write bursts -system.physmem.perBankRdBursts::9 28720 # Per bank write bursts -system.physmem.perBankRdBursts::10 28531 # Per bank write bursts -system.physmem.perBankRdBursts::11 28618 # Per bank write bursts -system.physmem.perBankRdBursts::12 28938 # Per bank write bursts -system.physmem.perBankRdBursts::13 28977 # Per bank write bursts -system.physmem.perBankRdBursts::14 28277 # Per bank write bursts -system.physmem.perBankRdBursts::15 28002 # Per bank write bursts -system.physmem.perBankWrBursts::0 7839 # Per bank write bursts -system.physmem.perBankWrBursts::1 8045 # Per bank write bursts -system.physmem.perBankWrBursts::2 8418 # Per bank write bursts -system.physmem.perBankWrBursts::3 7040 # Per bank write bursts -system.physmem.perBankWrBursts::4 6886 # Per bank write bursts -system.physmem.perBankWrBursts::5 7040 # Per bank write bursts -system.physmem.perBankWrBursts::6 7326 # Per bank write bursts -system.physmem.perBankWrBursts::7 7097 # Per bank write bursts -system.physmem.perBankWrBursts::8 7158 # Per bank write bursts -system.physmem.perBankWrBursts::9 7908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7739 # Per bank write bursts -system.physmem.perBankWrBursts::11 7821 # Per bank write bursts -system.physmem.perBankWrBursts::12 8331 # Per bank write bursts -system.physmem.perBankWrBursts::13 8401 # Per bank write bursts -system.physmem.perBankWrBursts::14 7959 # Per bank write bursts -system.physmem.perBankWrBursts::15 7587 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25632 # Per bank write bursts +system.physmem.perBankRdBursts::1 25720 # Per bank write bursts +system.physmem.perBankRdBursts::2 26346 # Per bank write bursts +system.physmem.perBankRdBursts::3 25660 # Per bank write bursts +system.physmem.perBankRdBursts::4 25672 # Per bank write bursts +system.physmem.perBankRdBursts::5 25150 # Per bank write bursts +system.physmem.perBankRdBursts::6 25568 # Per bank write bursts +system.physmem.perBankRdBursts::7 25491 # Per bank write bursts +system.physmem.perBankRdBursts::8 25973 # Per bank write bursts +system.physmem.perBankRdBursts::9 26167 # Per bank write bursts +system.physmem.perBankRdBursts::10 25812 # Per bank write bursts +system.physmem.perBankRdBursts::11 25687 # Per bank write bursts +system.physmem.perBankRdBursts::12 26023 # Per bank write bursts +system.physmem.perBankRdBursts::13 25844 # Per bank write bursts +system.physmem.perBankRdBursts::14 25108 # Per bank write bursts +system.physmem.perBankRdBursts::15 25632 # Per bank write bursts +system.physmem.perBankWrBursts::0 8431 # Per bank write bursts +system.physmem.perBankWrBursts::1 7989 # Per bank write bursts +system.physmem.perBankWrBursts::2 8275 # Per bank write bursts +system.physmem.perBankWrBursts::3 7382 # Per bank write bursts +system.physmem.perBankWrBursts::4 7684 # Per bank write bursts +system.physmem.perBankWrBursts::5 7400 # Per bank write bursts +system.physmem.perBankWrBursts::6 7193 # Per bank write bursts +system.physmem.perBankWrBursts::7 7021 # Per bank write bursts +system.physmem.perBankWrBursts::8 7374 # Per bank write bursts +system.physmem.perBankWrBursts::9 7755 # Per bank write bursts +system.physmem.perBankWrBursts::10 7777 # Per bank write bursts +system.physmem.perBankWrBursts::11 7454 # Per bank write bursts +system.physmem.perBankWrBursts::12 8052 # Per bank write bursts +system.physmem.perBankWrBursts::13 8097 # Per bank write bursts +system.physmem.perBankWrBursts::14 7762 # Per bank write bursts +system.physmem.perBankWrBursts::15 8306 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1906202745000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1903119235000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 451755 # Read request sizes (log2) +system.physmem.readPktSize::6 411673 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123979 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # 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What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -158,359 +161,357 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads -system.physmem.totQLat 9007685000 # Total ticks spent queuing -system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads +system.physmem.totQLat 3887945250 # Total ticks spent queuing +system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing -system.physmem.readRowHits 408104 # Number of row buffer hits during reads -system.physmem.writeRowHits 99226 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes -system.physmem.avgGap 3318713.65 # Average gap between requests -system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states -system.physmem.memoryStateTime::REF 63652420000 # Time in different power states +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 371100 # Number of row buffer hits during reads +system.physmem.writeRowHits 99427 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes +system.physmem.avgGap 3552902.32 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states +system.physmem.memoryStateTime::REF 63549460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states +system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19340215 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296416 # Transaction distribution -system.membus.trans_dist::ReadResp 296338 # Transaction distribution -system.membus.trans_dist::WriteReq 12317 # Transaction distribution -system.membus.trans_dist::WriteResp 12317 # Transaction distribution -system.membus.trans_dist::Writeback 122625 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution -system.membus.trans_dist::ReadExReq 163308 # Transaction distribution -system.membus.trans_dist::ReadExResp 163210 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36828250 # Total data (bytes) -system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) +system.membus.throughput 18054612 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296849 # Transaction distribution +system.membus.trans_dist::ReadResp 296569 # Transaction distribution +system.membus.trans_dist::WriteReq 12351 # Transaction distribution +system.membus.trans_dist::WriteResp 12351 # Transaction distribution +system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution +system.membus.trans_dist::ReadExReq 122594 # Transaction distribution +system.membus.trans_dist::ReadExResp 122459 # Transaction distribution +system.membus.trans_dist::BadAddressError 280 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34349922 # Total data (bytes) +system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 344852 # number of replacements -system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use -system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27313168 # Number of tag accesses -system.l2c.tags.data_accesses 27313168 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits -system.l2c.Writeback_hits::total 833565 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076901 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 887867500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2463812500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2506345500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1346682000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3853027500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.332576 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006860 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.130614 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.952645 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.878444 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.938855 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636364 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.694561 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.433880 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237142 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.393862 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163038 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.356133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.049239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163038 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53148.244515 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78863.058152 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53904.606206 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.580583 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.367159 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10021.369586 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10262.873016 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10059.203883 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10136.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70314.625224 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84710.913565 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72077.706793 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63778.895769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58011.646357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65459.688256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84046.157056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59312.009753 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -648,102 +649,94 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41700 # number of replacements -system.iocache.tags.tagsinuse 0.491390 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.219567 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41716 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711322153000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.491390 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030712 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030712 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710336549000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.219567 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.013723 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.013723 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375588 # Number of tag accesses -system.iocache.tags.data_accesses 375588 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses -system.iocache.ReadReq_misses::total 180 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses -system.iocache.demand_misses::total 41732 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses -system.iocache.overall_misses::total 41732 # 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number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.demand_misses::tsunami.ide 175 # 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number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -757,35 +750,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13535285 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits +system.cpu0.branchPred.lookups 13702956 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9655924 # DTB read hits -system.cpu0.dtb.read_misses 34371 # DTB read misses -system.cpu0.dtb.read_acv 569 # DTB read access violations -system.cpu0.dtb.read_accesses 673777 # DTB read accesses -system.cpu0.dtb.write_hits 6329246 # DTB write hits -system.cpu0.dtb.write_misses 8477 # DTB write misses -system.cpu0.dtb.write_acv 351 # DTB write access violations -system.cpu0.dtb.write_accesses 236111 # DTB write accesses -system.cpu0.dtb.data_hits 15985170 # DTB hits -system.cpu0.dtb.data_misses 42848 # DTB misses -system.cpu0.dtb.data_acv 920 # DTB access violations -system.cpu0.dtb.data_accesses 909888 # DTB accesses -system.cpu0.itb.fetch_hits 1092484 # ITB hits -system.cpu0.itb.fetch_misses 31809 # ITB misses -system.cpu0.itb.fetch_acv 996 # ITB acv -system.cpu0.itb.fetch_accesses 1124293 # ITB accesses +system.cpu0.dtb.read_hits 7950804 # DTB read hits +system.cpu0.dtb.read_misses 30543 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 683229 # DTB read accesses +system.cpu0.dtb.write_hits 5159026 # DTB write hits +system.cpu0.dtb.write_misses 6845 # DTB write misses +system.cpu0.dtb.write_acv 353 # DTB write access violations +system.cpu0.dtb.write_accesses 234573 # DTB write accesses +system.cpu0.dtb.data_hits 13109830 # DTB hits +system.cpu0.dtb.data_misses 37388 # DTB misses +system.cpu0.dtb.data_acv 899 # DTB access violations +system.cpu0.dtb.data_accesses 917802 # DTB accesses +system.cpu0.itb.fetch_hits 1312718 # ITB hits +system.cpu0.itb.fetch_misses 29261 # ITB misses +system.cpu0.itb.fetch_acv 629 # ITB acv +system.cpu0.itb.fetch_accesses 1341979 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -798,304 +791,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 120980731 # number of cpu cycles simulated +system.cpu0.numCycles 99665250 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued -system.cpu0.iq.rate 0.455910 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued +system.cpu0.iq.rate 0.452554 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3510502 # number of nop insts executed -system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8653897 # Number of branches executed -system.cpu0.iew.exec_stores 6352232 # Number of stores executed -system.cpu0.iew.exec_rate 0.451396 # Inst execution rate -system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 27468175 # num instructions producing a value -system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value +system.cpu0.iew.exec_nop 2858560 # number of nop insts executed +system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7039370 # Number of branches executed +system.cpu0.iew.exec_stores 5177228 # Number of stores executed +system.cpu0.iew.exec_rate 0.448278 # Inst execution rate +system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 22691402 # num instructions producing a value +system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 54435622 # Number of instructions committed -system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 44358216 # Number of instructions committed +system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14871832 # Number of memory references committed -system.cpu0.commit.loads 8745646 # Number of loads committed -system.cpu0.commit.membars 219982 # Number of memory barriers committed -system.cpu0.commit.branches 8204799 # Number of branches committed -system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. -system.cpu0.commit.function_calls 712916 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction +system.cpu0.commit.refs 12070511 # Number of memory references committed +system.cpu0.commit.loads 7090878 # Number of loads committed +system.cpu0.commit.membars 170277 # Number of memory barriers committed +system.cpu0.commit.branches 6663650 # Number of branches committed +system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. +system.cpu0.commit.function_calls 549728 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 139225703 # The number of ROB reads -system.cpu0.rob.rob_writes 125735253 # The number of ROB writes -system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 51290467 # Number of Instructions Simulated -system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads -system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes -system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads -system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads -system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes +system.cpu0.rob.rob_reads 143064224 # The number of ROB reads +system.cpu0.rob.rob_writes 101447849 # The number of ROB writes +system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41863465 # Number of Instructions Simulated +system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes +system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads +system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads +system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1127,49 +1120,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111935595 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 212628634 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) +system.toL2Bus.throughput 115690704 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 215700578 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1431950 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53869 # Transaction distribution -system.iobus.trans_dist::WriteResp 53869 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1434388 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7370 # Transaction distribution +system.iobus.trans_dist::ReadResp 7370 # Transaction distribution +system.iobus.trans_dist::WriteReq 53903 # Transaction distribution +system.iobus.trans_dist::WriteResp 53903 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1180,12 +1174,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1196,14 +1190,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729594 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729818 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1223,267 +1217,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 993039 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits -system.cpu0.icache.overall_hits::total 7257459 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses -system.cpu0.icache.overall_misses::total 1044346 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 762211 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits +system.cpu0.icache.overall_hits::total 6309809 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses +system.cpu0.icache.overall_misses::total 800080 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1357625 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1069035 # number of replacements +system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits -system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses -system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 170256 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8817417 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8817417 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8817417 # number of overall hits +system.cpu0.dcache.overall_hits::total 8817417 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1322171 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1322171 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1644281 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1644281 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16610 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16610 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2966452 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2966452 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2966452 # number of overall misses +system.cpu0.dcache.overall_misses::total 2966452 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 36169344894 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74324803897 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 267182493 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342822 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004479 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251738 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.251738 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251738 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.251738 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks -system.cpu0.dcache.writebacks::total 808609 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks +system.cpu0.dcache.writebacks::total 568073 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1491,35 +1485,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 1483279 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits +system.cpu1.branchPred.lookups 5770916 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1187167 # DTB read hits -system.cpu1.dtb.read_misses 8989 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 276351 # DTB read accesses -system.cpu1.dtb.write_hits 628916 # DTB write hits -system.cpu1.dtb.write_misses 1890 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 104365 # DTB write accesses -system.cpu1.dtb.data_hits 1816083 # DTB hits -system.cpu1.dtb.data_misses 10879 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 380716 # DTB accesses -system.cpu1.itb.fetch_hits 316911 # ITB hits -system.cpu1.itb.fetch_misses 5517 # ITB misses -system.cpu1.itb.fetch_acv 125 # ITB acv -system.cpu1.itb.fetch_accesses 322428 # ITB accesses +system.cpu1.dtb.read_hits 3015540 # DTB read hits +system.cpu1.dtb.read_misses 12269 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 293761 # DTB read accesses +system.cpu1.dtb.write_hits 1836726 # DTB write hits +system.cpu1.dtb.write_misses 2353 # DTB write misses +system.cpu1.dtb.write_acv 39 # DTB write access violations +system.cpu1.dtb.write_accesses 109652 # DTB write accesses +system.cpu1.dtb.data_hits 4852266 # DTB hits +system.cpu1.dtb.data_misses 14622 # DTB misses +system.cpu1.dtb.data_acv 44 # DTB access violations +system.cpu1.dtb.data_accesses 403413 # DTB accesses +system.cpu1.itb.fetch_hits 632341 # ITB hits +system.cpu1.itb.fetch_misses 5352 # ITB misses +system.cpu1.itb.fetch_acv 51 # ITB acv +system.cpu1.itb.fetch_accesses 637693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1532,553 +1526,554 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 8637240 # number of cpu cycles simulated +system.cpu1.numCycles 26335588 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued -system.cpu1.iq.rate 0.618450 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued +system.cpu1.iq.rate 0.598374 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 221139 # number of nop insts executed -system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed -system.cpu1.iew.exec_branches 762873 # Number of branches executed -system.cpu1.iew.exec_stores 633845 # Number of stores executed -system.cpu1.iew.exec_rate 0.612230 # Inst execution rate -system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 2532511 # num instructions producing a value -system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value +system.cpu1.iew.exec_nop 1012523 # number of nop insts executed +system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2446532 # Number of branches executed +system.cpu1.iew.exec_stores 1845237 # Number of stores executed +system.cpu1.iew.exec_rate 0.590834 # Inst execution rate +system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7566791 # num instructions producing a value +system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 4954074 # Number of instructions committed -system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15127070 # Number of instructions committed +system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1585273 # Number of memory references committed -system.cpu1.commit.loads 996375 # Number of loads committed -system.cpu1.commit.membars 16576 # Number of memory barriers committed -system.cpu1.commit.branches 700739 # Number of branches committed -system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. -system.cpu1.commit.function_calls 77324 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction +system.cpu1.commit.refs 4418203 # Number of memory references committed +system.cpu1.commit.loads 2674883 # Number of loads committed +system.cpu1.commit.membars 66521 # Number of memory barriers committed +system.cpu1.commit.branches 2263870 # Number of branches committed +system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. +system.cpu1.commit.function_calls 240978 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction -system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction +system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 13715407 # The number of ROB reads -system.cpu1.rob.rob_writes 12215098 # The number of ROB writes -system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 4765602 # Number of Instructions Simulated -system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads -system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes -system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes -system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads -system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes -system.cpu1.icache.tags.replacements 94727 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 41251186 # The number of ROB reads +system.cpu1.rob.rob_writes 36287802 # The number of ROB writes +system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14284756 # Number of Instructions Simulated +system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads +system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads +system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads +system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes +system.cpu1.icache.tags.replacements 353746 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits -system.cpu1.icache.overall_hits::total 794363 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses -system.cpu1.icache.overall_misses::total 99697 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits +system.cpu1.icache.overall_hits::total 2153244 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses +system.cpu1.icache.overall_misses::total 368891 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 45361 # number of replacements -system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits -system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses -system.cpu1.dcache.overall_misses::total 176847 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # 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number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 360788 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3528381 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3528381 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3528381 # number of overall hits +system.cpu1.dcache.overall_hits::total 3528381 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 524895 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 524895 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 378889 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 378889 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8897 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8897 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 903784 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 903784 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 903784 # number of overall misses +system.cpu1.dcache.overall_misses::total 903784 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8191623763 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 14087810149 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 135761491 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks -system.cpu1.dcache.writebacks::total 24956 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 273838 # number of writebacks +system.cpu1.dcache.writebacks::total 273838 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 229504 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 313811 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2087,161 +2082,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed -system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed -system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 187581 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed +system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 146768 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3931 # number of times the context was actually changed +system.cpu0.kern.swap_context 2906 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed -system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed -system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed -system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed +system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed +system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 28623 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 386 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 19 -system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 69486 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 67 +system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 299 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1335 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f07e7eac0..6fda1994e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860172 # Number of seconds simulated -sim_ticks 1860172195000 # Number of ticks simulated -final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860009 # Number of seconds simulated +sim_ticks 1860008936000 # Number of ticks simulated +final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152063 # Simulator instruction rate (inst/s) -host_op_rate 152063 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5340733222 # Simulator tick rate (ticks/s) -host_mem_usage 304984 # Number of bytes of host memory used -host_seconds 348.30 # Real time elapsed on the host -sim_insts 52963419 # Number of instructions simulated -sim_ops 52963419 # Number of ops (including micro ops) simulated +host_inst_rate 106543 # Simulator instruction rate (inst/s) +host_op_rate 106543 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3740252336 # Simulator tick rate (ticks/s) +host_mem_usage 320492 # Number of bytes of host memory used +host_seconds 497.30 # Real time elapsed on the host +sim_insts 52983264 # Number of instructions simulated +sim_ops 52983264 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445258 # Number of read requests accepted -system.physmem.writeReqs 117433 # Number of write requests accepted -system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404216 # Number of read requests accepted +system.physmem.writeReqs 117584 # Number of write requests accepted +system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28223 # Per bank write bursts -system.physmem.perBankRdBursts::1 27968 # Per bank write bursts -system.physmem.perBankRdBursts::2 28292 # Per bank write bursts -system.physmem.perBankRdBursts::3 27927 # Per bank write bursts -system.physmem.perBankRdBursts::4 27805 # Per bank write bursts -system.physmem.perBankRdBursts::5 27242 # Per bank write bursts -system.physmem.perBankRdBursts::6 27352 # Per bank write bursts -system.physmem.perBankRdBursts::7 27274 # Per bank write bursts -system.physmem.perBankRdBursts::8 27691 # Per bank write bursts -system.physmem.perBankRdBursts::9 27508 # Per bank write bursts -system.physmem.perBankRdBursts::10 27933 # Per bank write bursts -system.physmem.perBankRdBursts::11 27527 # Per bank write bursts -system.physmem.perBankRdBursts::12 27552 # Per bank write bursts -system.physmem.perBankRdBursts::13 28225 # Per bank write bursts -system.physmem.perBankRdBursts::14 28330 # Per bank write bursts -system.physmem.perBankRdBursts::15 28314 # Per bank write bursts -system.physmem.perBankWrBursts::0 7932 # Per bank write bursts -system.physmem.perBankWrBursts::1 7496 # Per bank write bursts -system.physmem.perBankWrBursts::2 7821 # Per bank write bursts -system.physmem.perBankWrBursts::3 7427 # Per bank write bursts -system.physmem.perBankWrBursts::4 7353 # Per bank write bursts -system.physmem.perBankWrBursts::5 6703 # Per bank write bursts -system.physmem.perBankWrBursts::6 6854 # Per bank write bursts -system.physmem.perBankWrBursts::7 6665 # Per bank write bursts -system.physmem.perBankWrBursts::8 7118 # Per bank write bursts -system.physmem.perBankWrBursts::9 6889 # Per bank write bursts -system.physmem.perBankWrBursts::10 7323 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7116 # Per bank write bursts -system.physmem.perBankWrBursts::13 7874 # Per bank write bursts -system.physmem.perBankWrBursts::14 8055 # Per bank write bursts -system.physmem.perBankWrBursts::15 7794 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25622 # Per bank write bursts +system.physmem.perBankRdBursts::1 25451 # Per bank write bursts +system.physmem.perBankRdBursts::2 25608 # Per bank write bursts +system.physmem.perBankRdBursts::3 25528 # Per bank write bursts +system.physmem.perBankRdBursts::4 25399 # Per bank write bursts +system.physmem.perBankRdBursts::5 24757 # Per bank write bursts +system.physmem.perBankRdBursts::6 24940 # Per bank write bursts +system.physmem.perBankRdBursts::7 25074 # Per bank write bursts +system.physmem.perBankRdBursts::8 24966 # Per bank write bursts +system.physmem.perBankRdBursts::9 25053 # Per bank write bursts +system.physmem.perBankRdBursts::10 25586 # Per bank write bursts +system.physmem.perBankRdBursts::11 24884 # Per bank write bursts +system.physmem.perBankRdBursts::12 24485 # Per bank write bursts +system.physmem.perBankRdBursts::13 25285 # Per bank write bursts +system.physmem.perBankRdBursts::14 25789 # Per bank write bursts +system.physmem.perBankRdBursts::15 25616 # Per bank write bursts +system.physmem.perBankWrBursts::0 7925 # Per bank write bursts +system.physmem.perBankWrBursts::1 7509 # Per bank write bursts +system.physmem.perBankWrBursts::2 7974 # Per bank write bursts +system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::4 7335 # Per bank write bursts +system.physmem.perBankWrBursts::5 6682 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 6701 # Per bank write bursts +system.physmem.perBankWrBursts::8 7135 # Per bank write bursts +system.physmem.perBankWrBursts::9 6719 # Per bank write bursts +system.physmem.perBankWrBursts::10 7431 # Per bank write bursts +system.physmem.perBankWrBursts::11 6970 # Per bank write bursts +system.physmem.perBankWrBursts::12 7113 # Per bank write bursts +system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::14 8065 # Per bank write bursts +system.physmem.perBankWrBursts::15 7817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 1860166839000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 1860003602000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445258 # Read request sizes (log2) +system.physmem.readPktSize::6 404216 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117433 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117584 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -148,282 +151,273 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1276 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6916 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads -system.physmem.totQLat 8740437500 # Total ticks spent queuing -system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads +system.physmem.totQLat 3626109250 # Total ticks spent queuing +system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing -system.physmem.readRowHits 403028 # Number of row buffer hits during reads -system.physmem.writeRowHits 95855 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes -system.physmem.avgGap 3305840.75 # Average gap between requests -system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states -system.physmem.memoryStateTime::REF 62115040000 # Time in different power states +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing +system.physmem.readRowHits 364992 # Number of row buffer hits during reads +system.physmem.writeRowHits 95512 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes +system.physmem.avgGap 3564591.03 # Average gap between requests +system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states +system.physmem.memoryStateTime::REF 62109580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states +system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19402477 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295985 # Transaction distribution -system.membus.trans_dist::ReadResp 295900 # Transaction distribution -system.membus.trans_dist::WriteReq 9597 # Transaction distribution -system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117433 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179 # Transaction distribution -system.membus.trans_dist::ReadExReq 156844 # Transaction distribution -system.membus.trans_dist::ReadExResp 156844 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36056364 # Total data (bytes) -system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks) +system.membus.throughput 17983494 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296097 # Transaction distribution +system.membus.trans_dist::ReadResp 296008 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::Writeback 76032 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 207 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 213 # Transaction distribution +system.membus.trans_dist::ReadExReq 115296 # Transaction distribution +system.membus.trans_dist::ReadExResp 115296 # Transaction distribution +system.membus.trans_dist::BadAddressError 89 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33439348 # Total data (bytes) +system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 376037 # Number of tag accesses +system.iocache.tags.data_accesses 376037 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles +system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -437,36 +431,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13973676 # Number of BP lookups -system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits +system.cpu.branchPred.lookups 17833670 # Number of BP lookups +system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10112222 # DTB read hits -system.cpu.dtb.read_misses 41745 # DTB read misses -system.cpu.dtb.read_acv 542 # DTB read access violations -system.cpu.dtb.read_accesses 945441 # DTB read accesses -system.cpu.dtb.write_hits 6611008 # DTB write hits -system.cpu.dtb.write_misses 10791 # DTB write misses -system.cpu.dtb.write_acv 413 # DTB write access violations -system.cpu.dtb.write_accesses 339727 # DTB write accesses -system.cpu.dtb.data_hits 16723230 # DTB hits -system.cpu.dtb.data_misses 52536 # DTB misses -system.cpu.dtb.data_acv 955 # DTB access violations -system.cpu.dtb.data_accesses 1285168 # DTB accesses -system.cpu.itb.fetch_hits 1309723 # ITB hits -system.cpu.itb.fetch_misses 39683 # ITB misses -system.cpu.itb.fetch_acv 1073 # ITB acv -system.cpu.itb.fetch_accesses 1349406 # ITB accesses +system.cpu.dtb.read_hits 10317598 # DTB read hits +system.cpu.dtb.read_misses 42841 # DTB read misses +system.cpu.dtb.read_acv 498 # DTB read access violations +system.cpu.dtb.read_accesses 968680 # DTB read accesses +system.cpu.dtb.write_hits 6661505 # DTB write hits +system.cpu.dtb.write_misses 9470 # DTB write misses +system.cpu.dtb.write_acv 409 # DTB write access violations +system.cpu.dtb.write_accesses 342844 # DTB write accesses +system.cpu.dtb.data_hits 16979103 # DTB hits +system.cpu.dtb.data_misses 52311 # DTB misses +system.cpu.dtb.data_acv 907 # DTB access violations +system.cpu.dtb.data_accesses 1311524 # DTB accesses +system.cpu.itb.fetch_hits 1772041 # ITB hits +system.cpu.itb.fetch_misses 34420 # ITB misses +system.cpu.itb.fetch_acv 658 # ITB acv +system.cpu.itb.fetch_accesses 1806461 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -479,255 +473,256 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121578156 # number of cpu cycles simulated +system.cpu.numCycles 118354133 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued -system.cpu.iq.rate 0.470676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued +system.cpu.iq.rate 0.487234 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3575705 # number of nop insts executed -system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed -system.cpu.iew.exec_branches 8947461 # Number of branches executed -system.cpu.iew.exec_stores 6637036 # Number of stores executed -system.cpu.iew.exec_rate 0.466251 # Inst execution rate -system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28606216 # num instructions producing a value -system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value +system.cpu.iew.exec_nop 3710734 # number of nop insts executed +system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed +system.cpu.iew.exec_branches 8987700 # Number of branches executed +system.cpu.iew.exec_stores 6686076 # Number of stores executed +system.cpu.iew.exec_rate 0.482265 # Inst execution rate +system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28961590 # num instructions producing a value +system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56153459 # Number of instructions committed -system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56174099 # Number of instructions committed +system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15466309 # Number of memory references committed -system.cpu.commit.loads 9089766 # Number of loads committed -system.cpu.commit.membars 226357 # Number of memory barriers committed -system.cpu.commit.branches 8438044 # Number of branches committed -system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52003822 # Number of committed integer instructions. -system.cpu.commit.function_calls 740374 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction +system.cpu.commit.refs 15471950 # Number of memory references committed +system.cpu.commit.loads 9093334 # Number of loads committed +system.cpu.commit.membars 226345 # Number of memory barriers committed +system.cpu.commit.branches 8441019 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52023449 # Number of committed integer instructions. +system.cpu.commit.function_calls 740634 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction @@ -753,30 +748,30 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction -system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction +system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141112277 # The number of ROB reads -system.cpu.rob.rob_writes 130308588 # The number of ROB writes -system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52963419 # Number of Instructions Simulated -system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads -system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74250743 # number of integer regfile reads -system.cpu.int_regfile_writes 40442410 # number of integer regfile writes -system.cpu.fp_regfile_reads 166399 # number of floating regfile reads -system.cpu.fp_regfile_writes 167429 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads -system.cpu.misc_regfile_writes 938976 # number of misc regfile writes +system.cpu.rob.rob_reads 173614429 # The number of ROB reads +system.cpu.rob.rob_writes 130369620 # The number of ROB writes +system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52983264 # Number of Instructions Simulated +system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74755796 # number of integer regfile reads +system.cpu.int_regfile_writes 40630218 # number of integer regfile writes +system.cpu.fp_regfile_reads 167440 # number of floating regfile reads +system.cpu.fp_regfile_writes 167913 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads +system.cpu.misc_regfile_writes 939431 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -808,12 +803,13 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454569 # Throughput (bytes/s) +system.iobus.throughput 1454701 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 51149 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51086 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -825,11 +821,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -841,12 +837,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705748 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705756 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -868,245 +864,250 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1008400 # number of replacements -system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1036559 # number of replacements +system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9663349 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9663349 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7589402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7589402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7589402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7589402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7589402 # number of overall hits -system.cpu.icache.overall_hits::total 7589402 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1064815 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1064815 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1064815 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1064815 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1064815 # number of overall misses -system.cpu.icache.overall_misses::total 1064815 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14788071318 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14788071318 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14788071318 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14788071318 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14788071318 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14788071318 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8654217 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8654217 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8654217 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8654217 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8654217 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8654217 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123040 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123040 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123040 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123040 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123040 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123040 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13887.925431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13887.925431 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4640 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits +system.cpu.icache.overall_hits::total 7968979 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses +system.cpu.icache.overall_misses::total 1088360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.494505 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55683 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55683 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55683 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55683 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55683 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55683 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009132 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1009132 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1009132 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1009132 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1009132 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1009132 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12130132326 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12130132326 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12130132326 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12130132326 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12130132326 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12130132326 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116606 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116606 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116606 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338319 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65340.875442 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2545143 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.307884 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5540956750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5321.183862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6177.356806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821569 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081195 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55469 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26719739 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26719739 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 993934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1821083 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840753 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840753 # number of Writeback hits +system.cpu.l2cache.tags.replacements 338424 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.396863 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 64006618 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 64006618 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7294645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7294645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4192085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4192085 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186406 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186406 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215722 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215722 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11486730 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11486730 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11486730 # number of overall hits +system.cpu.dcache.overall_hits::total 11486730 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1781450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1781450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1956078 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1956078 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23435 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23435 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3737528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3737528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3737528 # number of overall misses +system.cpu.dcache.overall_misses::total 3737528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39460898751 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39460898751 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77926098572 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77926098572 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 366682499 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 366682499 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 440006 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 440006 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117386997323 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117386997323 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117386997323 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117386997323 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9076095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9076095 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6148163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6148163 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209841 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209841 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215750 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15224258 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15224258 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15224258 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15224258 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.196279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318156 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318156 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245498 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245498 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245498 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245498 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22150.999888 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22150.999888 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39837.930068 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39837.930068 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15646.788948 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15646.788948 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15714.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15714.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31407.656966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31407.656966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31407.656966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3974317 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2076 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 180350 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 21 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.036690 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840753 # number of writebacks -system.cpu.dcache.writebacks::total 840753 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705849 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 705849 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1648446 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1648446 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5839 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5839 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2354295 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks +system.cpu.dcache.writebacks::total 845214 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1366,28 +1367,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1423,32 +1424,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191975 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.callpal::total 191967 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index de36b122c..6a79f5850 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842688 # Number of seconds simulated -sim_ticks 1842688380000 # Number of ticks simulated -final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841612 # Number of seconds simulated +sim_ticks 1841612285000 # Number of ticks simulated +final_tick 1841612285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219315 # Simulator instruction rate (inst/s) -host_op_rate 219315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5608158508 # Simulator tick rate (ticks/s) -host_mem_usage 303992 # Number of bytes of host memory used -host_seconds 328.57 # Real time elapsed on the host -sim_insts 72060922 # Number of instructions simulated -sim_ops 72060922 # Number of ops (including micro ops) simulated +host_inst_rate 168459 # Simulator instruction rate (inst/s) +host_op_rate 168459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4750760669 # Simulator tick rate (ticks/s) +host_mem_usage 319468 # Number of bytes of host memory used +host_seconds 387.65 # Real time elapsed on the host +sim_insts 65302548 # Number of instructions simulated +sim_ops 65302548 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98062 # Number of read requests accepted -system.physmem.writeReqs 44473 # Number of write requests accepted -system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue -system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 475840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19999104 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2248128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2645376 # Number of bytes read from this memory +system.physmem.bytes_read::total 25815040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 475840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4825408 # Number of bytes written to this memory +system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory +system.physmem.bytes_written::total 7484736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312486 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41334 # Number of read requests responded to by this memory +system.physmem.num_reads::total 403360 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75397 # Number of write requests responded to by this memory +system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116949 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 258382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10859563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1220739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 162154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1436446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14017630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 258382 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 162154 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 500362 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2620208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064230 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2620208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10859563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1220739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 162154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1436446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18081860 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83439 # Number of read requests accepted +system.physmem.writeReqs 46740 # Number of write requests accepted +system.physmem.readBursts 83439 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46740 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5337024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3072 # Total number of bytes read from write queue +system.physmem.bytesWritten 2989888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5340096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2991360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 48 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6096 # Per bank write bursts -system.physmem.perBankRdBursts::1 5927 # Per bank write bursts -system.physmem.perBankRdBursts::2 6222 # Per bank write bursts -system.physmem.perBankRdBursts::3 6258 # Per bank write bursts -system.physmem.perBankRdBursts::4 5693 # Per bank write bursts -system.physmem.perBankRdBursts::5 6247 # Per bank write bursts -system.physmem.perBankRdBursts::6 5971 # Per bank write bursts -system.physmem.perBankRdBursts::7 5980 # Per bank write bursts -system.physmem.perBankRdBursts::8 6426 # Per bank write bursts -system.physmem.perBankRdBursts::9 5994 # Per bank write bursts -system.physmem.perBankRdBursts::10 6527 # Per bank write bursts -system.physmem.perBankRdBursts::11 6117 # Per bank write bursts -system.physmem.perBankRdBursts::12 5881 # Per bank write bursts -system.physmem.perBankRdBursts::13 6322 # Per bank write bursts -system.physmem.perBankRdBursts::14 6340 # Per bank write bursts -system.physmem.perBankRdBursts::15 6043 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2556 # Per bank write bursts -system.physmem.perBankWrBursts::2 2841 # Per bank write bursts -system.physmem.perBankWrBursts::3 3001 # Per bank write bursts -system.physmem.perBankWrBursts::4 2678 # Per bank write bursts -system.physmem.perBankWrBursts::5 2962 # Per bank write bursts -system.physmem.perBankWrBursts::6 2867 # Per bank write bursts -system.physmem.perBankWrBursts::7 2601 # Per bank write bursts -system.physmem.perBankWrBursts::8 3150 # Per bank write bursts -system.physmem.perBankWrBursts::9 2533 # Per bank write bursts -system.physmem.perBankWrBursts::10 3049 # Per bank write bursts -system.physmem.perBankWrBursts::11 2640 # Per bank write bursts -system.physmem.perBankWrBursts::12 2384 # Per bank write bursts -system.physmem.perBankWrBursts::13 2771 # Per bank write bursts -system.physmem.perBankWrBursts::14 2950 # Per bank write bursts -system.physmem.perBankWrBursts::15 2744 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 52 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5256 # Per bank write bursts +system.physmem.perBankRdBursts::1 5087 # Per bank write bursts +system.physmem.perBankRdBursts::2 5115 # Per bank write bursts +system.physmem.perBankRdBursts::3 5179 # Per bank write bursts +system.physmem.perBankRdBursts::4 5173 # Per bank write bursts +system.physmem.perBankRdBursts::5 5205 # Per bank write bursts +system.physmem.perBankRdBursts::6 5267 # Per bank write bursts +system.physmem.perBankRdBursts::7 5273 # Per bank write bursts +system.physmem.perBankRdBursts::8 5423 # Per bank write bursts +system.physmem.perBankRdBursts::9 5013 # Per bank write bursts +system.physmem.perBankRdBursts::10 5464 # Per bank write bursts +system.physmem.perBankRdBursts::11 5273 # Per bank write bursts +system.physmem.perBankRdBursts::12 4813 # Per bank write bursts +system.physmem.perBankRdBursts::13 5124 # Per bank write bursts +system.physmem.perBankRdBursts::14 5602 # Per bank write bursts +system.physmem.perBankRdBursts::15 5124 # Per bank write bursts +system.physmem.perBankWrBursts::0 2825 # Per bank write bursts +system.physmem.perBankWrBursts::1 2787 # Per bank write bursts +system.physmem.perBankWrBursts::2 2858 # Per bank write bursts +system.physmem.perBankWrBursts::3 3069 # Per bank write bursts +system.physmem.perBankWrBursts::4 3024 # Per bank write bursts +system.physmem.perBankWrBursts::5 2822 # Per bank write bursts +system.physmem.perBankWrBursts::6 3224 # Per bank write bursts +system.physmem.perBankWrBursts::7 2821 # Per bank write bursts +system.physmem.perBankWrBursts::8 3331 # Per bank write bursts +system.physmem.perBankWrBursts::9 2683 # Per bank write bursts +system.physmem.perBankWrBursts::10 3131 # Per bank write bursts +system.physmem.perBankWrBursts::11 2953 # Per bank write bursts +system.physmem.perBankWrBursts::12 2475 # Per bank write bursts +system.physmem.perBankWrBursts::13 2748 # Per bank write bursts +system.physmem.perBankWrBursts::14 3227 # Per bank write bursts +system.physmem.perBankWrBursts::15 2739 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1841676054500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 1840600008500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98062 # Read request sizes (log2) +system.physmem.readPktSize::6 83439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44473 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46740 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,400 +156,398 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads -system.physmem.totQLat 2880597750 # Total ticks spent queuing -system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.758569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 220.447203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 381.120515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7019 32.60% 32.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4847 22.51% 55.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1849 8.59% 63.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1051 4.88% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 911 4.23% 72.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 506 2.35% 75.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 375 1.74% 76.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 418 1.94% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4554 21.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21530 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 40.873529 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1027.655163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2038 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.900490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.614282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.575456 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 33 1.62% 1.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 1.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 2.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.25% 2.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1695 83.09% 85.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 37 1.81% 87.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 5 0.25% 87.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 107 5.25% 92.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.34% 92.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.10% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.05% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.15% 93.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.39% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.05% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 93.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.05% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.10% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.10% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.39% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.15% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.15% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.10% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 78 3.82% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.05% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.05% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.34% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.15% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.05% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2040 # Writes before turning the bus around for reads +system.physmem.totQLat 869064750 # Total ticks spent queuing +system.physmem.totMemAccLat 2432646000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10421.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29171.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing -system.physmem.readRowHits 85382 # Number of row buffer hits during reads -system.physmem.writeRowHits 35296 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes -system.physmem.avgGap 12920868.94 # Average gap between requests -system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states -system.physmem.memoryStateTime::REF 61531340000 # Time in different power states +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing +system.physmem.readRowHits 71609 # Number of row buffer hits during reads +system.physmem.writeRowHits 36969 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes +system.physmem.avgGap 14138993.30 # Average gap between requests +system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1766589196000 # Time in different power states +system.physmem.memoryStateTime::REF 61495460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states +system.physmem.memoryStateTime::ACT 13527240250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19530148 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44582 # Transaction distribution -system.membus.trans_dist::ReadResp 44547 # Transaction distribution -system.membus.trans_dist::WriteReq 3734 # Transaction distribution -system.membus.trans_dist::WriteResp 3734 # Transaction distribution -system.membus.trans_dist::Writeback 44473 # Transaction distribution -system.membus.trans_dist::UpgradeReq 43 # Transaction distribution -system.membus.trans_dist::UpgradeResp 43 # Transaction distribution -system.membus.trans_dist::ReadExReq 56556 # Transaction distribution -system.membus.trans_dist::ReadExResp 56556 # Transaction distribution -system.membus.trans_dist::BadAddressError 35 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 190124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 70 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254144 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15652 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6962432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6978084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9137892 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35977992 # Total data (bytes) -system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12394500 # Layer occupancy (ticks) +system.membus.throughput 18112095 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44765 # Transaction distribution +system.membus.trans_dist::ReadResp 44760 # Transaction distribution +system.membus.trans_dist::WriteReq 3528 # Transaction distribution +system.membus.trans_dist::WriteResp 3528 # Transaction distribution +system.membus.trans_dist::Writeback 29460 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 17280 # Transaction distribution +system.membus.trans_dist::UpgradeReq 50 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 52 # Transaction distribution +system.membus.trans_dist::ReadExReq 41656 # Transaction distribution +system.membus.trans_dist::ReadExResp 41656 # Transaction distribution +system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 12900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 209322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 34645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 34645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 243967 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15792 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7224576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 7240368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1106880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 1106880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 8347248 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 33351936 # Total data (bytes) +system.membus.snoop_data_through_bus 3520 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11434500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 511002500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 517398750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 45000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 763523207 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 783386948 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 153153250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17911250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337462 # number of replacements -system.l2c.tags.tagsinuse 65424.483078 # Cycle average of tags in use -system.l2c.tags.total_refs 2473806 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402625 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.144194 # Average number of references to valid blocks. +system.l2c.tags.replacements 337577 # number of replacements +system.l2c.tags.tagsinuse 65421.096735 # Cycle average of tags in use +system.l2c.tags.total_refs 2486717 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402739 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.174513 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54864.362424 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2329.333896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2645.609154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 576.513665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 589.890909 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2235.608932 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2183.164099 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837164 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.040369 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034113 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033312 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998298 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 54723.362784 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2335.935658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2702.236553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 571.913553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 605.884543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2280.035703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2201.727940 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035644 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041233 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008727 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009245 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034791 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998247 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26155869 # Number of tag accesses -system.l2c.tags.data_accesses 26155869 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 519275 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 492761 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124644 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 294324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 240703 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1755062 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835893 # number of Writeback hits -system.l2c.Writeback_hits::total 835893 # number of Writeback hits +system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26259828 # Number of tag accesses +system.l2c.tags.data_accesses 26259828 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 505337 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 482025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 122124 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 80194 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 322880 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 255461 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768021 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835818 # number of Writeback hits +system.l2c.Writeback_hits::total 835818 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26300 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67701 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186935 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 519275 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 585695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109655 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 294324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 308404 # number of demand (read+write) hits -system.l2c.demand_hits::total 1941997 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 519275 # number of overall hits -system.l2c.overall_hits::cpu0.data 585695 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124644 # number of overall hits -system.l2c.overall_hits::cpu1.data 109655 # number of overall hits -system.l2c.overall_hits::cpu2.inst 294324 # number of overall hits -system.l2c.overall_hits::cpu2.data 308404 # number of overall hits -system.l2c.overall_hits::total 1941997 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7508 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238474 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16794 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4551 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17979 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287610 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 9 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # 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average ReadReq mshr uncacheable latency @@ -657,101 +666,93 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254888 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254802 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694865618000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254888 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693889914000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254802 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078425 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078425 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5047462530 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5047462530 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5056765993 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5056765993 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5056765993 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5056765993 # number of overall miss cycles +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 121473.395504 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121192.714032 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121192.714032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 149207 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11483 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.993730 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -769,22 +770,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4913708 # DTB read hits -system.cpu0.dtb.read_misses 6100 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428235 # DTB read accesses -system.cpu0.dtb.write_hits 3510172 # DTB write hits -system.cpu0.dtb.write_misses 671 # DTB write misses -system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163990 # DTB write accesses -system.cpu0.dtb.data_hits 8423880 # DTB hits -system.cpu0.dtb.data_misses 6771 # DTB misses -system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592225 # DTB accesses -system.cpu0.itb.fetch_hits 2758823 # ITB hits -system.cpu0.itb.fetch_misses 3034 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2761857 # ITB accesses +system.cpu0.dtb.read_hits 4820184 # DTB read hits +system.cpu0.dtb.read_misses 5970 # DTB read misses +system.cpu0.dtb.read_acv 109 # DTB read access violations +system.cpu0.dtb.read_accesses 427969 # DTB read accesses +system.cpu0.dtb.write_hits 3428698 # DTB write hits +system.cpu0.dtb.write_misses 674 # DTB write misses +system.cpu0.dtb.write_acv 81 # DTB write access violations +system.cpu0.dtb.write_accesses 164325 # DTB write accesses +system.cpu0.dtb.data_hits 8248882 # DTB hits +system.cpu0.dtb.data_misses 6644 # DTB misses +system.cpu0.dtb.data_acv 190 # DTB access violations +system.cpu0.dtb.data_accesses 592294 # DTB accesses +system.cpu0.itb.fetch_hits 2727685 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses +system.cpu0.itb.fetch_acv 97 # ITB acv +system.cpu0.itb.fetch_accesses 2730700 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -797,87 +798,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928196841 # number of cpu cycles simulated +system.cpu0.numCycles 929885466 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33463552 # Number of instructions committed -system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses -system.cpu0.num_func_calls 812549 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31328637 # number of integer instructions -system.cpu0.num_fp_insts 169756 # number of float instructions -system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written -system.cpu0.num_mem_refs 8454037 # number of memory refs -system.cpu0.num_load_insts 4935095 # Number of load instructions -system.cpu0.num_store_insts 3518942 # Number of store instructions -system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles -system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles -system.cpu0.Branches 5650356 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction -system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction -system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction -system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction -system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30965233 # Number of instructions committed +system.cpu0.committedOps 30965233 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28877959 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 164894 # Number of float alu accesses +system.cpu0.num_func_calls 798570 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3871145 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28877959 # number of integer instructions +system.cpu0.num_fp_insts 164894 # number of float instructions +system.cpu0.num_int_register_reads 39995093 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21215374 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85232 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86749 # number of times the floating registers were written +system.cpu0.num_mem_refs 8278255 # number of memory refs +system.cpu0.num_load_insts 4840998 # Number of load instructions +system.cpu0.num_store_insts 3437257 # Number of store instructions +system.cpu0.num_idle_cycles 908001022.276160 # Number of idle cycles +system.cpu0.num_busy_cycles 21884443.723840 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023535 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976465 # Percentage of idle cycles +system.cpu0.Branches 4926958 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1578460 5.10% 5.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 20418617 65.93% 71.02% # Class of executed instruction +system.cpu0.op_class::IntMult 31850 0.10% 71.13% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12902 0.04% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.17% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction +system.cpu0.op_class::MemRead 4971884 16.05% 87.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 3440357 11.11% 98.33% # Class of executed instruction +system.cpu0.op_class::IprAccess 516399 1.67% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33470533 # Class of executed instruction +system.cpu0.op_class::total 30972067 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818769989500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39220500 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357294000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22445011500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841611515500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -913,33 +914,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.callpal::total 192209 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 system.cpu0.kern.mode_good::user 1737 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29707694000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2577107000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809326710000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -971,460 +972,459 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110521342 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203645448 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks) +system.toL2Bus.throughput 112481926 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 825463 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 825443 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3528 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3528 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 385263 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17281 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 137914 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 137914 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 903973 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1415042 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2319015 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 28925888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 57212080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 86137968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 204476224 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2671872 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2218881500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2036319024 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2306325269 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469149 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2954 # Transaction distribution -system.iobus.trans_dist::ReadResp 2954 # Transaction distribution -system.iobus.trans_dist::WriteReq 20630 # Transaction distribution -system.iobus.trans_dist::WriteResp 20630 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707184 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.throughput 1470003 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2992 # Transaction distribution +system.iobus.trans_dist::ReadResp 2992 # Transaction distribution +system.iobus.trans_dist::WriteReq 20808 # Transaction distribution +system.iobus.trans_dist::WriteResp 20808 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 7420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2926 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 12900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47600 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 55 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 3710 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 2083 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 16 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1123168 # 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Layer utilization (%) -system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9372000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17532750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951958 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 964098 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.196429 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40281211 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964609 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.759108 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10190294250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 265.809335 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.640468 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.746626 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.519159 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126251 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016660 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121807 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023774 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016557 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016660 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121807 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023774 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016557 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016660 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121807 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023774 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136 # 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mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009724 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009724 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16160 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16160 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16160 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16160 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16160 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16160 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124421 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327585 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452006 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124421 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 327585 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452006 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124421 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 327585 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452006 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1525261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997287463 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5522548963 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1525261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997287463 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5522548963 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1525261500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997287463 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5522548963 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010954 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010954 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010954 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.866495 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.875110 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12202.290895 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.866495 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1392214 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13295925 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392726 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.546691 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1393139 # 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Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.896843 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.443174 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.657800 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509564 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345035 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63306620 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63306620 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4076279 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1084544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2409625 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7570448 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3214036 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 832568 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1295168 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5341772 # 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number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1130661 # number of overall misses -system.cpu0.dcache.overall_misses::total 2163760 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2236149750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9408423500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11644573250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1650986010 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18036124563 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19687110573 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28476000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 115371499 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 143847499 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8924184 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383049 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 877063 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1891684 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6151796 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126730 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21487 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54983 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203200 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126166 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21357 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8180929 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2059597 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4835454 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15075980 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8180929 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2059597 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4835454 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15075980 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150400 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082864 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181449 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151693 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049959 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050732 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315336 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131673 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076020 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100479 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128185 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092721 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108865 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069181 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233827 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143524 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069181 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233827 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143524 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8601.805116 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7634.812324 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 642685 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 913 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 30067 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151074 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082508 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183103 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.153289 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049890 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051112 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315634 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136183 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075656 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100592 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130361 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094049 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000163 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109341 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069141 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235171 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146316 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109341 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069141 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235171 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146316 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23147.063783 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17394.983005 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8764.089258 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37895.394695 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32350.284466 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8074.645116 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15406.369391 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 895030 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1251 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 63218 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.157835 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 113.727273 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835893 # number of writebacks -system.cpu0.dcache.writebacks::total 835893 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280644 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 280644 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507552 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 507552 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1619 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1619 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285455992 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553735990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2601199489 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4154935479 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24156000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66182251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90338251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3586353240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835818 # number of writebacks +system.cpu0.dcache.writebacks::total 835818 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 296217 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 296217 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534994 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 534994 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1640 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1640 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 831211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 831211 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 831211 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 831211 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94884 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267717 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 362601 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43578 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 94069 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137647 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2106 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6047 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8153 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 138462 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 361786 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 500248 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 138462 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 361786 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 500248 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1998980000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4480743134 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6479723134 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555929490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2922490326 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4478419816 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23542500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72865001 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96407501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 124998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 124998 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554909490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7403233460 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10958142950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554909490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7403233460 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10958142950 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342709000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592677500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320834500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419662000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740496500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 570803000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762371000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333174000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086925 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040574 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051112 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047199 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022383 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100592 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102549 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040011 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000163 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033159 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071318 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033159 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21067.619409 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.864428 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17870.119316 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35704.472211 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31067.517737 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1439,22 +1439,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1201953 # DTB read hits -system.cpu1.dtb.read_misses 1367 # DTB read misses +system.cpu1.dtb.read_hits 1168812 # DTB read hits +system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 898873 # DTB write hits -system.cpu1.dtb.write_misses 185 # DTB write misses -system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58321 # DTB write accesses -system.cpu1.dtb.data_hits 2100826 # DTB hits -system.cpu1.dtb.data_misses 1552 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201266 # DTB accesses -system.cpu1.itb.fetch_hits 861128 # ITB hits -system.cpu1.itb.fetch_misses 693 # ITB misses -system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 861821 # ITB accesses +system.cpu1.dtb.read_accesses 141647 # DTB read accesses +system.cpu1.dtb.write_hits 873733 # DTB write hits +system.cpu1.dtb.write_misses 170 # DTB write misses +system.cpu1.dtb.write_acv 22 # DTB write access violations +system.cpu1.dtb.write_accesses 57095 # DTB write accesses +system.cpu1.dtb.data_hits 2042545 # DTB hits +system.cpu1.dtb.data_misses 1495 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 198742 # DTB accesses +system.cpu1.itb.fetch_hits 849434 # ITB hits +system.cpu1.itb.fetch_misses 664 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 850098 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1467,64 +1467,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953604102 # number of cpu cycles simulated +system.cpu1.numCycles 953402608 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7738659 # Number of instructions committed -system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses -system.cpu1.num_func_calls 212104 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7195320 # number of integer instructions -system.cpu1.num_fp_insts 44971 # number of float instructions -system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written -system.cpu1.num_mem_refs 2108049 # number of memory refs -system.cpu1.num_load_insts 1206835 # Number of load instructions -system.cpu1.num_store_insts 901214 # Number of store instructions -system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles -system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles -system.cpu1.Branches 1227675 # Number of branches fetched -system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction -system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction -system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction -system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction -system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7466514 # Number of instructions committed +system.cpu1.committedOps 7466514 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6940405 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43972 # Number of float alu accesses +system.cpu1.num_func_calls 203873 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 905018 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6940405 # number of integer instructions +system.cpu1.num_fp_insts 43972 # number of float instructions +system.cpu1.num_int_register_reads 9656232 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5062933 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23750 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written +system.cpu1.num_mem_refs 2049510 # number of memory refs +system.cpu1.num_load_insts 1173515 # Number of load instructions +system.cpu1.num_store_insts 875995 # Number of store instructions +system.cpu1.num_idle_cycles 923975227.132686 # Number of idle cycles +system.cpu1.num_busy_cycles 29427380.867314 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles +system.cpu1.Branches 1173577 # Number of branches fetched +system.cpu1.op_class::No_OpClass 399506 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4845173 64.88% 70.23% # Class of executed instruction +system.cpu1.op_class::IntMult 8216 0.11% 70.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5112 0.07% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::MemRead 1201694 16.09% 86.51% # Class of executed instruction +system.cpu1.op_class::MemWrite 877208 11.75% 98.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 130346 1.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7740268 # Class of executed instruction +system.cpu1.op_class::total 7468065 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1542,35 +1542,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8997141 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits +system.cpu2.branchPred.lookups 9007020 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8266685 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6913379 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 4889018 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.718212 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 301119 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7670 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3232647 # DTB read hits -system.cpu2.dtb.read_misses 11674 # DTB read misses -system.cpu2.dtb.read_acv 117 # DTB read access violations -system.cpu2.dtb.read_accesses 217551 # DTB read accesses -system.cpu2.dtb.write_hits 2020818 # DTB write hits -system.cpu2.dtb.write_misses 2669 # DTB write misses -system.cpu2.dtb.write_acv 109 # DTB write access violations -system.cpu2.dtb.write_accesses 82591 # DTB write accesses -system.cpu2.dtb.data_hits 5253465 # DTB hits -system.cpu2.dtb.data_misses 14343 # DTB misses -system.cpu2.dtb.data_acv 226 # DTB access violations -system.cpu2.dtb.data_accesses 300142 # DTB accesses -system.cpu2.itb.fetch_hits 371576 # ITB hits -system.cpu2.itb.fetch_misses 5695 # ITB misses -system.cpu2.itb.fetch_acv 235 # ITB acv -system.cpu2.itb.fetch_accesses 377271 # ITB accesses +system.cpu2.dtb.read_hits 3485225 # DTB read hits +system.cpu2.dtb.read_misses 12620 # DTB read misses +system.cpu2.dtb.read_acv 152 # DTB read access violations +system.cpu2.dtb.read_accesses 227645 # DTB read accesses +system.cpu2.dtb.write_hits 2140940 # DTB write hits +system.cpu2.dtb.write_misses 2817 # DTB write misses +system.cpu2.dtb.write_acv 139 # DTB write access violations +system.cpu2.dtb.write_accesses 85106 # DTB write accesses +system.cpu2.dtb.data_hits 5626165 # DTB hits +system.cpu2.dtb.data_misses 15437 # DTB misses +system.cpu2.dtb.data_acv 291 # DTB access violations +system.cpu2.dtb.data_accesses 312751 # DTB accesses +system.cpu2.itb.fetch_hits 539657 # ITB hits +system.cpu2.itb.fetch_misses 5944 # ITB misses +system.cpu2.itb.fetch_acv 165 # ITB acv +system.cpu2.itb.fetch_accesses 545601 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1583,305 +1583,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31002313 # number of cpu cycles simulated +system.cpu2.numCycles 29515720 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9404916 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 35474807 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9007020 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5190137 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18003717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 410566 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 517 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1999 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 235781 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 98995 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 442 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2822037 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92550 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27961187 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.268716 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.388099 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20241670 72.39% 72.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312691 1.12% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 474251 1.70% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3278987 11.73% 86.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 837934 3.00% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194435 0.70% 90.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 239683 0.86% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 437644 1.57% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1943892 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27961187 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.305160 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.201895 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7704419 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13193149 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6090024 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 535254 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 192290 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 176132 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13346 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 32094888 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42715 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 192290 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7987526 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4830275 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6354829 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6312082 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2038145 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 31271508 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68877 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 405466 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 55957 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 963204 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 20931686 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 38638449 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 38578281 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56251 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 19026086 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1905600 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 533120 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63723 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3942739 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3510198 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2234995 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 462280 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329256 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 28739879 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 680947 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 28391596 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 17529 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2438506 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487021 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27961187 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.015393 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.594251 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17574861 62.85% 62.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2788082 9.97% 72.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1379347 4.93% 77.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4037262 14.44% 92.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1018579 3.64% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 572705 2.05% 97.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 385941 1.38% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 155733 0.56% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48677 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27961187 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 82533 21.35% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 178965 46.29% 67.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 125088 32.36% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 22261960 78.41% 78.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21111 0.07% 78.49% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20516 0.07% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3614417 12.73% 91.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2165470 7.63% 98.93% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 304438 1.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued -system.cpu2.iq.rate 1.036715 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 28391596 # Type of FU issued +system.cpu2.iq.rate 0.961914 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386586 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013616 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 84894790 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 31745632 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27810644 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253704 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119619 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117118 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 28639647 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136079 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206810 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 438537 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1486 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6057 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 183313 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5003 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 177760 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 192290 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4010862 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 349296 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 30806306 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 54542 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3510198 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2234995 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606167 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15566 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 285460 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6057 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62858 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135105 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197963 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 28193561 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3506622 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 198035 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1285472 # number of nop insts executed -system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7393667 # Number of branches executed -system.cpu2.iew.exec_stores 2027934 # Number of stores executed -system.cpu2.iew.exec_rate 1.031389 # Inst execution rate -system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18729651 # num instructions producing a value -system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value +system.cpu2.iew.exec_nop 1385480 # number of nop insts executed +system.cpu2.iew.exec_refs 5655108 # number of memory reference insts executed +system.cpu2.iew.exec_branches 5954900 # Number of branches executed +system.cpu2.iew.exec_stores 2148486 # Number of stores executed +system.cpu2.iew.exec_rate 0.955205 # Inst execution rate +system.cpu2.iew.wb_sent 27969918 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27927762 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15888662 # num instructions producing a value +system.cpu2.iew.wb_consumers 19538696 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.946200 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.813189 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2672008 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193926 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 180997 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27494343 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.021637 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.858517 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18377188 66.84% 66.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2251123 8.19% 75.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1180007 4.29% 79.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 3743706 13.62% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 543464 1.98% 94.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201872 0.73% 95.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 166281 0.60% 96.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179533 0.65% 96.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 851169 3.10% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32028137 # Number of instructions committed -system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27494343 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 28089240 # Number of instructions committed +system.cpu2.commit.committedOps 28089240 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4895422 # Number of memory references committed -system.cpu2.commit.loads 2948538 # Number of loads committed -system.cpu2.commit.membars 64184 # Number of memory barriers committed -system.cpu2.commit.branches 7237241 # Number of branches committed -system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229570 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5123343 # Number of memory references committed +system.cpu2.commit.loads 3071661 # Number of loads committed +system.cpu2.commit.membars 68272 # Number of memory barriers committed +system.cpu2.commit.branches 5784239 # Number of branches committed +system.cpu2.commit.fp_insts 115390 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 26574373 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240380 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1220895 4.35% 4.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 21328709 75.93% 80.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.35% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20067 0.07% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3139933 11.18% 91.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2053319 7.31% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 304438 1.08% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction -system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 28089240 # Class of committed instruction +system.cpu2.commit.bw_lim_events 851169 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 60296509 # The number of ROB reads -system.cpu2.rob.rob_writes 69467378 # The number of ROB writes -system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 30858711 # Number of Instructions Simulated -system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads -system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes +system.cpu2.rob.rob_reads 57327258 # The number of ROB reads +system.cpu2.rob.rob_writes 61989353 # The number of ROB writes +system.cpu2.timesIdled 175568 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1554533 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746289037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 26870801 # Number of Instructions Simulated +system.cpu2.committedOps 26870801 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.098431 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.098431 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.910389 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.910389 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 36957190 # number of integer regfile reads +system.cpu2.int_regfile_writes 19824047 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70953 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70972 # number of floating regfile writes +system.cpu2.misc_regfile_reads 3637810 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273227 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index d5447172f..4b75ac871 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,143 +1,143 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.146775 # Number of seconds simulated -sim_ticks 1146774863500 # Number of ticks simulated -final_tick 1146774863500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.145505 # Number of seconds simulated +sim_ticks 1145504982000 # Number of ticks simulated +final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52366 # Simulator instruction rate (inst/s) -host_op_rate 67406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 970268509 # Simulator tick rate (ticks/s) -host_mem_usage 448492 # Number of bytes of host memory used -host_seconds 1181.92 # Real time elapsed on the host -sim_insts 61892059 # Number of instructions simulated -sim_ops 79667620 # Number of ops (including micro ops) simulated +host_inst_rate 75061 # Simulator instruction rate (inst/s) +host_op_rate 90396 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1390275818 # Simulator tick rate (ticks/s) +host_mem_usage 476724 # Number of bytes of host memory used +host_seconds 823.94 # Real time elapsed on the host +sim_insts 61845931 # Number of instructions simulated +sim_ops 74481224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7022076 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3606712 # Number of bytes read from this memory -system.physmem.bytes_read::total 60963700 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 275840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1039744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4294592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory +system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7321936 # Number of bytes written to this memory +system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 109794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56383 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457684 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823939 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43889738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 2232 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 6123326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3145092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53161001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 666132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 240535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 906668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3744930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 14824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 2625052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6384807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3744930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43889738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 6138150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5770144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59545808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6457684 # Number of read requests accepted -system.physmem.writeReqs 823939 # Number of write requests accepted -system.physmem.readBursts 6457684 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823939 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 413268352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7334336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 60963700 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7321936 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 366 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709320 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12375 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 403317 # Per bank write bursts -system.physmem.perBankRdBursts::1 403674 # Per bank write bursts -system.physmem.perBankRdBursts::2 403089 # Per bank write bursts -system.physmem.perBankRdBursts::3 403454 # Per bank write bursts -system.physmem.perBankRdBursts::4 406236 # Per bank write bursts -system.physmem.perBankRdBursts::5 403730 # Per bank write bursts -system.physmem.perBankRdBursts::6 403529 # Per bank write bursts -system.physmem.perBankRdBursts::7 403381 # Per bank write bursts -system.physmem.perBankRdBursts::8 403672 # Per bank write bursts -system.physmem.perBankRdBursts::9 404158 # Per bank write bursts -system.physmem.perBankRdBursts::10 403104 # Per bank write bursts -system.physmem.perBankRdBursts::11 402562 # Per bank write bursts -system.physmem.perBankRdBursts::12 403651 # Per bank write bursts -system.physmem.perBankRdBursts::13 403575 # Per bank write bursts -system.physmem.perBankRdBursts::14 403252 # Per bank write bursts -system.physmem.perBankRdBursts::15 402934 # Per bank write bursts -system.physmem.perBankWrBursts::0 7008 # Per bank write bursts -system.physmem.perBankWrBursts::1 7418 # Per bank write bursts -system.physmem.perBankWrBursts::2 6865 # Per bank write bursts -system.physmem.perBankWrBursts::3 7084 # Per bank write bursts -system.physmem.perBankWrBursts::4 7615 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 7325 # Per bank write bursts -system.physmem.perBankWrBursts::7 7167 # Per bank write bursts -system.physmem.perBankWrBursts::8 7323 # Per bank write bursts -system.physmem.perBankWrBursts::9 7753 # Per bank write bursts -system.physmem.perBankWrBursts::10 6901 # Per bank write bursts -system.physmem.perBankWrBursts::11 6492 # Per bank write bursts -system.physmem.perBankWrBursts::12 7387 # Per bank write bursts -system.physmem.perBankWrBursts::13 7157 # Per bank write bursts -system.physmem.perBankWrBursts::14 7029 # Per bank write bursts -system.physmem.perBankWrBursts::15 6775 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6457305 # Number of read requests accepted +system.physmem.writeReqs 823729 # Number of write requests accepted +system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 403300 # Per bank write bursts +system.physmem.perBankRdBursts::1 403658 # Per bank write bursts +system.physmem.perBankRdBursts::2 403038 # Per bank write bursts +system.physmem.perBankRdBursts::3 403410 # Per bank write bursts +system.physmem.perBankRdBursts::4 406147 # Per bank write bursts +system.physmem.perBankRdBursts::5 403703 # Per bank write bursts +system.physmem.perBankRdBursts::6 403511 # Per bank write bursts +system.physmem.perBankRdBursts::7 403334 # Per bank write bursts +system.physmem.perBankRdBursts::8 403656 # Per bank write bursts +system.physmem.perBankRdBursts::9 404136 # Per bank write bursts +system.physmem.perBankRdBursts::10 403079 # Per bank write bursts +system.physmem.perBankRdBursts::11 402530 # Per bank write bursts +system.physmem.perBankRdBursts::12 403635 # Per bank write bursts +system.physmem.perBankRdBursts::13 403544 # Per bank write bursts +system.physmem.perBankRdBursts::14 403293 # Per bank write bursts +system.physmem.perBankRdBursts::15 402900 # Per bank write bursts +system.physmem.perBankWrBursts::0 6991 # Per bank write bursts +system.physmem.perBankWrBursts::1 7395 # Per bank write bursts +system.physmem.perBankWrBursts::2 6850 # Per bank write bursts +system.physmem.perBankWrBursts::3 7056 # Per bank write bursts +system.physmem.perBankWrBursts::4 7584 # Per bank write bursts +system.physmem.perBankWrBursts::5 7290 # Per bank write bursts +system.physmem.perBankWrBursts::6 7311 # Per bank write bursts +system.physmem.perBankWrBursts::7 7141 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts +system.physmem.perBankWrBursts::9 7743 # Per bank write bursts +system.physmem.perBankWrBursts::10 6877 # Per bank write bursts +system.physmem.perBankWrBursts::11 6465 # Per bank write bursts +system.physmem.perBankWrBursts::12 7382 # Per bank write bursts +system.physmem.perBankWrBursts::13 7153 # Per bank write bursts +system.physmem.perBankWrBursts::14 7067 # Per bank write bursts +system.physmem.perBankWrBursts::15 6768 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1146771945000 # Total gap between requests +system.physmem.totGap 1145502120500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 109 # Read request sizes (log2) -system.physmem.readPktSize::3 6291456 # Read request sizes (log2) +system.physmem.readPktSize::2 59 # Read request sizes (log2) +system.physmem.readPktSize::3 6291481 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166119 # Read request sizes (log2) +system.physmem.readPktSize::6 165765 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67103 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 558746 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 399850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 441647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 404684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 430598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1121698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1089151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1417401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 50859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 37752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 180 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66893 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -168,25 +168,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -217,66 +217,66 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 461513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 911.356100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 779.117173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 292.189115 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24977 5.41% 5.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21582 4.68% 10.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5972 1.29% 11.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2646 0.57% 11.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2555 0.55% 12.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 0.34% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4102 0.89% 13.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 979 0.21% 13.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 397126 86.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 461513 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6665 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 968.839160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26148.924018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6658 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6665 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6665 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.194149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.165520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984786 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2686 40.30% 40.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 20 0.30% 40.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3941 59.13% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 15 0.23% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6665 # Writes before turning the bus around for reads -system.physmem.totQLat 165007028750 # Total ticks spent queuing -system.physmem.totMemAccLat 286081741250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 32286590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25553.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads +system.physmem.totQLat 165525335000 # Total ticks spent queuing +system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44303.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.16 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.87 # Data bus utilization in percentage system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.54 # Average write queue length when enqueuing -system.physmem.readRowHits 6015984 # Number of row buffer hits during reads -system.physmem.writeRowHits 94420 # Number of row buffer hits during writes +system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 6016106 # Number of row buffer hits during reads +system.physmem.writeRowHits 94363 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.38 # Row buffer hit rate for writes -system.physmem.avgGap 157488.51 # Average gap between requests -system.physmem.pageHitRate 92.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 908124290750 # Time in different power states -system.physmem.memoryStateTime::REF 38293320000 # Time in different power states +system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes +system.physmem.avgGap 157326.85 # Average gap between requests +system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states +system.physmem.memoryStateTime::REF 38250680000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 200357121750 # Time in different power states +system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory @@ -289,266 +289,266 @@ system.realview.nvmem.num_reads::cpu1.inst 7 # system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 614 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 614 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 614 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 61651742 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7506663 # Transaction distribution -system.membus.trans_dist::ReadResp 7506663 # Transaction distribution -system.membus.trans_dist::WriteReq 767825 # Transaction distribution -system.membus.trans_dist::WriteResp 767825 # Transaction distribution -system.membus.trans_dist::Writeback 67103 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33483 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12375 # Transaction distribution -system.membus.trans_dist::ReadExReq 137796 # Transaction distribution -system.membus.trans_dist::ReadExResp 137454 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382664 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 61688542 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7506218 # Transaction distribution +system.membus.trans_dist::ReadResp 7506218 # Transaction distribution +system.membus.trans_dist::WriteReq 767823 # Transaction distribution +system.membus.trans_dist::WriteResp 767823 # Transaction distribution +system.membus.trans_dist::Writeback 66893 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution +system.membus.trans_dist::ReadExReq 137868 # Transaction distribution +system.membus.trans_dist::ReadExResp 137512 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11280 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976707 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4371551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16954463 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17953988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20369020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 70700668 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 70700668 # Total data (bytes) +system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 70664532 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1725618000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10203000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 700000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8808401000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8866177500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4909176600 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4931588899 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 15579623500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 73595 # number of replacements -system.l2c.tags.tagsinuse 53913.869309 # Cycle average of tags in use -system.l2c.tags.total_refs 2430089 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138750 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.514155 # Average number of references to valid blocks. +system.l2c.tags.replacements 73238 # number of replacements +system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use +system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38825.506974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 30.840279 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8944.299229 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.867460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6105.354070 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.592430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000471 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.136479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.093160 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.822660 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2303 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8599 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54129 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993973 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23296068 # Number of tag accesses -system.l2c.tags.data_accesses 23296068 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 29004 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 959141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 26476 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 968677 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1995155 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576981 # number of Writeback hits -system.l2c.Writeback_hits::total 576981 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 913 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 959 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 309 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 58748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 50778 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109526 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 29004 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 1017889 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 26476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1019455 # number of demand (read+write) hits -system.l2c.demand_hits::total 2104681 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 29004 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6772 # number of overall hits -system.l2c.overall_hits::cpu0.inst 1017889 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 26476 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5085 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1019455 # number of overall hits -system.l2c.overall_hits::total 2104681 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 40 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 23040420 # Number of tag accesses +system.l2c.tags.data_accesses 23040420 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits +system.l2c.Writeback_hits::total 575172 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits +system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits +system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits +system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits +system.l2c.overall_hits::total 2074936 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16374 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9914 # number of ReadReq misses -system.l2c.ReadReq_misses::total 26339 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 4863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 4102 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8965 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 683 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 310 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 993 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 92483 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 47388 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139871 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 40 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 108857 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 57302 # number of demand (read+write) misses -system.l2c.demand_misses::total 166210 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 40 # number of overall misses +system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses +system.l2c.demand_misses::total 165786 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 108857 # number of overall misses +system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu1.inst 57302 # number of overall misses -system.l2c.overall_misses::total 166210 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 3039250 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses +system.l2c.overall_misses::total 165786 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1157856000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 661250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 747415749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1909121749 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 8211643 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 13589417 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21801060 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 673971 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2091409 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2765380 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 6321431326 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 63731.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56157.179729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 61083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59171.302882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57198.566016 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -701,62 +701,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 164548117 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 3298522 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3298521 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767825 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767825 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576981 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 32938 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 50523 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260723 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260723 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1574360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3288712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16464 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 66826 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1600801 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2571055 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13478 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62668 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9194364 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 50355392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43867388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 116176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 51198592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38125568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20340 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 105940 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 183816492 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 183816492 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4883152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5169541990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3546630183 # Layer occupancy (ticks) +system.toL2Bus.throughput 163445997 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 182407496 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2800512724 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9693493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 37783748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 3604679924 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1938501968 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 8396493 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 36187242 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45973854 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7474822 # Transaction distribution -system.iobus.trans_dist::ReadResp 7474822 # Transaction distribution +system.iobus.throughput 46024799 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution +system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution system.iobus.trans_dist::WriteReq 7966 # Transaction distribution system.iobus.trans_dist::WriteResp 7966 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -778,12 +778,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14965576 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16100 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -805,14 +805,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390012 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 52721660 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 52721660 # Total data (bytes) +system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 52721636 # Total data (bytes) system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4031000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -858,19 +858,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374698000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15850285500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6861856 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5181081 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 652173 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4714052 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3350352 # Number of BTB hits +system.cpu0.branchPred.lookups 6670288 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.071596 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 844036 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 70439 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -894,25 +894,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8249046 # DTB read hits -system.cpu0.dtb.read_misses 22426 # DTB read misses -system.cpu0.dtb.write_hits 6048331 # DTB write hits -system.cpu0.dtb.write_misses 1452 # DTB write misses +system.cpu0.dtb.read_hits 7193152 # DTB read hits +system.cpu0.dtb.read_misses 17493 # DTB read misses +system.cpu0.dtb.write_hits 6058571 # DTB write hits +system.cpu0.dtb.write_misses 1416 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1952 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1134 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 199 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 288 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8271472 # DTB read accesses -system.cpu0.dtb.write_accesses 6049783 # DTB write accesses +system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7210645 # DTB read accesses +system.cpu0.dtb.write_accesses 6059987 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14297377 # DTB hits -system.cpu0.dtb.misses 23878 # DTB misses -system.cpu0.dtb.accesses 14321255 # DTB accesses +system.cpu0.dtb.hits 13251723 # DTB hits +system.cpu0.dtb.misses 18909 # DTB misses +system.cpu0.dtb.accesses 13270632 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -934,8 +934,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 12515958 # ITB inst hits -system.cpu0.itb.inst_misses 4886 # ITB inst misses +system.cpu0.itb.inst_hits 12268451 # ITB inst hits +system.cpu0.itb.inst_misses 4809 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -944,82 +944,82 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1295 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2118 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 12520844 # ITB inst accesses -system.cpu0.itb.hits 12515958 # DTB hits -system.cpu0.itb.misses 4886 # DTB misses -system.cpu0.itb.accesses 12520844 # DTB accesses -system.cpu0.numCycles 433909161 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses +system.cpu0.itb.hits 12268451 # DTB hits +system.cpu0.itb.misses 4809 # DTB misses +system.cpu0.itb.accesses 12273260 # DTB accesses +system.cpu0.numCycles 431172708 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29915294 # Number of instructions committed -system.cpu0.committedOps 39343022 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1900672 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 39481 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 1859706962 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 14.504593 # CPI: cycles per instruction -system.cpu0.ipc 0.068944 # IPC: instructions per cycle +system.cpu0.committedInsts 29878954 # Number of instructions committed +system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 14.430649 # CPI: cycles per instruction +system.cpu0.ipc 0.069297 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50347 # number of quiesce instructions executed -system.cpu0.tickCycles 353761855 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 80147306 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 784713 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.784867 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 11728456 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 785225 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 14.936427 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10280766000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.784867 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997627 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997627 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed +system.cpu0.tickCycles 351703832 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 79468876 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 775463 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 13298912 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 13298912 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 11728456 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11728456 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 11728456 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11728456 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 11728456 # number of overall hits -system.cpu0.icache.overall_hits::total 11728456 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 785228 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 785228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 785228 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 785228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 785228 # number of overall misses -system.cpu0.icache.overall_misses::total 785228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10819127683 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10819127683 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10819127683 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10819127683 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10819127683 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10819127683 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 12513684 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12513684 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 12513684 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12513684 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 12513684 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12513684 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.062750 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.062750 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.062750 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.062750 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.062750 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.062750 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13778.326401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13778.326401 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13778.326401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13778.326401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13778.326401 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits +system.cpu0.icache.overall_hits::total 11489502 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses +system.cpu0.icache.overall_misses::total 775978 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1028,125 +1028,125 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 785228 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 785228 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 785228 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 785228 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 785228 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 785228 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9244507317 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9244507317 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9244507317 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9244507317 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9244507317 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9244507317 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171313500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171313500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171313500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 171313500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.062750 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.062750 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.062750 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.062750 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11773.023016 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11773.023016 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11773.023016 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171406750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171406750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171406750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 171406750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 332522 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.116335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12493941 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 332889 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.531853 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 236260250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.116335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967024 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.967024 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 52581205 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 52581205 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 6652234 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6652234 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 5513247 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5513247 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152467 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 152467 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153686 # 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number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 565350 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 565350 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 565350 # number of overall misses -system.cpu0.dcache.overall_misses::total 565350 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3878128215 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3878128215 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15135680350 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 15135680350 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89040000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47241681 # 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average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26077.460970 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26077.460970 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks +system.cpu0.dcache.writebacks::total 307170 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796520252 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796520252 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309642252 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309642252 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1228,15 +1228,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6346953 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4931527 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 433505 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4095605 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3083437 # Number of BTB hits +system.cpu1.branchPred.lookups 6159330 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.286484 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 663921 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 63861 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1260,25 +1260,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7581512 # DTB read hits -system.cpu1.dtb.read_misses 20239 # DTB read misses -system.cpu1.dtb.write_hits 5551171 # DTB write hits -system.cpu1.dtb.write_misses 2521 # DTB write misses +system.cpu1.dtb.read_hits 6763605 # DTB read hits +system.cpu1.dtb.read_misses 17087 # DTB read misses +system.cpu1.dtb.write_hits 5563764 # DTB write hits +system.cpu1.dtb.write_misses 2456 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2404 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 237 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601751 # DTB read accesses -system.cpu1.dtb.write_accesses 5553692 # DTB write accesses +system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6780692 # DTB read accesses +system.cpu1.dtb.write_accesses 5566220 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13132683 # DTB hits -system.cpu1.dtb.misses 22760 # DTB misses -system.cpu1.dtb.accesses 13155443 # DTB accesses +system.cpu1.dtb.hits 12327369 # DTB hits +system.cpu1.dtb.misses 19543 # DTB misses +system.cpu1.dtb.accesses 12346912 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1300,8 +1300,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 11349850 # ITB inst hits -system.cpu1.itb.inst_misses 4207 # ITB inst misses +system.cpu1.itb.inst_hits 11206823 # ITB inst hits +system.cpu1.itb.inst_misses 4156 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1310,84 +1310,84 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1191 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2046 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 11354057 # ITB inst accesses -system.cpu1.itb.hits 11349850 # DTB hits -system.cpu1.itb.misses 4207 # DTB misses -system.cpu1.itb.accesses 11354057 # DTB accesses -system.cpu1.numCycles 149527233 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses +system.cpu1.itb.hits 11206823 # DTB hits +system.cpu1.itb.misses 4156 # DTB misses +system.cpu1.itb.accesses 11210979 # DTB accesses +system.cpu1.numCycles 147611080 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31976765 # Number of instructions committed -system.cpu1.committedOps 40324598 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1783017 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 39969 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 2144960974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 4.676121 # CPI: cycles per instruction -system.cpu1.ipc 0.213852 # IPC: instructions per cycle +system.cpu1.committedInsts 31966977 # Number of instructions committed +system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 4.617611 # CPI: cycles per instruction +system.cpu1.ipc 0.216562 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40497 # number of quiesce instructions executed -system.cpu1.tickCycles 120083069 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 29444164 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 800234 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.617194 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 10546899 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 800746 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.171341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 82063984250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.617194 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938705 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938705 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed +system.cpu1.tickCycles 117794277 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 29816803 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 791766 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 12148392 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 12148392 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 10546899 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 10546899 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 10546899 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 10546899 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 10546899 # number of overall hits -system.cpu1.icache.overall_hits::total 10546899 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 800747 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 800747 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 800747 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 800747 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 800747 # number of overall misses -system.cpu1.icache.overall_misses::total 800747 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10721128674 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10721128674 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10721128674 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10721128674 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10721128674 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10721128674 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 11347646 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 11347646 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 11347646 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 11347646 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 11347646 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 11347646 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070565 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.070565 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070565 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.070565 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070565 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.070565 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13388.908949 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13388.908949 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13388.908949 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13388.908949 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13388.908949 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits +system.cpu1.icache.overall_hits::total 10411414 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses +system.cpu1.icache.overall_misses::total 792279 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 11203693 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1396,128 +1396,128 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 800747 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 800747 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 800747 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 800747 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,72 +1526,72 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 269177 # number of writebacks -system.cpu1.dcache.writebacks::total 269177 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 37509 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 37509 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98167 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 98167 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 30 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 30 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 135676 # 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number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30271690 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30271690 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6554290133 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6554290133 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6554290133 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6554290133 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11992419500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11992419500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672512707 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672512707 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36664932207 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36664932207 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.027951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027069 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120479 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120479 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113503 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113503 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027609 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.027609 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027609 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11780.177749 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11780.177749 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.873202 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.873202 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6356.491815 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6356.491815 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2990.091861 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2990.091861 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19769.526997 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19769.526997 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks +system.cpu1.dcache.writebacks::total 268002 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082652 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082652 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1615,10 +1615,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 721880739500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 721880739500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 721880739500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 721880739500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 4491c3f13..4c74a9fb4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.567677 # Number of seconds simulated -sim_ticks 2567677478000 # Number of ticks simulated -final_tick 2567677478000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.566439 # Number of seconds simulated +sim_ticks 2566439177500 # Number of ticks simulated +final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53140 # Simulator instruction rate (inst/s) -host_op_rate 68307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2251849348 # Simulator tick rate (ticks/s) -host_mem_usage 443244 # Number of bytes of host memory used -host_seconds 1140.25 # Real time elapsed on the host -sim_insts 60592948 # Number of instructions simulated -sim_ops 77887482 # Number of ops (including micro ops) simulated +host_inst_rate 73545 # Simulator instruction rate (inst/s) +host_op_rate 88536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3115018228 # Simulator tick rate (ticks/s) +host_mem_usage 470576 # Number of bytes of host memory used +host_seconds 823.89 # Real time elapsed on the host +sim_insts 60593470 # Number of instructions simulated +sim_ops 72944147 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10106264 # Number of bytes read from this memory -system.physmem.bytes_read::total 131218072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1017856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3829760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory +system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6845832 # Number of bytes written to this memory +system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157946 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296782 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59840 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813858 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47167344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3935955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51103798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 396411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1491527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1174630 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666157 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1491527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47167344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5110586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53769956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296782 # Number of read requests accepted -system.physmem.writeReqs 813858 # Number of write requests accepted -system.physmem.readBursts 15296782 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813858 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978883904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 110144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6853696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131218072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6845832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1721 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706743 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4671 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955926 # Per bank write bursts -system.physmem.perBankRdBursts::1 955615 # Per bank write bursts -system.physmem.perBankRdBursts::2 955732 # Per bank write bursts -system.physmem.perBankRdBursts::3 955955 # Per bank write bursts -system.physmem.perBankRdBursts::4 957630 # Per bank write bursts -system.physmem.perBankRdBursts::5 955653 # Per bank write bursts -system.physmem.perBankRdBursts::6 955569 # Per bank write bursts -system.physmem.perBankRdBursts::7 955430 # Per bank write bursts -system.physmem.perBankRdBursts::8 956341 # Per bank write bursts -system.physmem.perBankRdBursts::9 955977 # Per bank write bursts -system.physmem.perBankRdBursts::10 955547 # Per bank write bursts -system.physmem.perBankRdBursts::11 955151 # Per bank write bursts -system.physmem.perBankRdBursts::12 956306 # Per bank write bursts -system.physmem.perBankRdBursts::13 956026 # Per bank write bursts -system.physmem.perBankRdBursts::14 956165 # Per bank write bursts -system.physmem.perBankRdBursts::15 956038 # Per bank write bursts -system.physmem.perBankWrBursts::0 6624 # Per bank write bursts -system.physmem.perBankWrBursts::1 6445 # Per bank write bursts -system.physmem.perBankWrBursts::2 6544 # Per bank write bursts -system.physmem.perBankWrBursts::3 6594 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6747 # Per bank write bursts -system.physmem.perBankWrBursts::6 6783 # Per bank write bursts -system.physmem.perBankWrBursts::7 6690 # Per bank write bursts -system.physmem.perBankWrBursts::8 7075 # Per bank write bursts -system.physmem.perBankWrBursts::9 6811 # Per bank write bursts -system.physmem.perBankWrBursts::10 6482 # Per bank write bursts -system.physmem.perBankWrBursts::11 6150 # Per bank write bursts -system.physmem.perBankWrBursts::12 7106 # Per bank write bursts -system.physmem.perBankWrBursts::13 6684 # Per bank write bursts -system.physmem.perBankWrBursts::14 7011 # Per bank write bursts -system.physmem.perBankWrBursts::15 6852 # Per bank write bursts +system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15296364 # Number of read requests accepted +system.physmem.writeReqs 813570 # Number of write requests accepted +system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue +system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955903 # Per bank write bursts +system.physmem.perBankRdBursts::1 955584 # Per bank write bursts +system.physmem.perBankRdBursts::2 955711 # Per bank write bursts +system.physmem.perBankRdBursts::3 955912 # Per bank write bursts +system.physmem.perBankRdBursts::4 957606 # Per bank write bursts +system.physmem.perBankRdBursts::5 955733 # Per bank write bursts +system.physmem.perBankRdBursts::6 955604 # Per bank write bursts +system.physmem.perBankRdBursts::7 955438 # Per bank write bursts +system.physmem.perBankRdBursts::8 956293 # Per bank write bursts +system.physmem.perBankRdBursts::9 955954 # Per bank write bursts +system.physmem.perBankRdBursts::10 955536 # Per bank write bursts +system.physmem.perBankRdBursts::11 955097 # Per bank write bursts +system.physmem.perBankRdBursts::12 956286 # Per bank write bursts +system.physmem.perBankRdBursts::13 955995 # Per bank write bursts +system.physmem.perBankRdBursts::14 956150 # Per bank write bursts +system.physmem.perBankRdBursts::15 956022 # Per bank write bursts +system.physmem.perBankWrBursts::0 6610 # Per bank write bursts +system.physmem.perBankWrBursts::1 6419 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6577 # Per bank write bursts +system.physmem.perBankWrBursts::4 6482 # Per bank write bursts +system.physmem.perBankWrBursts::5 6744 # Per bank write bursts +system.physmem.perBankWrBursts::6 6779 # Per bank write bursts +system.physmem.perBankWrBursts::7 6682 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6794 # Per bank write bursts +system.physmem.perBankWrBursts::10 6476 # Per bank write bursts +system.physmem.perBankWrBursts::11 6093 # Per bank write bursts +system.physmem.perBankWrBursts::12 7096 # Per bank write bursts +system.physmem.perBankWrBursts::13 6664 # Per bank write bursts +system.physmem.perBankWrBursts::14 6987 # Per bank write bursts +system.physmem.perBankWrBursts::15 6845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2567675574500 # Total gap between requests +system.physmem.totGap 2566437420000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157928 # Read request sizes (log2) +system.physmem.readPktSize::6 157520 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59840 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1112326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1085542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1043218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2679684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2578598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3358182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 142716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 121801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 111705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 108393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -155,25 +155,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -204,63 +204,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1015088 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.085857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 904.509360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 205.145024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22501 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22772 2.24% 4.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.84% 5.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2455 0.24% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2778 0.27% 5.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1897 0.19% 6.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8457 0.83% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 971 0.10% 6.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944694 93.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1015088 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2460.593951 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115853.550339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6211 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.227960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.199911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.974162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2395 38.53% 38.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.26% 38.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3798 61.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 7 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads -system.physmem.totQLat 396370290250 # Total ticks spent queuing -system.physmem.totMemAccLat 683152684000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76475305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25914.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads +system.physmem.totQLat 394563559000 # Total ticks spent queuing +system.physmem.totMemAccLat 681341509000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44664.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.49 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.85 # Average write queue length when enqueuing -system.physmem.readRowHits 14297424 # Number of row buffer hits during reads -system.physmem.writeRowHits 89638 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing +system.physmem.readRowHits 14297661 # Number of row buffer hits during reads +system.physmem.writeRowHits 89445 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.68 # Row buffer hit rate for writes -system.physmem.avgGap 159377.63 # Average gap between requests +system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes +system.physmem.avgGap 159307.76 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2210132306750 # Time in different power states -system.physmem.memoryStateTime::REF 85740200000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states +system.physmem.memoryStateTime::REF 85698860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271799415750 # Time in different power states +system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory @@ -274,49 +275,49 @@ system.realview.nvmem.bw_inst_read::cpu.inst 100 system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54704015 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16349240 # Transaction distribution -system.membus.trans_dist::ReadResp 16349240 # Transaction distribution +system.membus.throughput 54713053 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348871 # Transaction distribution +system.membus.trans_dist::ReadResp 16348871 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59840 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4671 # Transaction distribution -system.membus.trans_dist::ReadExReq 131634 # Transaction distribution -system.membus.trans_dist::ReadExResp 131634 # Transaction distribution +system.membus.trans_dist::Writeback 59552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution +system.membus.trans_dist::ReadExReq 131585 # Transaction distribution +system.membus.trans_dist::ReadExResp 131585 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34557660 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16953376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19351738 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140462266 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140462266 # Total data (bytes) +system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140417722 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1731218500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3525000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17560732500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17618628000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4805026968 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4827706725 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37408380500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -324,7 +325,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48098342 # Throughput (bytes/s) +system.iobus.throughput 48121550 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution system.iobus.trans_dist::WriteReq 8178 # Transaction distribution @@ -434,18 +435,18 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38224979500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12907759 # Number of BP lookups -system.cpu.branchPred.condPredicted 9898849 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1085572 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8888360 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6291175 # Number of BTB hits +system.cpu.branchPred.lookups 12541574 # Number of BP lookups +system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.779930 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1515479 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 141893 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -469,25 +470,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 15416418 # DTB read hits -system.cpu.dtb.read_misses 42733 # DTB read misses -system.cpu.dtb.write_hits 11344011 # DTB write hits -system.cpu.dtb.write_misses 3796 # DTB write misses +system.cpu.dtb.read_hits 13629654 # DTB read hits +system.cpu.dtb.read_misses 33608 # DTB read misses +system.cpu.dtb.write_hits 11376786 # DTB write hits +system.cpu.dtb.write_misses 3775 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3452 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 531 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15459151 # DTB read accesses -system.cpu.dtb.write_accesses 11347807 # DTB write accesses +system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 13663262 # DTB read accesses +system.cpu.dtb.write_accesses 11380561 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26760429 # DTB hits -system.cpu.dtb.misses 46529 # DTB misses -system.cpu.dtb.accesses 26806958 # DTB accesses +system.cpu.dtb.hits 25006440 # DTB hits +system.cpu.dtb.misses 37383 # DTB misses +system.cpu.dtb.accesses 25043823 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -509,8 +510,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 23352687 # ITB inst hits -system.cpu.itb.inst_misses 9286 # ITB inst misses +system.cpu.itb.inst_hits 22903214 # ITB inst hits +system.cpu.itb.inst_misses 9061 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -519,84 +520,84 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 23361973 # ITB inst accesses -system.cpu.itb.hits 23352687 # DTB hits -system.cpu.itb.misses 9286 # DTB misses -system.cpu.itb.accesses 23361973 # DTB accesses -system.cpu.numCycles 576983411 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 22912275 # ITB inst accesses +system.cpu.itb.hits 22903214 # DTB hits +system.cpu.itb.misses 9061 # DTB misses +system.cpu.itb.accesses 22912275 # DTB accesses +system.cpu.numCycles 572663270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60592948 # Number of instructions committed -system.cpu.committedOps 77887482 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3584241 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4560301069 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.522287 # CPI: cycles per instruction -system.cpu.ipc 0.105017 # IPC: instructions per cycle +system.cpu.committedInsts 60593470 # Number of instructions committed +system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed +system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 9.450907 # CPI: cycles per instruction +system.cpu.ipc 0.105810 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed -system.cpu.tickCycles 470832364 # Number of cycles that the object actually ticked -system.cpu.idleCycles 106151047 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1545254 # number of replacements -system.cpu.icache.tags.tagsinuse 511.467506 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21802506 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1545766 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 14.104661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.467506 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed +system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 1529303 # number of replacements +system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24894039 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24894039 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21802506 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21802506 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21802506 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21802506 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21802506 # number of overall hits -system.cpu.icache.overall_hits::total 21802506 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1545767 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1545767 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1545767 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1545767 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1545767 # number of overall misses -system.cpu.icache.overall_misses::total 1545767 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20898816329 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20898816329 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20898816329 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20898816329 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20898816329 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23348273 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23348273 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172141250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 172141250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 71776562 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3214470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3214469 # Transaction distribution +system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 602969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247546 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780457 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29847 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9031212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98954304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84855034 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45620 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214364 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 184069322 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 184069322 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 229740 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3400466435 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2325579079 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2551211790 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18447489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 73062749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51631.050557 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2439202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.636650 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2525290748000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36364.368368 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.573566 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 65085 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15253.108047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.554876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000207 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.787827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 10 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -890,86 +891,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 637780 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046299 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043743 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043743 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.038866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.038866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15153.967083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15153.967083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46297.537077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46297.537077 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13919.767335 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13919.767335 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30899.108654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30899.108654 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30899.108654 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9746069 # 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number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 10870 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 935346 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 935346 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 935346 # number of overall misses +system.cpu.dcache.overall_misses::total 935346 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6943170934 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6943170934 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22231593506 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22231593506 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151835000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 151835000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 29174764440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29174764440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 29174764440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29174764440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 12054137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12054137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 10222683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -978,64 +979,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 602969 # number of writebacks -system.cpu.dcache.writebacks::total 602969 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82884 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 82884 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222784 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 222784 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 68 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 68 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 305668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 305668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 305668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 305668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 379984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 379984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250506 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250506 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10763 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 10763 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 630490 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 630490 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 630490 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 630490 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4859150309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4859150309 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668108512 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668108512 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128265000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128265000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15527258821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15527258821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15527258821 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15527258821 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182582279000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182582279000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058245639 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058245639 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640524639 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640524639 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043469 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043469 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026175 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026175 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026175 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12787.776088 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12787.776088 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.239499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.239499 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11917.216389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11917.216389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24627.288016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24627.288016 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks +system.cpu.dcache.writebacks::total 600964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265395 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265395 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1059,10 +1060,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1738541884500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738541884500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1738541884500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 76ba3533e..05396d247 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525889 # Number of seconds simulated -sim_ticks 2525888859000 # Number of ticks simulated -final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542203 # Number of seconds simulated +sim_ticks 2542202956000 # Number of ticks simulated +final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55568 # Simulator instruction rate (inst/s) -host_op_rate 71500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2327295647 # Simulator tick rate (ticks/s) -host_mem_usage 420424 # Number of bytes of host memory used -host_seconds 1085.33 # Real time elapsed on the host -sim_insts 60309513 # Number of instructions simulated -sim_ops 77601128 # Number of ops (including micro ops) simulated +host_inst_rate 40853 # Simulator instruction rate (inst/s) +host_op_rate 49218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1721973071 # Simulator tick rate (ticks/s) +host_mem_usage 411692 # Number of bytes of host memory used +host_seconds 1476.33 # Real time elapsed on the host +sim_insts 60311945 # Number of instructions simulated +sim_ops 72661478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096846 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943526 # Per bank write bursts -system.physmem.perBankRdBursts::1 937990 # Per bank write bursts -system.physmem.perBankRdBursts::2 937469 # Per bank write bursts -system.physmem.perBankRdBursts::3 937431 # Per bank write bursts -system.physmem.perBankRdBursts::4 943079 # Per bank write bursts -system.physmem.perBankRdBursts::5 938170 # Per bank write bursts -system.physmem.perBankRdBursts::6 937203 # Per bank write bursts -system.physmem.perBankRdBursts::7 936910 # Per bank write bursts -system.physmem.perBankRdBursts::8 943866 # Per bank write bursts -system.physmem.perBankRdBursts::9 938107 # Per bank write bursts -system.physmem.perBankRdBursts::10 936563 # Per bank write bursts -system.physmem.perBankRdBursts::11 936045 # Per bank write bursts -system.physmem.perBankRdBursts::12 943886 # Per bank write bursts -system.physmem.perBankRdBursts::13 937531 # Per bank write bursts -system.physmem.perBankRdBursts::14 937186 # Per bank write bursts -system.physmem.perBankRdBursts::15 937024 # Per bank write bursts -system.physmem.perBankWrBursts::0 6617 # Per bank write bursts -system.physmem.perBankWrBursts::1 6376 # Per bank write bursts -system.physmem.perBankWrBursts::2 6529 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6459 # Per bank write bursts -system.physmem.perBankWrBursts::5 6705 # Per bank write bursts -system.physmem.perBankWrBursts::6 6711 # Per bank write bursts -system.physmem.perBankWrBursts::7 6649 # Per bank write bursts -system.physmem.perBankWrBursts::8 7036 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6111 # Per bank write bursts -system.physmem.perBankWrBursts::12 7073 # Per bank write bursts -system.physmem.perBankWrBursts::13 6679 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6824 # Per bank write bursts +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.writeReqs 812506 # Number of write requests accepted +system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::1 955478 # Per bank write bursts +system.physmem.perBankRdBursts::2 953003 # Per bank write bursts +system.physmem.perBankRdBursts::3 951059 # Per bank write bursts +system.physmem.perBankRdBursts::4 958601 # Per bank write bursts +system.physmem.perBankRdBursts::5 955602 # Per bank write bursts +system.physmem.perBankRdBursts::6 952653 # Per bank write bursts +system.physmem.perBankRdBursts::7 950407 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 955874 # Per bank write bursts +system.physmem.perBankRdBursts::10 952889 # Per bank write bursts +system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::12 956166 # Per bank write bursts +system.physmem.perBankRdBursts::13 955918 # Per bank write bursts +system.physmem.perBankRdBursts::14 953918 # Per bank write bursts +system.physmem.perBankRdBursts::15 950940 # Per bank write bursts +system.physmem.perBankWrBursts::0 6546 # Per bank write bursts +system.physmem.perBankWrBursts::1 6352 # Per bank write bursts +system.physmem.perBankWrBursts::2 6488 # Per bank write bursts +system.physmem.perBankWrBursts::3 6518 # Per bank write bursts +system.physmem.perBankWrBursts::4 6421 # Per bank write bursts +system.physmem.perBankWrBursts::5 6701 # Per bank write bursts +system.physmem.perBankWrBursts::6 6665 # Per bank write bursts +system.physmem.perBankWrBursts::7 6611 # Per bank write bursts +system.physmem.perBankWrBursts::8 6966 # Per bank write bursts +system.physmem.perBankWrBursts::9 6759 # Per bank write bursts +system.physmem.perBankWrBursts::10 6421 # Per bank write bursts +system.physmem.perBankWrBursts::11 6055 # Per bank write bursts +system.physmem.perBankWrBursts::12 7037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6645 # Per bank write bursts +system.physmem.perBankWrBursts::14 6920 # Per bank write bursts +system.physmem.perBankWrBursts::15 6806 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525887732500 # Total gap between requests +system.physmem.totGap 2542201638000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 14942208 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154600 # Read request sizes (log2) +system.physmem.readPktSize::6 153412 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58488 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -171,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -220,113 +220,113 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads -system.physmem.totQLat 389024977250 # Total ticks spent queuing -system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads +system.physmem.totQLat 395449280750 # Total ticks spent queuing +system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing -system.physmem.readRowHits 14042089 # Number of row buffer hits during reads -system.physmem.writeRowHits 91063 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 14269193 # Number of row buffer hits during reads +system.physmem.writeRowHits 90708 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158760.96 # Average gap between requests +system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes +system.physmem.avgGap 157821.19 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states -system.physmem.memoryStateTime::REF 84344780000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states +system.physmem.memoryStateTime::REF 84889480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states +system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54884184 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149487 # Transaction distribution -system.membus.trans_dist::ReadResp 16149487 # Transaction distribution -system.membus.trans_dist::WriteReq 763349 # Transaction distribution -system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131431 # Transaction distribution -system.membus.trans_dist::ReadExResp 131431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) +system.membus.throughput 55125441 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348039 # Transaction distribution +system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution +system.membus.trans_dist::ReadExReq 131651 # Transaction distribution +system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631350 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140140058 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,15 +334,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48271369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution -system.iobus.trans_dist::WriteReq 8174 # Transaction distribution -system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.throughput 48580309 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928114 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14910337 # Number of BP lookups -system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits +system.cpu.branchPred.lookups 13201290 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +479,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987595 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227720 # DTB write hits -system.cpu.checker.dtb.write_misses 2191 # DTB write misses +system.cpu.checker.dtb.read_hits 13156743 # DTB read hits +system.cpu.checker.dtb.read_misses 7321 # DTB read misses +system.cpu.checker.dtb.write_hits 11227340 # DTB write hits +system.cpu.checker.dtb.write_misses 2193 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses +system.cpu.checker.dtb.read_accesses 13164064 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229533 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215315 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26224812 # DTB accesses +system.cpu.checker.dtb.hits 24384083 # DTB hits +system.cpu.checker.dtb.misses 9514 # DTB misses +system.cpu.checker.dtb.accesses 24393597 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,7 +519,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits +system.cpu.checker.itb.inst_hits 61486079 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -536,11 +536,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses -system.cpu.checker.itb.hits 61483491 # DTB hits +system.cpu.checker.itb.inst_accesses 61490552 # ITB inst accesses +system.cpu.checker.itb.hits 61486079 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61487964 # DTB accesses -system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61490552 # DTB accesses +system.cpu.checker.numCycles 72947431 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -566,25 +566,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51097792 # DTB read hits -system.cpu.dtb.read_misses 64987 # DTB read misses -system.cpu.dtb.write_hits 11709971 # DTB write hits -system.cpu.dtb.write_misses 15921 # DTB write misses +system.cpu.dtb.read_hits 31642294 # DTB read hits +system.cpu.dtb.read_misses 39524 # DTB read misses +system.cpu.dtb.write_hits 11381361 # DTB write hits +system.cpu.dtb.write_misses 10135 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51162779 # DTB read accesses -system.cpu.dtb.write_accesses 11725892 # DTB write accesses +system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 31681818 # DTB read accesses +system.cpu.dtb.write_accesses 11391496 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62807763 # DTB hits -system.cpu.dtb.misses 80908 # DTB misses -system.cpu.dtb.accesses 62888671 # DTB accesses +system.cpu.dtb.hits 43023655 # DTB hits +system.cpu.dtb.misses 49659 # DTB misses +system.cpu.dtb.accesses 43073314 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -606,8 +606,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11575507 # ITB inst hits -system.cpu.itb.inst_misses 11335 # ITB inst misses +system.cpu.itb.inst_hits 24159481 # ITB inst hits +system.cpu.itb.inst_misses 10516 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -616,607 +616,598 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11586842 # ITB inst accesses -system.cpu.itb.hits 11575507 # DTB hits -system.cpu.itb.misses 11335 # DTB misses -system.cpu.itb.accesses 11586842 # DTB accesses -system.cpu.numCycles 476238509 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169997 # ITB inst accesses +system.cpu.itb.hits 24159481 # DTB hits +system.cpu.itb.misses 10516 # DTB misses +system.cpu.itb.accesses 24169997 # DTB accesses +system.cpu.numCycles 499350041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued -system.cpu.iq.rate 0.258180 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued +system.cpu.iq.rate 0.188050 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226309 # number of nop insts executed -system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed -system.cpu.iew.exec_branches 11843747 # Number of branches executed -system.cpu.iew.exec_stores 12222179 # Number of stores executed -system.cpu.iew.exec_rate 0.253798 # Inst execution rate -system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47892202 # num instructions producing a value -system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value +system.cpu.iew.exec_nop 176010 # number of nop insts executed +system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791342 # Number of branches executed +system.cpu.iew.exec_stores 11888889 # Number of stores executed +system.cpu.iew.exec_rate 0.186738 # Inst execution rate +system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35465784 # num instructions producing a value +system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459894 # Number of instructions committed -system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462326 # Number of instructions committed +system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386881 # Number of memory references committed -system.cpu.commit.loads 15654781 # Number of loads committed -system.cpu.commit.membars 403574 # Number of memory barriers committed -system.cpu.commit.branches 10306383 # Number of branches committed +system.cpu.commit.refs 25244569 # Number of memory references committed +system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.membars 403660 # Number of memory barriers committed +system.cpu.commit.branches 10308073 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction -system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction +system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239318561 # The number of ROB reads -system.cpu.rob.rob_writes 197472000 # The number of ROB writes -system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309513 # Number of Instructions Simulated -system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548833946 # number of integer regfile reads -system.cpu.int_regfile_writes 87707846 # number of integer regfile writes -system.cpu.fp_regfile_reads 8328 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 568287463 # The number of ROB reads +system.cpu.rob.rob_writes 154414560 # The number of ROB writes +system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311945 # Number of Instructions Simulated +system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116898 # number of integer regfile reads +system.cpu.int_regfile_writes 47012348 # number of integer regfile writes +system.cpu.fp_regfile_reads 8305 # number of floating regfile reads +system.cpu.fp_regfile_writes 2780 # number of floating regfile writes +system.cpu.cc_regfile_reads 320404209 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes +system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes +system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980898 # number of replacements -system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 959881 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits -system.cpu.icache.overall_hits::total 10510158 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses -system.cpu.icache.overall_misses::total 1061739 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits +system.cpu.icache.overall_hits::total 23149457 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses +system.cpu.icache.overall_misses::total 1005369 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64369 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 63302 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162204 # 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number of writebacks -system.cpu.dcache.writebacks::total 607940 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks +system.cpu.dcache.writebacks::total 599976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1522,16 +1524,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index fcbba5f01..b3c80425c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605246 # Number of seconds simulated -sim_ticks 2605245500000 # Number of ticks simulated -final_tick 2605245500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.621647 # Number of seconds simulated +sim_ticks 2621647051000 # Number of ticks simulated +final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66179 # Simulator instruction rate (inst/s) -host_op_rate 85203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2745863070 # Simulator tick rate (ticks/s) -host_mem_usage 426204 # Number of bytes of host memory used -host_seconds 948.79 # Real time elapsed on the host -sim_insts 62790043 # Number of instructions simulated -sim_ops 80839298 # Number of ops (including micro ops) simulated +host_inst_rate 56801 # Simulator instruction rate (inst/s) +host_op_rate 68443 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2377539464 # Simulator tick rate (ticks/s) +host_mem_usage 411700 # Number of bytes of host memory used +host_seconds 1102.67 # Real time elapsed on the host +sim_insts 62632896 # Number of instructions simulated +sim_ops 75470296 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4351548 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 427968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5241528 # Number of bytes read from this memory -system.physmem.bytes_read::total 131526900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 427968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4250944 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7280080 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory +system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6149 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6687 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301674 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66421 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823705 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46487184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1670302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2011913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50485415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164272 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1631687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156181 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1631687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46487184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1676828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3168095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53279808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15301674 # Number of read requests accepted -system.physmem.writeReqs 823705 # Number of write requests accepted -system.physmem.readBursts 15301674 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823705 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 974584832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4722304 # Total number of bytes read from write queue -system.physmem.bytesWritten 7299840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131526900 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7280080 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 73786 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709619 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956301 # Per bank write bursts -system.physmem.perBankRdBursts::1 950868 # Per bank write bursts -system.physmem.perBankRdBursts::2 950386 # Per bank write bursts -system.physmem.perBankRdBursts::3 950557 # Per bank write bursts -system.physmem.perBankRdBursts::4 956616 # Per bank write bursts -system.physmem.perBankRdBursts::5 950990 # Per bank write bursts -system.physmem.perBankRdBursts::6 949776 # Per bank write bursts -system.physmem.perBankRdBursts::7 949548 # Per bank write bursts -system.physmem.perBankRdBursts::8 956645 # Per bank write bursts -system.physmem.perBankRdBursts::9 951285 # Per bank write bursts -system.physmem.perBankRdBursts::10 949982 # Per bank write bursts -system.physmem.perBankRdBursts::11 948991 # Per bank write bursts -system.physmem.perBankRdBursts::12 956228 # Per bank write bursts -system.physmem.perBankRdBursts::13 950424 # Per bank write bursts -system.physmem.perBankRdBursts::14 949846 # Per bank write bursts -system.physmem.perBankRdBursts::15 949445 # Per bank write bursts -system.physmem.perBankWrBursts::0 7049 # Per bank write bursts -system.physmem.perBankWrBursts::1 6917 # Per bank write bursts -system.physmem.perBankWrBursts::2 7321 # Per bank write bursts -system.physmem.perBankWrBursts::3 7203 # Per bank write bursts -system.physmem.perBankWrBursts::4 7749 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 7008 # Per bank write bursts -system.physmem.perBankWrBursts::7 6995 # Per bank write bursts -system.physmem.perBankWrBursts::8 7363 # Per bank write bursts -system.physmem.perBankWrBursts::9 7456 # Per bank write bursts -system.physmem.perBankWrBursts::10 6910 # Per bank write bursts -system.physmem.perBankWrBursts::11 6580 # Per bank write bursts -system.physmem.perBankWrBursts::12 7092 # Per bank write bursts -system.physmem.perBankWrBursts::13 7012 # Per bank write bursts -system.physmem.perBankWrBursts::14 7131 # Per bank write bursts -system.physmem.perBankWrBursts::15 6974 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15303475 # Number of read requests accepted +system.physmem.writeReqs 822748 # Number of write requests accepted +system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue +system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956536 # Per bank write bursts +system.physmem.perBankRdBursts::1 956505 # Per bank write bursts +system.physmem.perBankRdBursts::2 953083 # Per bank write bursts +system.physmem.perBankRdBursts::3 951219 # Per bank write bursts +system.physmem.perBankRdBursts::4 959451 # Per bank write bursts +system.physmem.perBankRdBursts::5 955886 # Per bank write bursts +system.physmem.perBankRdBursts::6 953593 # Per bank write bursts +system.physmem.perBankRdBursts::7 950807 # Per bank write bursts +system.physmem.perBankRdBursts::8 956024 # Per bank write bursts +system.physmem.perBankRdBursts::9 956507 # Per bank write bursts +system.physmem.perBankRdBursts::10 953309 # Per bank write bursts +system.physmem.perBankRdBursts::11 950948 # Per bank write bursts +system.physmem.perBankRdBursts::12 956403 # Per bank write bursts +system.physmem.perBankRdBursts::13 956390 # Per bank write bursts +system.physmem.perBankRdBursts::14 954120 # Per bank write bursts +system.physmem.perBankRdBursts::15 951130 # Per bank write bursts +system.physmem.perBankWrBursts::0 7301 # Per bank write bursts +system.physmem.perBankWrBursts::1 7301 # Per bank write bursts +system.physmem.perBankWrBursts::2 6635 # Per bank write bursts +system.physmem.perBankWrBursts::3 6826 # Per bank write bursts +system.physmem.perBankWrBursts::4 7245 # Per bank write bursts +system.physmem.perBankWrBursts::5 6961 # Per bank write bursts +system.physmem.perBankWrBursts::6 7187 # Per bank write bursts +system.physmem.perBankWrBursts::7 6869 # Per bank write bursts +system.physmem.perBankWrBursts::8 6823 # Per bank write bursts +system.physmem.perBankWrBursts::9 7301 # Per bank write bursts +system.physmem.perBankWrBursts::10 6956 # Per bank write bursts +system.physmem.perBankWrBursts::11 6738 # Per bank write bursts +system.physmem.perBankWrBursts::12 7232 # Per bank write bursts +system.physmem.perBankWrBursts::13 7102 # Per bank write bursts +system.physmem.perBankWrBursts::14 7378 # Per bank write bursts +system.physmem.perBankWrBursts::15 7255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605244301000 # Total gap between requests +system.physmem.totGap 2621645657000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 109 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 59 # Read request sizes (log2) +system.physmem.readPktSize::3 15138841 # Read request sizes (log2) +system.physmem.readPktSize::4 3426 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 162749 # Read request sizes (log2) +system.physmem.readPktSize::6 161149 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66421 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1076672 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1007796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 966781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1073648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 970528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1031139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2669789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2577083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3357471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128637 # What read queue length does an incoming req see +system.physmem.writePktSize::6 65464 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 102015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -176,28 +176,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see @@ -225,383 +225,385 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1012037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 970.206299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 901.657757 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 207.022901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24841 2.45% 2.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20798 2.06% 4.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8822 0.87% 5.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2548 0.25% 5.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 0.25% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1879 0.19% 6.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8798 0.87% 6.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1115 0.11% 7.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 940696 92.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1012037 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2278.257181 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 111148.889106 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6680 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.064632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.010880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.396865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3849 57.59% 57.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 42 0.63% 58.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1749 26.17% 84.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 863 12.91% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 73 1.09% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 28 0.42% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.46% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.46% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.21% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads -system.physmem.totQLat 394529621500 # Total ticks spent queuing -system.physmem.totMemAccLat 680052521500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76139440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25908.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads +system.physmem.totQLat 395207982750 # Total ticks spent queuing +system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44658.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.94 # Data bus utilization in percentage -system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.93 # Data bus utilization in percentage +system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 14233868 # Number of row buffer hits during reads -system.physmem.writeRowHits 96043 # Number of row buffer hits during writes +system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing +system.physmem.readRowHits 14274861 # Number of row buffer hits during reads +system.physmem.writeRowHits 95334 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.18 # Row buffer hit rate for writes -system.physmem.avgGap 161561.74 # Average gap between requests +system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes +system.physmem.avgGap 162570.35 # Average gap between requests system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2261037204000 # Time in different power states -system.physmem.memoryStateTime::REF 86994700000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states +system.physmem.memoryStateTime::REF 87542520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 257208674750 # Time in different power states +system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54210578 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352619 # Transaction distribution -system.membus.trans_dist::ReadResp 16352619 # Transaction distribution -system.membus.trans_dist::WriteReq 769183 # Transaction distribution -system.membus.trans_dist::WriteResp 769183 # Transaction distribution -system.membus.trans_dist::Writeback 66421 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35773 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18321 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14174 # Transaction distribution -system.membus.trans_dist::ReadExReq 137666 # Transaction distribution -system.membus.trans_dist::ReadExResp 137285 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 53827614 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16353736 # Transaction distribution +system.membus.trans_dist::ReadResp 16353736 # Transaction distribution +system.membus.trans_dist::WriteReq 768463 # Transaction distribution +system.membus.trans_dist::WriteResp 768463 # Transaction distribution +system.membus.trans_dist::Writeback 65464 # Transaction distribution +system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution +system.membus.trans_dist::ReadExReq 137713 # Transaction distribution +system.membus.trans_dist::ReadExResp 137251 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975354 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4375612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34653244 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17696452 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20121337 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141231865 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141231865 # Total data (bytes) +system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141117005 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487709500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11701000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1799000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17608394498 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4825319244 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37398632151 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72458 # number of replacements -system.l2c.tags.tagsinuse 53011.924457 # Cycle average of tags in use -system.l2c.tags.total_refs 1875821 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137631 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.629349 # Average number of references to valid blocks. +system.l2c.tags.replacements 71035 # number of replacements +system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use +system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37713.505334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.216539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4181.052971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2965.825646 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.076579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4028.442908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4106.804235 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575462 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045255 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061469 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062665 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8671 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53043 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18870937 # Number of tag accesses -system.l2c.tags.data_accesses 18870937 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 23602 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393472 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166101 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17281163575 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 176335500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 29432158571 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3342000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155119958750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184731794821 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038974 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017257 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016899 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.771693 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.910870 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.830226 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.655654 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.842953 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746736 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589536 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506032 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559394 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098358 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098358 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -792,64 +797,66 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58770672 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2743232 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2743231 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583097 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35011 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18701 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53712 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259154 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259154 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 799809 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 57985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1233533 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820063 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8090245 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25576064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34728353 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18500 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39453888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48201112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 22492 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148227457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148227457 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4884572 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4922251450 # Layer occupancy (ticks) +system.toL2Bus.throughput 57560286 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146550569 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1802620121 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1515652575 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9436941 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34537141 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2778792830 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3257203486 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 9681453 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 42845398 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47405592 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution +system.iobus.throughput 47108999 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution system.iobus.trans_dist::WriteReq 8083 # Transaction distribution system.iobus.trans_dist::WriteResp 8083 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) @@ -869,14 +876,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) @@ -896,18 +903,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503205 # Total data (bytes) +system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503169 # Total data (bytes) system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -949,19 +956,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38152801849 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6193187 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4738042 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296192 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3876930 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2986045 # Number of BTB hits +system.cpu0.branchPred.lookups 8682194 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.020864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 687525 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28310 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -985,25 +992,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8977307 # DTB read hits -system.cpu0.dtb.read_misses 29619 # DTB read misses -system.cpu0.dtb.write_hits 5215302 # DTB write hits -system.cpu0.dtb.write_misses 5680 # DTB write misses +system.cpu0.dtb.read_hits 10917771 # DTB read hits +system.cpu0.dtb.read_misses 23643 # DTB read misses +system.cpu0.dtb.write_hits 7767808 # DTB write hits +system.cpu0.dtb.write_misses 8146 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1732 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 993 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 620 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9006926 # DTB read accesses -system.cpu0.dtb.write_accesses 5220982 # DTB write accesses +system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 10941414 # DTB read accesses +system.cpu0.dtb.write_accesses 7775954 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14192609 # DTB hits -system.cpu0.dtb.misses 35299 # DTB misses -system.cpu0.dtb.accesses 14227908 # DTB accesses +system.cpu0.dtb.hits 18685579 # DTB hits +system.cpu0.dtb.misses 31789 # DTB misses +system.cpu0.dtb.accesses 18717368 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1025,8 +1032,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4299863 # ITB inst hits -system.cpu0.itb.inst_misses 5195 # ITB inst misses +system.cpu0.itb.inst_hits 16449037 # ITB inst hits +system.cpu0.itb.inst_misses 5743 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1035,580 +1042,593 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1219 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1331 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4305058 # ITB inst accesses -system.cpu0.itb.hits 4299863 # DTB hits -system.cpu0.itb.misses 5195 # DTB misses -system.cpu0.itb.accesses 4305058 # DTB accesses -system.cpu0.numCycles 69478980 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses +system.cpu0.itb.hits 16449037 # DTB hits +system.cpu0.itb.misses 5743 # DTB misses +system.cpu0.itb.accesses 16454780 # DTB accesses +system.cpu0.numCycles 110984158 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11944453 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32774113 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6193187 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3673570 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7678957 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1502530 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 63317 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19508655 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 6049 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47760 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1413705 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 248 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4298413 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 159366 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2185 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41753011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.013655 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.394447 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34081524 81.63% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 576095 1.38% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 828597 1.98% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 688423 1.65% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 783359 1.88% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570610 1.37% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 698382 1.67% 91.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 360373 0.86% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3165648 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41753011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089138 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471713 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12274082 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20961054 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7066192 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 425731 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1025952 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 955706 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65065 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40945366 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213036 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1025952 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12760478 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 3004976 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13648632 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7041602 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4271371 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39802599 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1199 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1526731 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1438820 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1837389 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 522 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40279465 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182145305 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 165318292 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 4116 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31479900 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8799564 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460456 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417031 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4293085 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7837564 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5796369 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1159621 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1213862 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37649045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 906994 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37770468 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93887 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6620221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14342287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 258409 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41753011 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904617 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.539726 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26686839 63.92% 63.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5690671 13.63% 77.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3035101 7.27% 84.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2408430 5.77% 90.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2094356 5.02% 95.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 953036 2.28% 97.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 611124 1.46% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 212675 0.51% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60779 0.15% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41753011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29050 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 460 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 862862 76.64% 79.26% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 233562 20.74% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14549 0.04% 0.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22728130 60.17% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48220 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9442602 25.00% 85.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5536256 14.66% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37770468 # Type of FU issued -system.cpu0.iq.rate 0.543624 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1125934 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.029810 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118540397 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45184408 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34905571 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8382 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38877516 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4337 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 330330 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued +system.cpu0.iq.rate 0.499469 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1458060 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2363 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13414 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 565962 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2141820 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5981 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1025952 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2385802 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 275075 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38676599 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 76106 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7837564 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5796369 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 579111 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58653 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 199282 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13414 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149919 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118426 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268345 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37387044 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9294285 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 383424 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 120560 # number of nop insts executed -system.cpu0.iew.exec_refs 14782259 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4971290 # Number of branches executed -system.cpu0.iew.exec_stores 5487974 # Number of stores executed -system.cpu0.iew.exec_rate 0.538106 # Inst execution rate -system.cpu0.iew.wb_sent 37190474 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34909443 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18996365 # num instructions producing a value -system.cpu0.iew.wb_consumers 36943291 # num instructions consuming a value +system.cpu0.iew.exec_nop 93848 # number of nop insts executed +system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7332190 # Number of branches executed +system.cpu0.iew.exec_stores 8168521 # Number of stores executed +system.cpu0.iew.exec_rate 0.495806 # Inst execution rate +system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25110485 # num instructions producing a value +system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.502446 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.514203 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6443412 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 648585 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232277 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40727059 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.780301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.748318 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28935599 71.05% 71.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5796697 14.23% 85.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1842943 4.53% 89.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1067095 2.62% 92.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 737891 1.81% 94.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 511993 1.26% 95.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448684 1.10% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 197374 0.48% 97.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1188783 2.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40727059 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24067678 # Number of instructions committed -system.cpu0.commit.committedOps 31779383 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 43173906 # Number of instructions committed +system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11609911 # Number of memory references committed -system.cpu0.commit.loads 6379504 # Number of loads committed -system.cpu0.commit.membars 231786 # Number of memory barriers committed -system.cpu0.commit.branches 4350837 # Number of branches committed +system.cpu0.commit.refs 16914467 # Number of memory references committed +system.cpu0.commit.loads 8858661 # Number of loads committed +system.cpu0.commit.membars 263890 # Number of memory barriers committed +system.cpu0.commit.branches 7043091 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28125415 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498912 # Number of function calls committed. +system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666034 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 20129006 63.34% 63.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39786 0.13% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.47% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6379504 20.07% 83.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5230407 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 31779383 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1188783 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction +system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 76892389 # The number of ROB reads -system.cpu0.rob.rob_writes 77473478 # The number of ROB writes -system.cpu0.timesIdled 368167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27725969 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5140969387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23986936 # Number of Instructions Simulated -system.cpu0.committedOps 31698641 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.896534 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.896534 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.345240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.345240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174527841 # number of integer regfile reads -system.cpu0.int_regfile_writes 34672219 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3319 # number of floating regfile reads -system.cpu0.fp_regfile_writes 920 # number of floating regfile writes -system.cpu0.misc_regfile_reads 78617689 # number of misc regfile reads -system.cpu0.misc_regfile_writes 500675 # number of misc regfile writes -system.cpu0.icache.tags.replacements 399525 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.581560 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3866760 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 400037 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.666006 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6951542250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.581560 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999183 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999183 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 159811836 # The number of ROB reads +system.cpu0.rob.rob_writes 108530018 # The number of ROB writes +system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 43093164 # Number of Instructions Simulated +system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads +system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads +system.cpu0.fp_regfile_writes 840 # number of floating regfile writes +system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads +system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes +system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads +system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes +system.cpu0.icache.tags.replacements 554010 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 4698333 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 4698333 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 3866760 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3866760 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3866760 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3866760 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3866760 # number of overall hits -system.cpu0.icache.overall_hits::total 3866760 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431519 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431519 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431519 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431519 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431519 # number of overall misses -system.cpu0.icache.overall_misses::total 431519 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5963742706 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5963742706 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5963742706 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5963742706 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5963742706 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5963742706 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4298279 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4298279 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4298279 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4298279 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4298279 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4298279 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100393 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100393 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100393 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100393 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100393 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100393 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13820.347901 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13820.347901 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13820.347901 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13820.347901 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13820.347901 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4778 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 15866984 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 15866984 # number of overall hits +system.cpu0.icache.overall_hits::total 15866984 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 579761 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 579761 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 579761 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 579761 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 579761 # number of overall misses +system.cpu0.icache.overall_misses::total 579761 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8029558142 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8029558142 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 8029558142 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 275167 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.361699 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9408418 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 275679 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.128164 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42907250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.361699 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938206 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938206 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 409126 # number of replacements +system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 45804428 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 45804428 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5867272 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5867272 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3220606 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3220606 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139465 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139465 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137168 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137168 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9087878 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9087878 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9087878 # number of overall hits -system.cpu0.dcache.overall_hits::total 9087878 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 403110 # 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number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6270382 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6270382 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4809403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4809403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148385 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148385 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144926 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144926 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11079785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11079785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11079785 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179778 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.179778 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14025.047153 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14025.047153 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47114.809888 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47114.809888 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10242.486771 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10242.486771 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6451.374968 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6451.374968 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40418.305355 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 40418.305355 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 40418.305355 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9294 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6492 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 635 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 113 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.636220 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 57.451327 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits +system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses +system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255545 # number of writebacks -system.cpu0.dcache.writebacks::total 255545 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 213826 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 213826 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457949 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1457949 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1671775 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1671775 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1671775 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1671775 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189284 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189284 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130848 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130848 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7758 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320132 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320132 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320132 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320132 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2416725188 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2416725188 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5154000431 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5154000431 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69605516 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69605516 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34529233 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34529233 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7570725619 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7570725619 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7570725619 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7570725619 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434660545 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434660545 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206058380 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206058380 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640718925 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640718925 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030187 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030187 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027207 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053531 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053531 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028893 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028893 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028893 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12767.720399 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12767.720399 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39389.218261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39389.218261 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8236.364454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8236.364454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4450.790539 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4450.790539 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23648.762445 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23648.762445 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks +system.cpu0.dcache.writebacks::total 375988 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1616,15 +1636,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9402679 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7728805 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 418099 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6037829 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5108046 # Number of BTB hits +system.cpu1.branchPred.lookups 5001209 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.600707 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 802186 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 44176 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1648,25 +1668,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42878527 # DTB read hits -system.cpu1.dtb.read_misses 38253 # DTB read misses -system.cpu1.dtb.write_hits 6985734 # DTB write hits -system.cpu1.dtb.write_misses 10793 # DTB write misses +system.cpu1.dtb.read_hits 21293354 # DTB read hits +system.cpu1.dtb.read_misses 17527 # DTB read misses +system.cpu1.dtb.write_hits 4063342 # DTB write hits +system.cpu1.dtb.write_misses 3266 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1922 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2963 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 687 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42916780 # DTB read accesses -system.cpu1.dtb.write_accesses 6996527 # DTB write accesses +system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 21310881 # DTB read accesses +system.cpu1.dtb.write_accesses 4066608 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49864261 # DTB hits -system.cpu1.dtb.misses 49046 # DTB misses -system.cpu1.dtb.accesses 49913307 # DTB accesses +system.cpu1.dtb.hits 25356696 # DTB hits +system.cpu1.dtb.misses 20793 # DTB misses +system.cpu1.dtb.accesses 25377489 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1688,8 +1708,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7755980 # ITB inst hits -system.cpu1.itb.inst_misses 5491 # ITB inst misses +system.cpu1.itb.inst_hits 8626509 # ITB inst hits +system.cpu1.itb.inst_misses 4363 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1698,579 +1718,595 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1362 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1507 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7761471 # ITB inst accesses -system.cpu1.itb.hits 7755980 # DTB hits -system.cpu1.itb.misses 5491 # DTB misses -system.cpu1.itb.accesses 7761471 # DTB accesses -system.cpu1.numCycles 413132210 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses +system.cpu1.itb.hits 8626509 # DTB hits +system.cpu1.itb.misses 4363 # DTB misses +system.cpu1.itb.accesses 8630872 # DTB accesses +system.cpu1.numCycles 396849081 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19420388 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61788688 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9402679 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5910232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13466568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3411318 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 67616 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77041165 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1523639 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7754163 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 555305 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2851 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113918823 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.663934 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.994464 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100459727 88.19% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 820479 0.72% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 969052 0.85% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1718827 1.51% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1427854 1.25% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 590556 0.52% 93.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1988498 1.75% 94.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 426289 0.37% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5517541 4.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113918823 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022759 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.149562 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20573629 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78271180 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12141436 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 681674 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2250904 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1146333 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 101070 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71648546 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 337709 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2250904 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21753755 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 11785871 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 44839476 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11758144 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 21530673 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67615561 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 613 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 15671923 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18336953 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1545811 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 1295 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71310682 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 315205355 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 288681323 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6622 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50413608 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20897074 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 766814 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 706637 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7207016 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12951593 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8155935 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1106689 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1533453 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62295252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1184366 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88905891 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 106644 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13983630 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 37714490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 285025 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113918823 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780432 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.530885 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83813472 73.57% 73.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8528665 7.49% 81.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3988574 3.50% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3433815 3.01% 87.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10704573 9.40% 96.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1891022 1.66% 98.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1169449 1.03% 99.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 305487 0.27% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 83766 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113918823 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 34951 0.44% 0.44% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 989 0.01% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7593663 95.44% 95.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 326577 4.10% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 14267 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37698483 42.40% 42.42% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61348 0.07% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.49% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43772925 49.24% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7357130 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88905891 # Type of FU issued -system.cpu1.iq.rate 0.215200 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7956180 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089490 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 299826864 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 77472999 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54370047 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15424 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8128 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6867 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96839621 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8183 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 371805 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued +system.cpu1.iq.rate 0.104429 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2971595 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3826 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 18443 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1153168 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31846626 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675699 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2250904 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 9489416 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1235015 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63585663 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 104803 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12951593 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8155935 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 886916 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 232294 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 885959 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 18443 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 206591 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 158855 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 365446 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87166570 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43262018 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1739321 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106045 # number of nop insts executed -system.cpu1.iew.exec_refs 50553896 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7398817 # Number of branches executed -system.cpu1.iew.exec_stores 7291878 # Number of stores executed -system.cpu1.iew.exec_rate 0.210990 # Inst execution rate -system.cpu1.iew.wb_sent 86399299 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54376914 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30829889 # num instructions producing a value -system.cpu1.iew.wb_consumers 55266228 # num instructions consuming a value +system.cpu1.iew.exec_nop 82227 # number of nop insts executed +system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3899404 # Number of branches executed +system.cpu1.iew.exec_stores 4241599 # Number of stores executed +system.cpu1.iew.exec_rate 0.103764 # Inst execution rate +system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 11348419 # num instructions producing a value +system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131621 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557843 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13879712 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 899341 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 318567 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111667919 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440684 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.404622 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 93786179 83.99% 83.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9487781 8.50% 92.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2098555 1.88% 94.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1338170 1.20% 95.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 960614 0.86% 96.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 571645 0.51% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1030883 0.92% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 527820 0.47% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1866272 1.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111667919 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38872746 # Number of instructions committed -system.cpu1.commit.committedOps 49210296 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 19609371 # Number of instructions committed +system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16982765 # Number of memory references committed -system.cpu1.commit.loads 9979998 # Number of loads committed -system.cpu1.commit.membars 195533 # Number of memory barriers committed -system.cpu1.commit.branches 6424967 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43922606 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553368 # Number of function calls committed. +system.cpu1.commit.refs 9369646 # Number of memory references committed +system.cpu1.commit.loads 5202699 # Number of loads committed +system.cpu1.commit.membars 162322 # Number of memory barriers committed +system.cpu1.commit.branches 3698878 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions. +system.cpu1.commit.function_calls 385194 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 32167564 65.37% 65.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58261 0.12% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9979998 20.28% 85.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7002767 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 49210296 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1866272 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction +system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171825162 # The number of ROB reads -system.cpu1.rob.rob_writes 128514038 # The number of ROB writes -system.cpu1.timesIdled 1427088 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 299213387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796716848 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38803107 # Number of Instructions Simulated -system.cpu1.committedOps 49140657 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 10.646885 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.646885 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.093924 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.093924 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391718305 # number of integer regfile reads -system.cpu1.int_regfile_writes 56505033 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5108 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 199117817 # number of misc regfile reads -system.cpu1.misc_regfile_writes 722972 # number of misc regfile writes -system.cpu1.icache.tags.replacements 616464 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.721065 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7090163 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 616976 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.491797 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74744507500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.721065 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974065 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974065 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 419589246 # The number of ROB reads +system.cpu1.rob.rob_writes 52032512 # The number of ROB writes +system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 19539732 # Number of Instructions Simulated +system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads +system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes +system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes +system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads +system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes +system.cpu1.icache.tags.replacements 439266 # number of replacements +system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 8371129 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 8371129 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 7090163 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7090163 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7090163 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7090163 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7090163 # number of overall hits -system.cpu1.icache.overall_hits::total 7090163 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 663949 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 663949 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 663949 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 663949 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 663949 # number of overall misses -system.cpu1.icache.overall_misses::total 663949 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9003300184 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9003300184 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9003300184 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9003300184 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9003300184 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9003300184 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7754112 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7754112 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7754112 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7754112 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7754112 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7754112 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085625 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.085625 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085625 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.085625 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085625 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.085625 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13560.228548 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13560.228548 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13560.228548 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13560.228548 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13560.228548 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3101 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 648 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 217 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.290323 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 648 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits +system.cpu1.icache.overall_hits::total 8166304 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses +system.cpu1.icache.overall_misses::total 457900 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46932 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46932 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46932 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46932 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46932 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46932 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 617017 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 617017 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 617017 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 617017 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 617017 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 617017 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7343865656 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7343865656 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7343865656 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7343865656 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7343865656 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7343865656 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4135000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4135000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4135000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4135000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079573 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079573 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079573 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079573 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11902.209592 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11902.209592 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11902.209592 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 363234 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.053035 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 13011922 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 363603 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.786069 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70837218250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.053035 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947369 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947369 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 60324528 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 60324528 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8516413 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8516413 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4259216 # 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number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14210 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14210 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10944 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10944 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1986483 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1986483 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1986483 # number of overall misses -system.cpu1.dcache.overall_misses::total 1986483 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6227092173 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6227092173 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 74233295889 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 74233295889 # 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number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5836211 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113826 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 113826 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108002 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 108002 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14762112 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14762112 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14762112 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14762112 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045876 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045876 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.270209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.270209 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124840 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124840 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101331 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101331 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134566 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134566 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134566 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134566 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15207.019920 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15207.019920 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47072.626032 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 47072.626032 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9220.988318 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9220.988318 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5340.011696 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5340.011696 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 40503.939909 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 40503.939909 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 40503.939909 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 30714 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17665 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 190 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.344083 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 92.973684 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 227040 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits +system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses +system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327552 # number of writebacks -system.cpu1.dcache.writebacks::total 327552 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178171 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 178171 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1413840 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1413840 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1455 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1592011 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1592011 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1592011 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1592011 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231317 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231317 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163155 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163155 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12755 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12755 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10944 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10944 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394472 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394472 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394472 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394472 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2894401946 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2894401946 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6921941032 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6921941032 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89586755 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89586755 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36550912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36550912 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9816342978 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9816342978 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9816342978 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9816342978 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231628259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231628259 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25874415734 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25874415734 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195106043993 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195106043993 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025915 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025915 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027956 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112057 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112057 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026722 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026722 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026722 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.707436 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.707436 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42425.552585 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42425.552585 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7023.657781 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7023.657781 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3339.812865 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3339.812865 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks +system.cpu1.dcache.writebacks::total 207281 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24884.764896 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24884.764896 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2294,18 +2330,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734300149849 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734300149849 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734300149849 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42635 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50404 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 8259c3ed2..e77a65365 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525889 # Number of seconds simulated -sim_ticks 2525888859000 # Number of ticks simulated -final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542203 # Number of seconds simulated +sim_ticks 2542202956000 # Number of ticks simulated +final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66506 # Simulator instruction rate (inst/s) -host_op_rate 85575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2785423099 # Simulator tick rate (ticks/s) -host_mem_usage 419792 # Number of bytes of host memory used -host_seconds 906.82 # Real time elapsed on the host -sim_insts 60309513 # Number of instructions simulated -sim_ops 77601128 # Number of ops (including micro ops) simulated +host_inst_rate 47189 # Simulator instruction rate (inst/s) +host_op_rate 56852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1989066585 # Simulator tick rate (ticks/s) +host_mem_usage 412724 # Number of bytes of host memory used +host_seconds 1278.09 # Real time elapsed on the host +sim_insts 60311945 # Number of instructions simulated +sim_ops 72661478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096846 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943526 # Per bank write bursts -system.physmem.perBankRdBursts::1 937990 # Per bank write bursts -system.physmem.perBankRdBursts::2 937469 # Per bank write bursts -system.physmem.perBankRdBursts::3 937431 # Per bank write bursts -system.physmem.perBankRdBursts::4 943079 # Per bank write bursts -system.physmem.perBankRdBursts::5 938170 # Per bank write bursts -system.physmem.perBankRdBursts::6 937203 # Per bank write bursts -system.physmem.perBankRdBursts::7 936910 # Per bank write bursts -system.physmem.perBankRdBursts::8 943866 # Per bank write bursts -system.physmem.perBankRdBursts::9 938107 # Per bank write bursts -system.physmem.perBankRdBursts::10 936563 # Per bank write bursts -system.physmem.perBankRdBursts::11 936045 # Per bank write bursts -system.physmem.perBankRdBursts::12 943886 # Per bank write bursts -system.physmem.perBankRdBursts::13 937531 # Per bank write bursts -system.physmem.perBankRdBursts::14 937186 # Per bank write bursts -system.physmem.perBankRdBursts::15 937024 # Per bank write bursts -system.physmem.perBankWrBursts::0 6617 # Per bank write bursts -system.physmem.perBankWrBursts::1 6376 # Per bank write bursts -system.physmem.perBankWrBursts::2 6529 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6459 # Per bank write bursts -system.physmem.perBankWrBursts::5 6705 # Per bank write bursts -system.physmem.perBankWrBursts::6 6711 # Per bank write bursts -system.physmem.perBankWrBursts::7 6649 # Per bank write bursts -system.physmem.perBankWrBursts::8 7036 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6111 # Per bank write bursts -system.physmem.perBankWrBursts::12 7073 # Per bank write bursts -system.physmem.perBankWrBursts::13 6679 # Per bank write bursts -system.physmem.perBankWrBursts::14 6963 # Per bank write bursts -system.physmem.perBankWrBursts::15 6824 # Per bank write bursts +system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.writeReqs 812506 # Number of write requests accepted +system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::1 955478 # Per bank write bursts +system.physmem.perBankRdBursts::2 953003 # Per bank write bursts +system.physmem.perBankRdBursts::3 951059 # Per bank write bursts +system.physmem.perBankRdBursts::4 958601 # Per bank write bursts +system.physmem.perBankRdBursts::5 955602 # Per bank write bursts +system.physmem.perBankRdBursts::6 952653 # Per bank write bursts +system.physmem.perBankRdBursts::7 950407 # Per bank write bursts +system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::9 955874 # Per bank write bursts +system.physmem.perBankRdBursts::10 952889 # Per bank write bursts +system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::12 956166 # Per bank write bursts +system.physmem.perBankRdBursts::13 955918 # Per bank write bursts +system.physmem.perBankRdBursts::14 953918 # Per bank write bursts +system.physmem.perBankRdBursts::15 950940 # Per bank write bursts +system.physmem.perBankWrBursts::0 6546 # Per bank write bursts +system.physmem.perBankWrBursts::1 6352 # Per bank write bursts +system.physmem.perBankWrBursts::2 6488 # Per bank write bursts +system.physmem.perBankWrBursts::3 6518 # Per bank write bursts +system.physmem.perBankWrBursts::4 6421 # Per bank write bursts +system.physmem.perBankWrBursts::5 6701 # Per bank write bursts +system.physmem.perBankWrBursts::6 6665 # Per bank write bursts +system.physmem.perBankWrBursts::7 6611 # Per bank write bursts +system.physmem.perBankWrBursts::8 6966 # Per bank write bursts +system.physmem.perBankWrBursts::9 6759 # Per bank write bursts +system.physmem.perBankWrBursts::10 6421 # Per bank write bursts +system.physmem.perBankWrBursts::11 6055 # Per bank write bursts +system.physmem.perBankWrBursts::12 7037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6645 # Per bank write bursts +system.physmem.perBankWrBursts::14 6920 # Per bank write bursts +system.physmem.perBankWrBursts::15 6806 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525887732500 # Total gap between requests +system.physmem.totGap 2542201638000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 14942208 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) +system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154600 # Read request sizes (log2) +system.physmem.readPktSize::6 153412 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58488 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,125 +208,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads -system.physmem.totQLat 389024977250 # Total ticks spent queuing -system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads +system.physmem.totQLat 395449280750 # Total ticks spent queuing +system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.99 # Data bus utilization in percentage -system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing -system.physmem.readRowHits 14042089 # Number of row buffer hits during reads -system.physmem.writeRowHits 91063 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing +system.physmem.readRowHits 14269193 # Number of row buffer hits during reads +system.physmem.writeRowHits 90708 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes -system.physmem.avgGap 158760.96 # Average gap between requests +system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes +system.physmem.avgGap 157821.19 # Average gap between requests system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states -system.physmem.memoryStateTime::REF 84344780000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states +system.physmem.memoryStateTime::REF 84889480000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states +system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54884184 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149487 # Transaction distribution -system.membus.trans_dist::ReadResp 16149487 # Transaction distribution -system.membus.trans_dist::WriteReq 763349 # Transaction distribution -system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution -system.membus.trans_dist::ReadExReq 131431 # Transaction distribution -system.membus.trans_dist::ReadExResp 131431 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55125441 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16348039 # Transaction distribution +system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution +system.membus.trans_dist::ReadExReq 131651 # Transaction distribution +system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138631350 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140140058 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,15 +334,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48271369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution -system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution -system.iobus.trans_dist::WriteReq 8174 # Transaction distribution -system.iobus.trans_dist::WriteResp 8174 # Transaction distribution +system.iobus.throughput 48580309 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -362,14 +362,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -389,18 +389,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121928114 # Total data (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -440,22 +440,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14910337 # Number of BP lookups -system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits +system.cpu.branchPred.lookups 13201290 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +479,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51097792 # DTB read hits -system.cpu.dtb.read_misses 64987 # DTB read misses -system.cpu.dtb.write_hits 11709971 # DTB write hits -system.cpu.dtb.write_misses 15921 # DTB write misses +system.cpu.dtb.read_hits 31642294 # DTB read hits +system.cpu.dtb.read_misses 39524 # DTB read misses +system.cpu.dtb.write_hits 11381361 # DTB write hits +system.cpu.dtb.write_misses 10135 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51162779 # DTB read accesses -system.cpu.dtb.write_accesses 11725892 # DTB write accesses +system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 31681818 # DTB read accesses +system.cpu.dtb.write_accesses 11391496 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62807763 # DTB hits -system.cpu.dtb.misses 80908 # DTB misses -system.cpu.dtb.accesses 62888671 # DTB accesses +system.cpu.dtb.hits 43023655 # DTB hits +system.cpu.dtb.misses 49659 # DTB misses +system.cpu.dtb.accesses 43073314 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,8 +519,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11575507 # ITB inst hits -system.cpu.itb.inst_misses 11335 # ITB inst misses +system.cpu.itb.inst_hits 24159481 # ITB inst hits +system.cpu.itb.inst_misses 10516 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -529,607 +529,598 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11586842 # ITB inst accesses -system.cpu.itb.hits 11575507 # DTB hits -system.cpu.itb.misses 11335 # DTB misses -system.cpu.itb.accesses 11586842 # DTB accesses -system.cpu.numCycles 476238509 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169997 # ITB inst accesses +system.cpu.itb.hits 24159481 # DTB hits +system.cpu.itb.misses 10516 # DTB misses +system.cpu.itb.accesses 24169997 # DTB accesses +system.cpu.numCycles 499350041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued -system.cpu.iq.rate 0.258180 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued +system.cpu.iq.rate 0.188050 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 226309 # number of nop insts executed -system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed -system.cpu.iew.exec_branches 11843747 # Number of branches executed -system.cpu.iew.exec_stores 12222179 # Number of stores executed -system.cpu.iew.exec_rate 0.253798 # Inst execution rate -system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47892202 # num instructions producing a value -system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value +system.cpu.iew.exec_nop 176010 # number of nop insts executed +system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791342 # Number of branches executed +system.cpu.iew.exec_stores 11888889 # Number of stores executed +system.cpu.iew.exec_rate 0.186738 # Inst execution rate +system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35465784 # num instructions producing a value +system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60459894 # Number of instructions committed -system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462326 # Number of instructions committed +system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386881 # Number of memory references committed -system.cpu.commit.loads 15654781 # Number of loads committed -system.cpu.commit.membars 403574 # Number of memory barriers committed -system.cpu.commit.branches 10306383 # Number of branches committed +system.cpu.commit.refs 25244569 # Number of memory references committed +system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.membars 403660 # Number of memory barriers committed +system.cpu.commit.branches 10308073 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191543 # Number of committed integer instructions. -system.cpu.commit.function_calls 991261 # Number of function calls committed. +system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction -system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction +system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239318561 # The number of ROB reads -system.cpu.rob.rob_writes 197472000 # The number of ROB writes -system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309513 # Number of Instructions Simulated -system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548833940 # number of integer regfile reads -system.cpu.int_regfile_writes 87707844 # number of integer regfile writes -system.cpu.fp_regfile_reads 8328 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 568287463 # The number of ROB reads +system.cpu.rob.rob_writes 154414560 # The number of ROB writes +system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311945 # Number of Instructions Simulated +system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116898 # number of integer regfile reads +system.cpu.int_regfile_writes 47012340 # number of integer regfile writes +system.cpu.fp_regfile_reads 8305 # number of floating regfile reads +system.cpu.fp_regfile_writes 2780 # number of floating regfile writes +system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes +system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes +system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980898 # number of replacements -system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 959881 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits -system.cpu.icache.overall_hits::total 10510158 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses -system.cpu.icache.overall_misses::total 1061739 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits +system.cpu.icache.overall_hits::total 23149457 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005369 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 64369 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 63302 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks +system.cpu.dcache.writebacks::total 599976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1435,16 +1437,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d741bed70..3b38aee5d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403860 # Number of seconds simulated -sim_ticks 2403859810000 # Number of ticks simulated -final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400983 # Number of seconds simulated +sim_ticks 2400982506000 # Number of ticks simulated +final_tick 2400982506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189252 # Simulator instruction rate (inst/s) -host_op_rate 243065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7540617560 # Simulator tick rate (ticks/s) -host_mem_usage 419508 # Number of bytes of host memory used -host_seconds 318.79 # Real time elapsed on the host -sim_insts 60331162 # Number of instructions simulated -sim_ops 77486236 # Number of ops (including micro ops) simulated +host_inst_rate 112943 # Simulator instruction rate (inst/s) +host_op_rate 135898 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4496473277 # Simulator tick rate (ticks/s) +host_mem_usage 411684 # Number of bytes of host memory used +host_seconds 533.97 # Real time elapsed on the host +sim_insts 60307964 # Number of instructions simulated +sim_ops 72565708 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 493064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6826968 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 75520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 799936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1451264 # Number of bytes read from this memory +system.physmem.bytes_read::total 124655200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 493064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 75520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 757000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3741312 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1144164 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1712388 # Number of bytes written to this memory +system.physmem.bytes_written::total 6757128 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 106697 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1180 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 22676 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 286041 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 428097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812412 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47821703 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 205359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2843406 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31454 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 333170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 604446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51918412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 205359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558242 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 476540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 713203 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2814318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47821703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 205359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3319946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13444811 # Number of read requests accepted -system.physmem.writeReqs 446538 # Number of write requests accepted -system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835670 # Per bank write bursts -system.physmem.perBankRdBursts::1 835346 # Per bank write bursts -system.physmem.perBankRdBursts::2 835517 # Per bank write bursts -system.physmem.perBankRdBursts::3 836010 # Per bank write bursts -system.physmem.perBankRdBursts::4 837094 # Per bank write bursts -system.physmem.perBankRdBursts::5 837780 # Per bank write bursts -system.physmem.perBankRdBursts::6 837922 # Per bank write bursts -system.physmem.perBankRdBursts::7 839142 # Per bank write bursts -system.physmem.perBankRdBursts::8 840618 # Per bank write bursts -system.physmem.perBankRdBursts::9 843327 # Per bank write bursts -system.physmem.perBankRdBursts::10 843373 # Per bank write bursts -system.physmem.perBankRdBursts::11 843894 # Per bank write bursts -system.physmem.perBankRdBursts::12 845193 # Per bank write bursts -system.physmem.perBankRdBursts::13 844981 # Per bank write bursts -system.physmem.perBankRdBursts::14 844356 # Per bank write bursts -system.physmem.perBankRdBursts::15 844587 # Per bank write bursts -system.physmem.perBankWrBursts::0 2683 # Per bank write bursts -system.physmem.perBankWrBursts::1 2536 # Per bank write bursts -system.physmem.perBankWrBursts::2 2524 # Per bank write bursts -system.physmem.perBankWrBursts::3 3040 # Per bank write bursts -system.physmem.perBankWrBursts::4 3434 # Per bank write bursts -system.physmem.perBankWrBursts::5 3138 # Per bank write bursts -system.physmem.perBankWrBursts::6 2510 # Per bank write bursts -system.physmem.perBankWrBursts::7 2271 # Per bank write bursts -system.physmem.perBankWrBursts::8 2160 # Per bank write bursts -system.physmem.perBankWrBursts::9 2378 # Per bank write bursts -system.physmem.perBankWrBursts::10 2319 # Per bank write bursts -system.physmem.perBankWrBursts::11 2803 # Per bank write bursts -system.physmem.perBankWrBursts::12 3771 # Per bank write bursts -system.physmem.perBankWrBursts::13 3447 # Per bank write bursts -system.physmem.perBankWrBursts::14 2601 # Per bank write bursts -system.physmem.perBankWrBursts::15 2498 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 31454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 399503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1317649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13448319 # Number of read requests accepted +system.physmem.writeReqs 485647 # Number of write requests accepted +system.physmem.readBursts 13448319 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 485647 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860692416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 3019520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109787968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3006628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 438446 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835559 # Per bank write bursts +system.physmem.perBankRdBursts::1 835684 # Per bank write bursts +system.physmem.perBankRdBursts::2 835582 # Per bank write bursts +system.physmem.perBankRdBursts::3 835955 # Per bank write bursts +system.physmem.perBankRdBursts::4 836860 # Per bank write bursts +system.physmem.perBankRdBursts::5 838029 # Per bank write bursts +system.physmem.perBankRdBursts::6 838426 # Per bank write bursts +system.physmem.perBankRdBursts::7 839444 # Per bank write bursts +system.physmem.perBankRdBursts::8 841128 # Per bank write bursts +system.physmem.perBankRdBursts::9 843519 # Per bank write bursts +system.physmem.perBankRdBursts::10 843777 # Per bank write bursts +system.physmem.perBankRdBursts::11 843721 # Per bank write bursts +system.physmem.perBankRdBursts::12 845312 # Per bank write bursts +system.physmem.perBankRdBursts::13 845603 # Per bank write bursts +system.physmem.perBankRdBursts::14 845260 # Per bank write bursts +system.physmem.perBankRdBursts::15 844460 # Per bank write bursts +system.physmem.perBankWrBursts::0 2621 # Per bank write bursts +system.physmem.perBankWrBursts::1 2605 # Per bank write bursts +system.physmem.perBankWrBursts::2 2850 # Per bank write bursts +system.physmem.perBankWrBursts::3 3117 # Per bank write bursts +system.physmem.perBankWrBursts::4 3557 # Per bank write bursts +system.physmem.perBankWrBursts::5 3522 # Per bank write bursts +system.physmem.perBankWrBursts::6 2837 # Per bank write bursts +system.physmem.perBankWrBursts::7 2549 # Per bank write bursts +system.physmem.perBankWrBursts::8 2654 # Per bank write bursts +system.physmem.perBankWrBursts::9 2632 # Per bank write bursts +system.physmem.perBankWrBursts::10 2402 # Per bank write bursts +system.physmem.perBankWrBursts::11 2522 # Per bank write bursts +system.physmem.perBankWrBursts::12 3817 # Per bank write bursts +system.physmem.perBankWrBursts::13 3843 # Per bank write bursts +system.physmem.perBankWrBursts::14 3141 # Per bank write bursts +system.physmem.perBankWrBursts::15 2511 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402823771000 # Total gap between requests +system.physmem.totGap 2398981428000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13409088 # Read request sizes (log2) +system.physmem.readPktSize::3 13409008 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35723 # Read request sizes (log2) +system.physmem.readPktSize::6 39311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429341 # Write request sizes (log2) +system.physmem.writePktSize::2 467913 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17734 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 878886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 855155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 940592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 914649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2399113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2323436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3041002 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 79661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 76726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,42 +178,42 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,83 +242,84 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 866402 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.895132 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.187701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.697526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8320 0.96% 0.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8911 1.03% 1.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6111 0.71% 2.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 785 0.09% 2.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 956 0.11% 2.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 773 0.09% 2.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7768 0.90% 3.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 290 0.03% 3.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832488 96.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866402 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2583 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5206.469222 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249565.705681 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2582 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads -system.physmem.totQLat 346456254750 # Total ticks spent queuing -system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2583 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.265583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.091885 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.157240 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 3 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 2 0.08% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.04% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.12% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 4 0.15% 0.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 537 20.79% 21.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.27% 21.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 754 29.19% 51.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1050 40.65% 91.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 100 3.87% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 31 1.20% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.77% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.58% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.35% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.12% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.27% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.19% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.19% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.19% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.23% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.15% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.19% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2583 # Writes before turning the bus around for reads +system.physmem.totQLat 346447958000 # Total ticks spent queuing +system.physmem.totMemAccLat 598603939250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67241595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25761.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44511.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing -system.physmem.readRowHits 12585053 # Number of row buffer hits during reads -system.physmem.writeRowHits 37880 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.91 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.57 # Average write queue length when enqueuing +system.physmem.readRowHits 12588353 # Number of row buffer hits during reads +system.physmem.writeRowHits 40744 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes -system.physmem.avgGap 172972.67 # Average gap between requests +system.physmem.writeRowHitRate 86.32 # Row buffer hit rate for writes +system.physmem.avgGap 172167.88 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states -system.physmem.memoryStateTime::REF 80270060000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2165142880250 # Time in different power states +system.physmem.memoryStateTime::REF 80173860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states +system.physmem.memoryStateTime::ACT 155659356000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -332,322 +333,323 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55668579 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13780402 # Transaction distribution -system.membus.trans_dist::ReadResp 13780402 # Transaction distribution -system.membus.trans_dist::WriteReq 432242 # Transaction distribution -system.membus.trans_dist::WriteResp 432242 # Transaction distribution -system.membus.trans_dist::Writeback 17197 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution -system.membus.trans_dist::ReadExReq 28083 # Transaction distribution -system.membus.trans_dist::ReadExResp 28083 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133819459 # Total data (bytes) +system.membus.throughput 55731244 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13775425 # Transaction distribution +system.membus.trans_dist::ReadResp 13775425 # Transaction distribution +system.membus.trans_dist::WriteReq 471057 # Transaction distribution +system.membus.trans_dist::WriteResp 471057 # Transaction distribution +system.membus.trans_dist::Writeback 17734 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2870 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2870 # Transaction distribution +system.membus.trans_dist::ReadExReq 31339 # Transaction distribution +system.membus.trans_dist::ReadExResp 31339 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 722736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1037922 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1761100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26818016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28579116 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 726717 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5522532 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6250133 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107272064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113522197 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133809743 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 411651000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 449000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14570118500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 14677819500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1595700088 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1677943291 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33207877250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33210614750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63255 # number of replacements -system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use -system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor +system.l2c.tags.replacements 63162 # number of replacements +system.l2c.tags.tagsinuse 50410.338960 # Cycle average of tags in use +system.l2c.tags.total_refs 1759139 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128553 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.684154 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2389834567500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36865.555388 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4868.284859 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3674.892610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993335 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 794.582710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 806.547655 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832999 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1730.563101 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1659.086161 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562524 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074284 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.056074 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768978 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65393 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55911 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997818 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17684075 # Number of tag accesses -system.l2c.tags.data_accesses 17684075 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8753 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3188 # 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012307 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.026406 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.025316 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769201 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3043 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6074 # 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average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -800,52 +802,51 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58812389 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141273763 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks) +system.toL2Bus.throughput 59108244 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1059674 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1059674 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 471057 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 471057 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275568 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1835 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1835 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 93577 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 93577 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 911138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2522746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20145 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55378 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3509407 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29133952 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 38939733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 68189241 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141801951 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 115908 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2288858155 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2052757055 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1915102818 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13212439 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33686507 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758810 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution -system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution -system.iobus.trans_dist::WriteReq 2835 # Transaction distribution -system.iobus.trans_dist::WriteResp 2835 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48817267 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13767391 # Transaction distribution +system.iobus.trans_dist::ReadResp 13767391 # Transaction distribution +system.iobus.trans_dist::WriteReq 2985 # Transaction distribution +system.iobus.trans_dist::WriteResp 2985 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 12256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3140 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 288 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 706746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -861,18 +862,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 722736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26818016 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27540752 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 16027 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 576 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 703222 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -888,18 +889,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209343 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 726717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 107998781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209403 # Total data (bytes) +system.iobus.reqLayer0.occupancy 8657000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1570000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -907,7 +908,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 353820000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -939,11 +940,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13409008000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 719751000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33775984250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -968,25 +969,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7992228 # DTB read hits -system.cpu0.dtb.read_misses 6211 # DTB read misses -system.cpu0.dtb.write_hits 6585208 # DTB write hits -system.cpu0.dtb.write_misses 1983 # DTB write misses -system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6543805 # DTB read hits +system.cpu0.dtb.read_misses 5435 # DTB read misses +system.cpu0.dtb.write_hits 6063639 # DTB write hits +system.cpu0.dtb.write_misses 1808 # DTB write misses +system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5223 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 107 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7998439 # DTB read accesses -system.cpu0.dtb.write_accesses 6587191 # DTB write accesses +system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6549240 # DTB read accesses +system.cpu0.dtb.write_accesses 6065447 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14577436 # DTB hits -system.cpu0.dtb.misses 8194 # DTB misses -system.cpu0.dtb.accesses 14585630 # DTB accesses +system.cpu0.dtb.hits 12607444 # DTB hits +system.cpu0.dtb.misses 7243 # DTB misses +system.cpu0.dtb.accesses 12614687 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1008,468 +1009,486 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32348466 # ITB inst hits -system.cpu0.itb.inst_misses 3468 # ITB inst misses +system.cpu0.itb.inst_hits 30119411 # ITB inst hits +system.cpu0.itb.inst_misses 2986 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2362 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses -system.cpu0.itb.hits 32348466 # DTB hits -system.cpu0.itb.misses 3468 # DTB misses -system.cpu0.itb.accesses 32351934 # DTB accesses -system.cpu0.numCycles 113676157 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30122397 # ITB inst accesses +system.cpu0.itb.hits 30119411 # DTB hits +system.cpu0.itb.misses 2986 # DTB misses +system.cpu0.itb.accesses 30122397 # DTB accesses +system.cpu0.numCycles 109377986 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31863567 # Number of instructions committed -system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses -system.cpu0.num_func_calls 1197302 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37388293 # number of integer instructions -system.cpu0.num_fp_insts 5018 # number of float instructions -system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written -system.cpu0.num_mem_refs 15242780 # number of memory refs -system.cpu0.num_load_insts 8359522 # Number of load instructions -system.cpu0.num_store_insts 6883258 # Number of store instructions -system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles -system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles -system.cpu0.Branches 5616963 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction -system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1435 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.78% # Class of executed instruction -system.cpu0.op_class::MemRead 8359522 19.86% 83.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 6883258 16.36% 100.00% # Class of executed instruction +system.cpu0.committedInsts 29708958 # Number of instructions committed +system.cpu0.committedOps 36436691 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32091710 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses +system.cpu0.num_func_calls 1119227 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3806697 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32091710 # number of integer instructions +system.cpu0.num_fp_insts 4289 # number of float instructions +system.cpu0.num_int_register_reads 59433720 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21150393 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 109113758 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14198144 # number of times the CC registers were written +system.cpu0.num_mem_refs 13068134 # number of memory refs +system.cpu0.num_load_insts 6718957 # Number of load instructions +system.cpu0.num_store_insts 6349177 # Number of store instructions +system.cpu0.num_idle_cycles 107075141.411044 # Number of idle cycles +system.cpu0.num_busy_cycles 2302844.588956 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021054 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978946 # Percentage of idle cycles +system.cpu0.Branches 5297571 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11842 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23375924 64.04% 64.07% # Class of executed instruction +system.cpu0.op_class::IntMult 45526 0.12% 64.20% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1430 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::MemRead 6718957 18.41% 82.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 6349177 17.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 42085609 # Class of executed instruction +system.cpu0.op_class::total 36502856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891568 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602608 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43675041 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892080 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.958660 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8174940250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.966915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.710732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.924961 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964779 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015060 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019385 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82922 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 899179 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.616650 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41225487 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 899691 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.821829 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7765042250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.273634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.912581 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.430435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967331 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011548 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020372 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999251 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45483451 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45483451 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31876897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8043794 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3754350 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43675041 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31876897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8043794 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3754350 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43675041 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31876897 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8043794 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3754350 # number of overall hits -system.cpu0.icache.overall_hits::total 43675041 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 474237 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 131660 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 310425 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916322 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 474237 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 131660 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 310425 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916322 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 474237 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 131660 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 310425 # number of overall misses -system.cpu0.icache.overall_misses::total 916322 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1777118000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4193284063 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5970402063 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1777118000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4193284063 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5970402063 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1777118000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4193284063 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5970402063 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32351134 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8175454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4064775 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44591363 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32351134 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8175454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4064775 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44591363 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32351134 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8175454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4064775 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44591363 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014659 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016104 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076370 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020549 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014659 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016104 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076370 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020549 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014659 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016104 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076370 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020549 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13497.782166 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13508.203473 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6515.615758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6515.615758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13497.782166 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13508.203473 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6515.615758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3442 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43052663 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43052663 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29678002 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7860593 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3686892 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41225487 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29678002 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7860593 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3686892 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41225487 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29678002 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7860593 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3686892 # number of overall hits +system.cpu0.icache.overall_hits::total 41225487 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 443773 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9490.532076 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7113.102438 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # 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average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597941 # number of writebacks +system.cpu0.dcache.writebacks::total 597941 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 82 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146159 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5024090738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1767125017 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3901843974 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5668968991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27358748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27904372000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55263120000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1501669410 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14569249955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16070919365 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28860417410 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42473621955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71334039365 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030412 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022156 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013024 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022380 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020276 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009335 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.413658 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363378 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197185 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044111 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044956 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021722 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026680 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021412 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011327 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024102 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.012886 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1503,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096820 # DTB read hits -system.cpu1.dtb.read_misses 2107 # DTB read misses -system.cpu1.dtb.write_hits 1423125 # DTB write hits -system.cpu1.dtb.write_misses 370 # DTB write misses -system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 1746639 # DTB read hits +system.cpu1.dtb.read_misses 1917 # DTB read misses +system.cpu1.dtb.write_hits 1378449 # DTB write hits +system.cpu1.dtb.write_misses 367 # DTB write misses +system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1626 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 33 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098927 # DTB read accesses -system.cpu1.dtb.write_accesses 1423495 # DTB write accesses +system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 1748556 # DTB read accesses +system.cpu1.dtb.write_accesses 1378816 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519945 # DTB hits -system.cpu1.dtb.misses 2477 # DTB misses -system.cpu1.dtb.accesses 3522422 # DTB accesses +system.cpu1.dtb.hits 3125088 # DTB hits +system.cpu1.dtb.misses 2284 # DTB misses +system.cpu1.dtb.accesses 3127372 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1543,96 +1562,98 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8175454 # ITB inst hits -system.cpu1.itb.inst_misses 1196 # ITB inst misses +system.cpu1.itb.inst_hits 7981130 # ITB inst hits +system.cpu1.itb.inst_misses 1058 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 834 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses -system.cpu1.itb.hits 8175454 # DTB hits -system.cpu1.itb.misses 1196 # DTB misses -system.cpu1.itb.accesses 8176650 # DTB accesses -system.cpu1.numCycles 584791217 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7982188 # ITB inst accesses +system.cpu1.itb.hits 7981130 # DTB hits +system.cpu1.itb.misses 1058 # DTB misses +system.cpu1.itb.accesses 7982188 # DTB accesses +system.cpu1.numCycles 582833153 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7972563 # Number of instructions committed -system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses -system.cpu1.num_func_calls 305506 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9111769 # number of integer instructions -system.cpu1.num_fp_insts 2002 # number of float instructions -system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3688880 # number of memory refs -system.cpu1.num_load_insts 2190803 # Number of load instructions -system.cpu1.num_store_insts 1498077 # Number of store instructions -system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles -system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles -system.cpu1.Branches 1447411 # Number of branches fetched -system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction -system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction -system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7797141 # Number of instructions committed +system.cpu1.committedOps 9191219 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 8219243 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses +system.cpu1.num_func_calls 289029 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 993030 # number of instructions that are conditional controls +system.cpu1.num_int_insts 8219243 # number of integer instructions +system.cpu1.num_fp_insts 1689 # number of float instructions +system.cpu1.num_int_register_reads 14554839 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5500250 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 33218155 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 3793046 # number of times the CC registers were written +system.cpu1.num_mem_refs 3251661 # number of memory refs +system.cpu1.num_load_insts 1804549 # Number of load instructions +system.cpu1.num_store_insts 1447112 # Number of store instructions +system.cpu1.num_idle_cycles 548698663.963538 # Number of idle cycles +system.cpu1.num_busy_cycles 34134489.036462 # Number of busy cycles +system.cpu1.not_idle_fraction 0.058566 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.941434 # Percentage of idle cycles +system.cpu1.Branches 1360376 # Number of branches fetched +system.cpu1.op_class::No_OpClass 4595 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6078995 65.05% 65.10% # Class of executed instruction +system.cpu1.op_class::IntMult 10163 0.11% 65.20% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 281 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::MemRead 1804549 19.31% 84.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 1447112 15.48% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 10324133 # Class of executed instruction +system.cpu1.op_class::total 9345695 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4844951 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits +system.cpu2.branchPred.lookups 5844133 # Number of BP lookups +system.cpu2.branchPred.condPredicted 4389690 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 248799 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3701982 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2861782 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 77.304050 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 588875 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15609 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1656,25 +1677,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10946099 # DTB read hits -system.cpu2.dtb.read_misses 23259 # DTB read misses -system.cpu2.dtb.write_hits 3358425 # DTB write hits -system.cpu2.dtb.write_misses 6569 # DTB write misses -system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 13926534 # DTB read hits +system.cpu2.dtb.read_misses 28241 # DTB read misses +system.cpu2.dtb.write_hits 3979346 # DTB write hits +system.cpu2.dtb.write_misses 9743 # DTB write misses +system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2739 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 445 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 255 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10969358 # DTB read accesses -system.cpu2.dtb.write_accesses 3364994 # DTB write accesses +system.cpu2.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 13954775 # DTB read accesses +system.cpu2.dtb.write_accesses 3989089 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14304524 # DTB hits -system.cpu2.dtb.misses 29828 # DTB misses -system.cpu2.dtb.accesses 14334352 # DTB accesses +system.cpu2.dtb.hits 17905880 # DTB hits +system.cpu2.dtb.misses 37984 # DTB misses +system.cpu2.dtb.accesses 17943864 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1696,329 +1717,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4066170 # ITB inst hits -system.cpu2.itb.inst_misses 4558 # ITB inst misses +system.cpu2.itb.inst_hits 4053038 # ITB inst hits +system.cpu2.itb.inst_misses 6578 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 2058 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 2441 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses -system.cpu2.itb.hits 4066170 # DTB hits -system.cpu2.itb.misses 4558 # DTB misses -system.cpu2.itb.accesses 4070728 # DTB accesses -system.cpu2.numCycles 88357644 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059616 # ITB inst accesses +system.cpu2.itb.hits 4053038 # DTB hits +system.cpu2.itb.misses 6578 # DTB misses +system.cpu2.itb.accesses 4059616 # DTB accesses +system.cpu2.numCycles 88208146 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10487397 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32911643 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 5844133 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 3450657 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 74966701 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 679472 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 80302 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 72243 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 1263867 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 410 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050067 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 153217 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2804 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 87212188 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 0.443226 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.629212 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 79899565 91.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 625094 0.72% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 698013 0.80% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 764181 0.88% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 868461 1.00% 95.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 574503 0.66% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 981504 1.13% 96.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 301305 0.35% 97.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2499562 2.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 87212188 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.066254 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.373113 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8569138 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 72587758 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 4831209 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 941079 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 281926 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 736866 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 58789 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34844703 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 196626 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 281926 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9031224 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 19204705 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13140033 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5253439 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 40299841 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33794581 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 29618551 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 37683898 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1100267 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 36626919 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 154339316 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41664821 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4127 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 28795876 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 7831027 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 344066 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 286541 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5082070 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6089915 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 4400227 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 719431 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1142118 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32029170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 669683 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 38616590 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 44993 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5567256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12099893 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 238978 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 87212188 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.442789 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.239118 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73763195 84.58% 84.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4095516 4.70% 89.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2328743 2.67% 91.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2051674 2.35% 94.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2976748 3.41% 97.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 798764 0.92% 98.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 739781 0.85% 99.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 293068 0.34% 99.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 164699 0.19% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 87212188 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 122993 5.40% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1970586 86.46% 91.85% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 185678 8.15% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 12081 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 20207276 52.33% 52.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 34218 0.09% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 404 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.45% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 14176555 36.71% 89.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 4186056 10.84% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued -system.cpu2.iq.rate 0.394298 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 38616590 # Type of FU issued +system.cpu2.iq.rate 0.437789 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2279258 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.059023 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 166760031 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 38278238 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29588244 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 40878658 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5109 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 176007 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1107424 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2018 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 18033 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 469449 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5207867 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 3518142 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 281926 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 17856855 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 716566 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32817404 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 57776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6089915 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 4400227 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 491578 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 63121 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 616282 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 18033 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 121106 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 106258 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 227364 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 38297957 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 14051286 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 280797 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 84315 # number of nop insts executed -system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3774133 # Number of branches executed -system.cpu2.iew.exec_stores 3493369 # Number of stores executed -system.cpu2.iew.exec_rate 0.383919 # Inst execution rate -system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16326972 # num instructions producing a value -system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value +system.cpu2.iew.exec_nop 118551 # number of nop insts executed +system.cpu2.iew.exec_refs 18186993 # number of memory reference insts executed +system.cpu2.iew.exec_branches 4220297 # Number of branches executed +system.cpu2.iew.exec_stores 4135707 # Number of stores executed +system.cpu2.iew.exec_rate 0.434177 # Inst execution rate +system.cpu2.iew.wb_sent 34852514 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29592548 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17266310 # num instructions producing a value +system.cpu2.iew.wb_consumers 30698955 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.335485 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.562440 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 5479640 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 430705 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 190919 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86342246 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.312843 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.237203 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 77364915 89.60% 89.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4177735 4.84% 94.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1290086 1.49% 95.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 753837 0.87% 96.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 490440 0.57% 97.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 381562 0.44% 97.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 374801 0.43% 98.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 197147 0.23% 98.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1311723 1.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20550287 # Number of instructions committed -system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86342246 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 22875674 # Number of instructions committed +system.cpu2.commit.committedOps 27011607 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8440164 # Number of memory references committed -system.cpu2.commit.loads 5095105 # Number of loads committed -system.cpu2.commit.membars 94591 # Number of memory barriers committed -system.cpu2.commit.branches 3237542 # Number of branches committed -system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295831 # Number of function calls committed. +system.cpu2.commit.refs 8913269 # Number of memory references committed +system.cpu2.commit.loads 4982491 # Number of loads committed +system.cpu2.commit.membars 117220 # Number of memory barriers committed +system.cpu2.commit.branches 3644555 # Number of branches committed +system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 23908542 # Number of committed integer instructions. +system.cpu2.commit.function_calls 341319 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 18065773 66.88% 66.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 32161 0.12% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 404 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 4982491 18.45% 85.45% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3930778 14.55% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 27011607 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1311723 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66778885 # The number of ROB reads -system.cpu2.rob.rob_writes 66779605 # The number of ROB writes -system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20495032 # Number of Instructions Simulated -system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads -system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes +system.cpu2.rob.rob_reads 116854146 # The number of ROB reads +system.cpu2.rob.rob_writes 65855440 # The number of ROB writes +system.cpu2.timesIdled 179134 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 995958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3544369510 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 22801865 # Number of Instructions Simulated +system.cpu2.committedOps 26937798 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 3.868462 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.868462 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.258501 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.258501 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 45014030 # number of integer regfile reads +system.cpu2.int_regfile_writes 19144459 # number of integer regfile writes +system.cpu2.fp_regfile_reads 47113 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes +system.cpu2.cc_regfile_reads 130800569 # number of cc regfile reads +system.cpu2.cc_regfile_writes 12559359 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124603397 # number of misc regfile reads +system.cpu2.misc_regfile_writes 350092 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2035,10 +2056,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536004079250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 4b7f3d43e..055919fe9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550237 # Number of seconds simulated -sim_ticks 2550237191000 # Number of ticks simulated -final_tick 2550237191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.539697 # Number of seconds simulated +sim_ticks 2539696838000 # Number of ticks simulated +final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66377 # Simulator instruction rate (inst/s) -host_op_rate 85409 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2806608319 # Simulator tick rate (ticks/s) -host_mem_usage 421988 # Number of bytes of host memory used -host_seconds 908.65 # Real time elapsed on the host -sim_insts 60314055 # Number of instructions simulated -sim_ops 77607027 # Number of ops (including micro ops) simulated +host_inst_rate 33216 # Simulator instruction rate (inst/s) +host_op_rate 40018 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1398403355 # Simulator tick rate (ticks/s) +host_mem_usage 411672 # Number of bytes of host memory used +host_seconds 1816.14 # Real time elapsed on the host +sim_insts 60325607 # Number of instructions simulated +sim_ops 72677421 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 507520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5298200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3795584 # Number of bytes read from this memory -system.physmem.bytes_read::total 131007192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 507520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494672 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802312 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory +system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7930 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 59306 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59160 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380350 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373668 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47489907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2077532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1488326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51370591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586091 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2667325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47489907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2674104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2074417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54037916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293487 # Number of read requests accepted -system.physmem.writeReqs 813178 # Number of write requests accepted -system.physmem.readBursts 15293487 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813178 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977052352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1730816 # Total number of bytes read from write queue -system.physmem.bytesWritten 6829312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131007192 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6802312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 27044 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706441 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4687 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955866 # Per bank write bursts -system.physmem.perBankRdBursts::1 953274 # Per bank write bursts -system.physmem.perBankRdBursts::2 953247 # Per bank write bursts -system.physmem.perBankRdBursts::3 953514 # Per bank write bursts -system.physmem.perBankRdBursts::4 955750 # Per bank write bursts -system.physmem.perBankRdBursts::5 953800 # Per bank write bursts -system.physmem.perBankRdBursts::6 953588 # Per bank write bursts -system.physmem.perBankRdBursts::7 953504 # Per bank write bursts -system.physmem.perBankRdBursts::8 956261 # Per bank write bursts -system.physmem.perBankRdBursts::9 953859 # Per bank write bursts -system.physmem.perBankRdBursts::10 953506 # Per bank write bursts -system.physmem.perBankRdBursts::11 952990 # Per bank write bursts -system.physmem.perBankRdBursts::12 956201 # Per bank write bursts -system.physmem.perBankRdBursts::13 953861 # Per bank write bursts -system.physmem.perBankRdBursts::14 953718 # Per bank write bursts -system.physmem.perBankRdBursts::15 953504 # Per bank write bursts -system.physmem.perBankWrBursts::0 6593 # Per bank write bursts -system.physmem.perBankWrBursts::1 6395 # Per bank write bursts -system.physmem.perBankWrBursts::2 6535 # Per bank write bursts -system.physmem.perBankWrBursts::3 6562 # Per bank write bursts -system.physmem.perBankWrBursts::4 6485 # Per bank write bursts -system.physmem.perBankWrBursts::5 6754 # Per bank write bursts -system.physmem.perBankWrBursts::6 6752 # Per bank write bursts -system.physmem.perBankWrBursts::7 6692 # Per bank write bursts -system.physmem.perBankWrBursts::8 7013 # Per bank write bursts -system.physmem.perBankWrBursts::9 6813 # Per bank write bursts -system.physmem.perBankWrBursts::10 6467 # Per bank write bursts -system.physmem.perBankWrBursts::11 6119 # Per bank write bursts -system.physmem.perBankWrBursts::12 7057 # Per bank write bursts -system.physmem.perBankWrBursts::13 6685 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 184891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2072011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2694403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293132 # Number of read requests accepted +system.physmem.writeReqs 812993 # Number of write requests accepted +system.physmem.readBursts 15293132 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812993 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 975241856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue +system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6790472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 54978 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4635 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 954958 # Per bank write bursts +system.physmem.perBankRdBursts::1 950647 # Per bank write bursts +system.physmem.perBankRdBursts::2 950811 # Per bank write bursts +system.physmem.perBankRdBursts::3 950999 # Per bank write bursts +system.physmem.perBankRdBursts::4 954856 # Per bank write bursts +system.physmem.perBankRdBursts::5 951881 # Per bank write bursts +system.physmem.perBankRdBursts::6 951736 # Per bank write bursts +system.physmem.perBankRdBursts::7 951699 # Per bank write bursts +system.physmem.perBankRdBursts::8 955454 # Per bank write bursts +system.physmem.perBankRdBursts::9 951840 # Per bank write bursts +system.physmem.perBankRdBursts::10 951452 # Per bank write bursts +system.physmem.perBankRdBursts::11 951010 # Per bank write bursts +system.physmem.perBankRdBursts::12 955349 # Per bank write bursts +system.physmem.perBankRdBursts::13 951888 # Per bank write bursts +system.physmem.perBankRdBursts::14 952124 # Per bank write bursts +system.physmem.perBankRdBursts::15 951450 # Per bank write bursts +system.physmem.perBankWrBursts::0 6588 # Per bank write bursts +system.physmem.perBankWrBursts::1 6390 # Per bank write bursts +system.physmem.perBankWrBursts::2 6534 # Per bank write bursts +system.physmem.perBankWrBursts::3 6563 # Per bank write bursts +system.physmem.perBankWrBursts::4 6471 # Per bank write bursts +system.physmem.perBankWrBursts::5 6764 # Per bank write bursts +system.physmem.perBankWrBursts::6 6747 # Per bank write bursts +system.physmem.perBankWrBursts::7 6681 # Per bank write bursts +system.physmem.perBankWrBursts::8 6996 # Per bank write bursts +system.physmem.perBankWrBursts::9 6810 # Per bank write bursts +system.physmem.perBankWrBursts::10 6454 # Per bank write bursts +system.physmem.perBankWrBursts::11 6114 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 6669 # Per bank write bursts system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6821 # Per bank write bursts +system.physmem.perBankWrBursts::15 6837 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550236004000 # Total gap between requests +system.physmem.totGap 2539695718000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 38 # Read request sizes (log2) -system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::2 18 # Read request sizes (log2) +system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154633 # Read request sizes (log2) +system.physmem.readPktSize::6 154288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59160 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1068642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1003556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 964678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1068028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3400925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 102170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 95874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58975 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1062790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 969024 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1031345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3403260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 99295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 93778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 90278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,96 +225,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1011151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.031391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 908.214038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 201.586844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22832 2.26% 2.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19987 1.98% 4.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8899 0.88% 5.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2276 0.23% 5.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 0.21% 5.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1805 0.18% 5.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9141 0.90% 6.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 764 0.08% 6.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943330 93.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1011151 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2512.992263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47101.457482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6047 99.54% 99.54% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 7 0.12% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1008721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.577780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.477346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22290 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20048 1.99% 4.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8821 0.87% 5.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2154 0.21% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2027 0.20% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1663 0.16% 5.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9185 0.91% 6.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 821 0.08% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008721 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47472.970867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.565103 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.376946 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 6 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 5 0.08% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.03% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.03% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 4 0.07% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.08% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.03% 0.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2721 44.79% 45.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 38 0.63% 46.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1583 26.06% 72.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1297 21.35% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.50% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 44 0.72% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 54 0.89% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.79% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.48% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.30% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 20 0.33% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.28% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 13 0.21% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.26% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 12 0.20% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 10 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads -system.physmem.totQLat 393209260500 # Total ticks spent queuing -system.physmem.totMemAccLat 679455066750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76332215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25756.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.390583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.344347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.03% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 3 0.05% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 4 0.07% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 3 0.05% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.02% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 392019251500 # Total ticks spent queuing +system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44506.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 383.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.01 # Data bus utilization in percentage -system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.02 # Data bus utilization in percentage +system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.37 # Average write queue length when enqueuing -system.physmem.readRowHits 14270960 # Number of row buffer hits during reads -system.physmem.writeRowHits 91040 # Number of row buffer hits during writes +system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing +system.physmem.readRowHits 14244888 # Number of row buffer hits during reads +system.physmem.writeRowHits 91209 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.29 # Row buffer hit rate for writes -system.physmem.avgGap 158334.21 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2202305646000 # Time in different power states -system.physmem.memoryStateTime::REF 85157800000 # Time in different power states +system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes +system.physmem.avgGap 157685.09 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states +system.physmem.memoryStateTime::REF 84806020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262767276500 # Time in different power states +system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -328,289 +328,280 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54978267 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346128 # Transaction distribution -system.membus.trans_dist::ReadResp 16346128 # Transaction distribution -system.membus.trans_dist::WriteReq 763361 # Transaction distribution -system.membus.trans_dist::WriteResp 763361 # Transaction distribution -system.membus.trans_dist::Writeback 59160 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4685 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4687 # Transaction distribution -system.membus.trans_dist::ReadExReq 131439 # Transaction distribution -system.membus.trans_dist::ReadExResp 131439 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383052 # Packet count per connected master and slave (bytes) +system.membus.throughput 55193080 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16345666 # Transaction distribution +system.membus.trans_dist::ReadResp 16345666 # Transaction distribution +system.membus.trans_dist::WriteReq 763357 # Transaction distribution +system.membus.trans_dist::WriteResp 763357 # Transaction distribution +system.membus.trans_dist::Writeback 58975 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution +system.membus.trans_dist::ReadExReq 131547 # Transaction distribution +system.membus.trans_dist::ReadExResp 131547 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550390 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390470 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698976 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19097094 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140207622 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140207622 # Total data (bytes) +system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140173690 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487194000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3622500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17516054500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4714051227 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37455331951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64405 # number of replacements -system.l2c.tags.tagsinuse 51448.142618 # Cycle average of tags in use -system.l2c.tags.total_refs 1904465 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129797 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.672643 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2540066144500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37002.110374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 24.124150 # Average occupied blocks per requestor +system.l2c.tags.replacements 64063 # number of replacements +system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use +system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4932.290143 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3309.962047 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.942781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3265.462064 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2905.250809 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000368 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044331 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785036 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65365 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.082546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040299 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784204 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3060 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6878 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997391 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18931296 # Number of tag accesses -system.l2c.tags.data_accesses 18931296 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32363 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 504085 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 191784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 466764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 195789 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435474 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608464 # number of Writeback hits -system.l2c.Writeback_hits::total 608464 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 26 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55192 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113050 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32363 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 504085 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 249642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 466764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 250981 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548524 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32363 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6829 # number of overall hits -system.l2c.overall_hits::cpu0.inst 504085 # number of overall hits -system.l2c.overall_hits::cpu0.data 249642 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30935 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6925 # number of overall hits -system.l2c.overall_hits::cpu1.inst 466764 # number of overall hits -system.l2c.overall_hits::cpu1.data 250981 # number of overall hits -system.l2c.overall_hits::total 1548524 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 35 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18903981 # Number of tag accesses +system.l2c.tags.data_accesses 18903981 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 27725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7459 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 477090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 174144 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 29829 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8048 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 498641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 211687 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434623 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 606690 # number of Writeback hits +system.l2c.Writeback_hits::total 606690 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55364 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112762 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 27725 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7459 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 477090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229508 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 427109500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3690889818 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 625000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294835000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5054676898 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9469369716 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6117750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83698669250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83244575500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7714617000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9329751845 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17044368845 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6117750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91413286250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92574327345 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183993731345 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020750 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015526 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991618 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989779 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.504178 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.572862 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091527 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -797,48 +776,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58447524 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676676 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676675 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608464 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2946 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2964 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246266 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246266 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967872 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5798454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7953186 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62935104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85607366 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 55020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 253376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148850866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148850866 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 204184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4964883974 # Layer occupancy (ticks) +system.toL2Bus.throughput 58696725 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148879474 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4433375902 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4485758372 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24044394 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86236537 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48427259 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322165 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322165 # Transaction distribution -system.iobus.trans_dist::WriteReq 8177 # Transaction distribution -system.iobus.trans_dist::WriteResp 8177 # Transaction distribution +system.iobus.throughput 48628247 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::WriteReq 8176 # Transaction distribution +system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7932 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -858,14 +837,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383052 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -885,18 +864,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390470 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500998 # Total data (bytes) +system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123501006 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3971000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -938,19 +917,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374875000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38148865049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7661485 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6126508 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 381527 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4905065 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3983490 # Number of BTB hits +system.cpu0.branchPred.lookups 7765284 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.211768 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 723596 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38982 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -974,25 +953,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25785436 # DTB read hits -system.cpu0.dtb.read_misses 39736 # DTB read misses -system.cpu0.dtb.write_hits 6191742 # DTB write hits -system.cpu0.dtb.write_misses 10170 # DTB write misses -system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 27181562 # DTB read hits +system.cpu0.dtb.read_misses 37782 # DTB read misses +system.cpu0.dtb.write_hits 5596065 # DTB write hits +system.cpu0.dtb.write_misses 10098 # DTB write misses +system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5474 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1453 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 628 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25825172 # DTB read accesses -system.cpu0.dtb.write_accesses 6201912 # DTB write accesses +system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 27219344 # DTB read accesses +system.cpu0.dtb.write_accesses 5606163 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31977178 # DTB hits -system.cpu0.dtb.misses 49906 # DTB misses -system.cpu0.dtb.accesses 32027084 # DTB accesses +system.cpu0.dtb.hits 32777627 # DTB hits +system.cpu0.dtb.misses 47880 # DTB misses +system.cpu0.dtb.accesses 32825507 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1014,696 +993,712 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5958651 # ITB inst hits -system.cpu0.itb.inst_misses 7224 # ITB inst misses +system.cpu0.itb.inst_hits 5349242 # ITB inst hits +system.cpu0.itb.inst_misses 7594 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2573 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5965875 # ITB inst accesses -system.cpu0.itb.hits 5958651 # DTB hits -system.cpu0.itb.misses 7224 # DTB misses -system.cpu0.itb.accesses 5965875 # DTB accesses -system.cpu0.numCycles 242096947 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses +system.cpu0.itb.hits 5349242 # DTB hits +system.cpu0.itb.misses 7594 # DTB misses +system.cpu0.itb.accesses 5356836 # DTB accesses +system.cpu0.numCycles 234138431 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15548527 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 46430150 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7661485 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4707086 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10443980 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2504010 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 87505 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47991707 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1669 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1947 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50069 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1492171 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5956718 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 371320 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2975 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.753757 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.110815 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66925381 86.51% 86.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685980 0.89% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 883677 1.14% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1195178 1.54% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1096516 1.42% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 566437 0.73% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1314357 1.70% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 386846 0.50% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4307624 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77361996 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031646 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.191783 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16313273 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49370536 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9491475 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 529288 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1655237 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1021533 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91523 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55531280 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303986 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1655237 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17162522 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7654348 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 28580121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9244360 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 13063308 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52889125 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1160 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 8605902 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9933616 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1829408 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 705 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54696180 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 245103090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 223663577 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5274 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39761499 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14934681 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 590339 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 538925 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5812671 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10214201 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7053988 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1084092 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1355038 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49147671 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1004891 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62507144 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 106564 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10354652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26208427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256708 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77361996 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.807983 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.536259 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55228815 71.39% 71.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6921867 8.95% 80.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3371546 4.36% 84.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2828196 3.66% 88.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6343832 8.20% 96.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1429149 1.85% 98.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 903697 1.17% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 264810 0.34% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 70084 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77361996 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 34065 0.76% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4230863 93.99% 94.75% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 236461 5.25% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14977 0.02% 0.02% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29471794 47.15% 47.17% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48326 0.08% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1252 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26467836 42.34% 89.60% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6502932 10.40% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62507144 # Type of FU issued -system.cpu0.iq.rate 0.258191 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4501391 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.072014 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207022163 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60516960 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43741315 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11807 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6284 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5315 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66987291 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6267 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 331575 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued +system.cpu0.iq.rate 0.252050 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2258680 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16640 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 890724 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17025951 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348422 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1655237 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6199849 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 752551 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50264845 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 98291 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10214201 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7053988 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 705061 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 147463 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 536075 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16640 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186895 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147787 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 334682 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61435794 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26133192 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1071350 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 112283 # number of nop insts executed -system.cpu0.iew.exec_refs 32576038 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6024055 # Number of branches executed -system.cpu0.iew.exec_stores 6442846 # Number of stores executed -system.cpu0.iew.exec_rate 0.253765 # Inst execution rate -system.cpu0.iew.wb_sent 60932314 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43746630 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24175990 # num instructions producing a value -system.cpu0.iew.wb_consumers 44857309 # num instructions consuming a value +system.cpu0.iew.exec_nop 111268 # number of nop insts executed +system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5668977 # Number of branches executed +system.cpu0.iew.exec_stores 5863010 # Number of stores executed +system.cpu0.iew.exec_rate 0.250297 # Inst execution rate +system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21645924 # num instructions producing a value +system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.180699 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.538953 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10244306 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 748183 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 291383 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75706759 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.522606 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.501619 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61320530 81.00% 81.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7333121 9.69% 90.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1910409 2.52% 93.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1174950 1.55% 94.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 814971 1.08% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569506 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 771340 1.02% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 344904 0.46% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1467028 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75706759 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30422123 # Number of instructions committed -system.cpu0.commit.committedOps 39564795 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29059194 # Number of instructions committed +system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14118785 # Number of memory references committed -system.cpu0.commit.loads 7955521 # Number of loads committed -system.cpu0.commit.membars 210845 # Number of memory barriers committed -system.cpu0.commit.branches 5215430 # Number of branches committed -system.cpu0.commit.fp_insts 5270 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35234514 # Number of committed integer instructions. -system.cpu0.commit.function_calls 505825 # Number of function calls committed. +system.cpu0.commit.refs 12086481 # Number of memory references committed +system.cpu0.commit.loads 6517661 # Number of loads committed +system.cpu0.commit.membars 192728 # Number of memory barriers committed +system.cpu0.commit.branches 4958536 # Number of branches committed +system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions. +system.cpu0.commit.function_calls 472350 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25399613 64.20% 64.20% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45146 0.11% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 1251 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.31% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7955521 20.11% 84.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 6163264 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 39564795 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1467028 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1507447 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123090455 # The number of ROB reads -system.cpu0.rob.rob_writes 101316686 # The number of ROB writes -system.cpu0.timesIdled 905863 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 164734951 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248240039 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30347856 # Number of Instructions Simulated -system.cpu0.committedOps 39490528 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 7.977399 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.977399 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.125354 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.125354 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279159718 # number of integer regfile reads -system.cpu0.int_regfile_writes 44499662 # number of integer regfile writes -system.cpu0.fp_regfile_reads 45106 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42408 # number of floating regfile writes -system.cpu0.misc_regfile_reads 136236681 # number of misc regfile reads -system.cpu0.misc_regfile_writes 579467 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983848 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.584983 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10572279 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984360 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.740257 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6906897250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 320.103204 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.481778 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.625202 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.373988 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 270795640 # The number of ROB reads +system.cpu0.rob.rob_writes 85052492 # The number of ROB writes +system.cpu0.timesIdled 264396 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1761356 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2270391996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 28992496 # Number of Instructions Simulated +system.cpu0.committedOps 34782112 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 8.075829 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.075829 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123826 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123826 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66468797 # number of integer regfile reads +system.cpu0.int_regfile_writes 24185826 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44758 # number of floating regfile reads +system.cpu0.fp_regfile_writes 41844 # number of floating regfile writes +system.cpu0.cc_regfile_reads 196782773 # number of cc regfile reads +system.cpu0.cc_regfile_writes 15711716 # number of cc regfile writes +system.cpu0.misc_regfile_reads 291428250 # number of misc regfile reads +system.cpu0.misc_regfile_writes 565781 # number of misc regfile writes +system.cpu0.icache.tags.replacements 988317 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.592753 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089596 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089596 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 644041 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993361 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21521749 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644553 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.390193 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 42479250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 255.642215 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 256.351146 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.499301 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.500686 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 641884 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19756750 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 642396 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.754784 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.972457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.020960 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.261665 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.738322 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101726761 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101726761 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7076892 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6698233 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13775125 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3751457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3500966 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7252423 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 118146 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 125300 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243446 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 120516 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 127110 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247626 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10828349 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10199199 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21027548 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10828349 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10199199 # number of overall hits -system.cpu0.dcache.overall_hits::total 21027548 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 365609 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 402058 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 767667 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1663469 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1307220 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2970689 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7411 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6147 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13558 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 9 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # 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number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 106232248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 81884247 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 188116495 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 129501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 129501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 259002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89857275282 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 61994690587 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 151851965869 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89857275282 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 61994690587 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 151851965869 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7442501 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7100291 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14542792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5414926 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4808186 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223112 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125557 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 131447 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257004 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 120525 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 127119 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247644 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12857427 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11908477 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24765904 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12857427 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 11908477 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24765904 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.049124 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.056626 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.052787 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.307201 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.271874 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.290586 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059025 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.046764 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052754 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000075 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000071 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000073 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.157814 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.143535 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.150948 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.157814 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.143535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.150948 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15787.195712 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14669.479242 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15201.802763 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50548.182410 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42912.982591 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47188.394190 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14334.401295 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13321.009761 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13874.944313 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14389 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 14389 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14389 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40619.985328 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44284.781207 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36269.518818 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 40619.985328 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 36311 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 24635 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3444 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 311 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.543264 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 79.212219 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 95317436 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 95317436 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5857300 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6196947 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 12054247 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3502178 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3641154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7143332 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35246 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29793 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 65039 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110182 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133190 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243372 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112371 # 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number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1725190273 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2222171472 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3947361745 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4787330436 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6538944348 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11326274784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 807768256 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 644366504 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1452134760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73471759 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72597010 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146068769 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6512520709 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8761115820 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15273636529 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7320288965 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9405482324 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16725771289 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91407551750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90929310002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11972132389 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14721058995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693191384 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021369 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026985 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024274 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023230 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394263 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.379732 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.387919 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044389 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022191 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026253 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025837 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028734 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027343 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1714,15 +1709,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7344792 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5924572 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342317 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4758265 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3794052 # Number of BTB hits +system.cpu1.branchPred.lookups 8288231 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.736038 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 685317 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35371 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1746,25 +1741,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25350014 # DTB read hits -system.cpu1.dtb.read_misses 36246 # DTB read misses -system.cpu1.dtb.write_hits 5533315 # DTB write hits -system.cpu1.dtb.write_misses 8540 # DTB write misses -system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 28293531 # DTB read hits +system.cpu1.dtb.read_misses 40544 # DTB read misses +system.cpu1.dtb.write_hits 6190636 # DTB write hits +system.cpu1.dtb.write_misses 14491 # DTB write misses +system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5471 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1908 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25386260 # DTB read accesses -system.cpu1.dtb.write_accesses 5541855 # DTB write accesses +system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 28334075 # DTB read accesses +system.cpu1.dtb.write_accesses 6205127 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 30883329 # DTB hits -system.cpu1.dtb.misses 44786 # DTB misses -system.cpu1.dtb.accesses 30928115 # DTB accesses +system.cpu1.dtb.hits 34484167 # DTB hits +system.cpu1.dtb.misses 55035 # DTB misses +system.cpu1.dtb.accesses 34539202 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1786,329 +1781,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5683844 # ITB inst hits -system.cpu1.itb.inst_misses 6848 # ITB inst misses +system.cpu1.itb.inst_hits 5693555 # ITB inst hits +system.cpu1.itb.inst_misses 8207 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2653 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1514 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5690692 # ITB inst accesses -system.cpu1.itb.hits 5683844 # DTB hits -system.cpu1.itb.misses 6848 # DTB misses -system.cpu1.itb.accesses 5690692 # DTB accesses -system.cpu1.numCycles 235812118 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses +system.cpu1.itb.hits 5693555 # DTB hits +system.cpu1.itb.misses 8207 # DTB misses +system.cpu1.itb.accesses 5701762 # DTB accesses +system.cpu1.numCycles 237058963 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14488159 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45028124 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7344792 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4479369 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9950354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2325910 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82893 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 46948697 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1099 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1893 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 45519 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1268155 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 161 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5681743 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 353393 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2950 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.748631 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.104884 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64461074 86.64% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 633258 0.85% 87.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 845202 1.14% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1118143 1.50% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1030578 1.39% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 551741 0.74% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1296054 1.74% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 370486 0.50% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4096442 5.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74402978 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.031147 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190949 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15290128 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48029788 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9010807 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 535995 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1534066 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 962796 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84486 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53087117 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 281620 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1534066 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16089413 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6996685 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 28422508 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8819964 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 12538212 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50579819 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 715 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 8590875 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 9852379 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1395671 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 1301 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 52976488 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 233969396 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 213834273 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5207 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38971918 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14004569 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 583497 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 540607 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 5363476 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9768473 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6353478 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 903299 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1144541 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47001226 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 985413 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60595640 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 98989 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9593116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24473464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 250944 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74402978 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814425 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.533021 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 52794785 70.96% 70.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6823804 9.17% 80.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3272663 4.40% 84.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2786608 3.75% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6272134 8.43% 96.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1319081 1.77% 98.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 820611 1.10% 99.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 247257 0.33% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 66035 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74402978 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29526 0.66% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4196905 94.38% 95.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 220217 4.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13541 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28679065 47.33% 47.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45344 0.07% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 858 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.43% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26009717 42.92% 90.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5847084 9.65% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60595640 # Type of FU issued -system.cpu1.iq.rate 0.256966 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4446652 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.073382 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200172970 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57588554 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41991709 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11520 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6240 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4992 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65022566 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6185 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 323560 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued +system.cpu1.iq.rate 0.264676 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2067890 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2468 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15600 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 783792 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16950409 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 331839 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1534066 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5578937 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 735039 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48101549 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 89840 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9768473 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6353478 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 710230 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 138266 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 531900 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15600 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 167974 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132221 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 300195 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59563474 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25690610 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1032166 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 114910 # number of nop insts executed -system.cpu1.iew.exec_refs 31485549 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5840798 # Number of branches executed -system.cpu1.iew.exec_stores 5794939 # Number of stores executed -system.cpu1.iew.exec_rate 0.252589 # Inst execution rate -system.cpu1.iew.wb_sent 59096440 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41996701 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23719594 # num instructions producing a value -system.cpu1.iew.wb_consumers 43668575 # num instructions consuming a value +system.cpu1.iew.exec_nop 133996 # number of nop insts executed +system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6064585 # Number of branches executed +system.cpu1.iew.exec_stores 6442500 # Number of stores executed +system.cpu1.iew.exec_rate 0.262884 # Inst execution rate +system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23329556 # num instructions producing a value +system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178094 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543173 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9469311 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 734469 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259123 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 72868911 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.524128 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.502288 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 58802570 80.70% 80.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7335717 10.07% 90.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1834357 2.52% 93.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1110131 1.52% 94.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 806352 1.11% 95.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 478738 0.66% 96.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 708592 0.97% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 352493 0.48% 98.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1439961 1.98% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 72868911 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30042313 # Number of instructions committed -system.cpu1.commit.committedOps 38192613 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31416794 # Number of instructions committed +system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13270269 # Number of memory references committed -system.cpu1.commit.loads 7700583 # Number of loads committed -system.cpu1.commit.membars 192827 # Number of memory barriers committed -system.cpu1.commit.branches 5091642 # Number of branches committed -system.cpu1.commit.fp_insts 4942 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33962282 # Number of committed integer instructions. -system.cpu1.commit.function_calls 485556 # Number of function calls committed. +system.cpu1.commit.refs 13164154 # Number of memory references committed +system.cpu1.commit.loads 6998485 # Number of loads committed +system.cpu1.commit.membars 211048 # Number of memory barriers committed +system.cpu1.commit.branches 5351716 # Number of branches committed +system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions. +system.cpu1.commit.function_calls 519749 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24878693 65.14% 65.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 42793 0.11% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 858 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.25% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 7700583 20.16% 85.42% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 5569686 14.58% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 38192613 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1439961 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 118199712 # The number of ROB reads -system.cpu1.rob.rob_writes 96901530 # The number of ROB writes -system.cpu1.timesIdled 866503 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 161409140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2317329341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29966199 # Number of Instructions Simulated -system.cpu1.committedOps 38116499 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.869270 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.869270 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.127077 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.127077 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 270334360 # number of integer regfile reads -system.cpu1.int_regfile_writes 43344614 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45048 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42280 # number of floating regfile writes -system.cpu1.misc_regfile_reads 130449609 # number of misc regfile reads -system.cpu1.misc_regfile_writes 594503 # number of misc regfile writes +system.cpu1.rob.rob_reads 276790751 # The number of ROB reads +system.cpu1.rob.rob_writes 91451122 # The number of ROB writes +system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31333111 # Number of Instructions Simulated +system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads +system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes +system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes +system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads +system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes +system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads +system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2125,17 +2120,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1734330533049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734330533049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1734330533049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83063 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index cce768d16..936db738a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.631271 # Number of seconds simulated -sim_ticks 2631271319500 # Number of ticks simulated -final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.626162 # Number of seconds simulated +sim_ticks 2626161554000 # Number of ticks simulated +final_tick 2626161554000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354699 # Simulator instruction rate (inst/s) -host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15499898557 # Simulator tick rate (ticks/s) -host_mem_usage 465856 # Number of bytes of host memory used -host_seconds 169.76 # Real time elapsed on the host -sim_insts 60213853 # Number of instructions simulated -sim_ops 76620850 # Number of ops (including micro ops) simulated +host_inst_rate 476066 # Simulator instruction rate (inst/s) +host_op_rate 568569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20761634862 # Simulator tick rate (ticks/s) +host_mem_usage 472496 # Number of bytes of host memory used +host_seconds 126.49 # Real time elapsed on the host +sim_insts 60218144 # Number of instructions simulated +sim_ops 71918894 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory @@ -27,134 +27,134 @@ system.realview.nvmem.bw_total::cpu0.inst 8 # T system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 306888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4490328 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 399040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4560448 # Number of bytes read from this memory +system.physmem.bytes_read::total 134013152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 306888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 399040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677952 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1536620 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1479452 # Number of bytes written to this memory +system.physmem.bytes_written::total 6694024 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11007 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 71257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690721 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 384155 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 369863 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811486 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47314780 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1709845 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 151948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1736545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51030049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116858 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 151948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268806 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1400505 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 585120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548976 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1400505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47314780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2294965 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690868 # Number of read requests accepted -system.physmem.writeReqs 811684 # Number of write requests accepted -system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 980391 # Per bank write bursts -system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980222 # Per bank write bursts -system.physmem.perBankRdBursts::3 980428 # Per bank write bursts -system.physmem.perBankRdBursts::4 986950 # Per bank write bursts -system.physmem.perBankRdBursts::5 980708 # Per bank write bursts -system.physmem.perBankRdBursts::6 980611 # Per bank write bursts -system.physmem.perBankRdBursts::7 980420 # Per bank write bursts -system.physmem.perBankRdBursts::8 980615 # Per bank write bursts -system.physmem.perBankRdBursts::9 980431 # Per bank write bursts -system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979544 # Per bank write bursts -system.physmem.perBankRdBursts::12 980153 # Per bank write bursts -system.physmem.perBankRdBursts::13 980076 # Per bank write bursts -system.physmem.perBankRdBursts::14 980177 # Per bank write bursts -system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6626 # Per bank write bursts -system.physmem.perBankWrBursts::1 6496 # Per bank write bursts -system.physmem.perBankWrBursts::2 6497 # Per bank write bursts -system.physmem.perBankWrBursts::3 6558 # Per bank write bursts -system.physmem.perBankWrBursts::4 6634 # Per bank write bursts -system.physmem.perBankWrBursts::5 6937 # Per bank write bursts -system.physmem.perBankWrBursts::6 6920 # Per bank write bursts -system.physmem.perBankWrBursts::7 6772 # Per bank write bursts -system.physmem.perBankWrBursts::8 6893 # Per bank write bursts -system.physmem.perBankWrBursts::9 6718 # Per bank write bursts -system.physmem.perBankWrBursts::10 6212 # Per bank write bursts -system.physmem.perBankWrBursts::11 6014 # Per bank write bursts -system.physmem.perBankWrBursts::12 6499 # Per bank write bursts -system.physmem.perBankWrBursts::13 6274 # Per bank write bursts -system.physmem.perBankWrBursts::14 6516 # Per bank write bursts -system.physmem.perBankWrBursts::15 6506 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 151948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2299897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53579025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690721 # Number of read requests accepted +system.physmem.writeReqs 811486 # Number of write requests accepted +system.physmem.readBursts 15690721 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811486 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004205504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 6711360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134013152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6694024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706602 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4522 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 980414 # Per bank write bursts +system.physmem.perBankRdBursts::1 980046 # Per bank write bursts +system.physmem.perBankRdBursts::2 979991 # Per bank write bursts +system.physmem.perBankRdBursts::3 980262 # Per bank write bursts +system.physmem.perBankRdBursts::4 986671 # Per bank write bursts +system.physmem.perBankRdBursts::5 980424 # Per bank write bursts +system.physmem.perBankRdBursts::6 980568 # Per bank write bursts +system.physmem.perBankRdBursts::7 980428 # Per bank write bursts +system.physmem.perBankRdBursts::8 980784 # Per bank write bursts +system.physmem.perBankRdBursts::9 980432 # Per bank write bursts +system.physmem.perBankRdBursts::10 979731 # Per bank write bursts +system.physmem.perBankRdBursts::11 979594 # Per bank write bursts +system.physmem.perBankRdBursts::12 980346 # Per bank write bursts +system.physmem.perBankRdBursts::13 980257 # Per bank write bursts +system.physmem.perBankRdBursts::14 980396 # Per bank write bursts +system.physmem.perBankRdBursts::15 980367 # Per bank write bursts +system.physmem.perBankWrBursts::0 6649 # Per bank write bursts +system.physmem.perBankWrBursts::1 6328 # Per bank write bursts +system.physmem.perBankWrBursts::2 6318 # Per bank write bursts +system.physmem.perBankWrBursts::3 6427 # Per bank write bursts +system.physmem.perBankWrBursts::4 6389 # Per bank write bursts +system.physmem.perBankWrBursts::5 6673 # Per bank write bursts +system.physmem.perBankWrBursts::6 6856 # Per bank write bursts +system.physmem.perBankWrBursts::7 6766 # Per bank write bursts +system.physmem.perBankWrBursts::8 7040 # Per bank write bursts +system.physmem.perBankWrBursts::9 6684 # Per bank write bursts +system.physmem.perBankWrBursts::10 6144 # Per bank write bursts +system.physmem.perBankWrBursts::11 6041 # Per bank write bursts +system.physmem.perBankWrBursts::12 6664 # Per bank write bursts +system.physmem.perBankWrBursts::13 6480 # Per bank write bursts +system.physmem.perBankWrBursts::14 6708 # Per bank write bursts +system.physmem.perBankWrBursts::15 6698 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2631266900000 # Total gap between requests +system.physmem.totGap 2626157242500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6664 # Read request sizes (log2) -system.physmem.readPktSize::3 15532032 # Read request sizes (log2) +system.physmem.readPktSize::2 6644 # Read request sizes (log2) +system.physmem.readPktSize::3 15532042 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152172 # Read request sizes (log2) +system.physmem.readPktSize::6 152035 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57666 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57468 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1099516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1065450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2766854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2672571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3490866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 121692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 109210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -169,39 +169,39 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 317 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5638 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -233,350 +233,349 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.796235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.926694 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.945376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22813 2.19% 2.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22914 2.20% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8969 0.86% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2415 0.23% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2270 0.22% 5.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1819 0.17% 5.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9086 0.87% 6.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 877 0.08% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969093 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040256 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5997 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2616.425880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 48628.845120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5973 99.60% 99.60% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 7 0.12% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 4 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads -system.physmem.totQLat 402822623250 # Total ticks spent queuing -system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5997 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.486243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.330739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.155795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 3 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 3 0.05% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 4 0.07% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 5 0.08% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 8 0.13% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 4 0.07% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2055 34.27% 35.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.50% 35.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3613 60.25% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 37 0.62% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 21 0.35% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.27% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.23% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.30% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.22% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 29 0.48% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 18 0.30% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.25% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.15% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 11 0.18% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 15 0.25% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.27% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.18% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5997 # Writes before turning the bus around for reads +system.physmem.totQLat 404022182250 # Total ticks spent queuing +system.physmem.totMemAccLat 698223013500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78453555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25749.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44499.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.00 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.01 # Data bus utilization in percentage +system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing -system.physmem.readRowHits 14667283 # Number of row buffer hits during reads -system.physmem.writeRowHits 88101 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14667428 # Number of row buffer hits during reads +system.physmem.writeRowHits 87892 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes -system.physmem.avgGap 159446.06 # Average gap between requests +system.physmem.writeRowHitRate 83.80 # Row buffer hit rate for writes +system.physmem.avgGap 159139.76 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states -system.physmem.memoryStateTime::REF 87863880000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2253794386750 # Time in different power states +system.physmem.memoryStateTime::REF 87693060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states +system.physmem.memoryStateTime::ACT 284666999500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54394584 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743630 # Transaction distribution -system.membus.trans_dist::ReadResp 16743630 # Transaction distribution +system.membus.throughput 54492260 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743274 # Transaction distribution +system.membus.trans_dist::ReadResp 16743274 # Transaction distribution system.membus.trans_dist::WriteReq 763389 # Transaction distribution system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57666 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131349 # Transaction distribution -system.membus.trans_dist::ReadExResp 131349 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57468 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution +system.membus.trans_dist::ReadExReq 131560 # Transaction distribution +system.membus.trans_dist::ReadExResp 131560 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383096 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4278894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35342958 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390558 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16450920 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18849222 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143126910 # Total data (bytes) +system.membus.tot_pkt_size::total 143105478 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143105478 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225841000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3816000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171677500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4988493167 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38432312250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62060 # number of replacements -system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use -system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy +system.l2c.tags.replacements 61927 # number of replacements +system.l2c.tags.tagsinuse 50918.981702 # Cycle average of tags in use +system.l2c.tags.total_refs 1698761 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127310 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.343500 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574018004500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37920.667518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2858.981429 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3190.441154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4136.744409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2812.146305 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.578623 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043625 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048682 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17278044 # Number of tag accesses -system.l2c.tags.data_accesses 17278044 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits -system.l2c.Writeback_hits::total 596476 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.063122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042910 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.776962 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2167 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6500 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56664 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17277278 # Number of tag accesses +system.l2c.tags.data_accesses 17277278 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9702 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 462087 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 188003 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9966 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3602 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 382555 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 182697 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242114 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596521 # number of Writeback hits +system.l2c.Writeback_hits::total 596521 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56762 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114533 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3664 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 418356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 245103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9807 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 426125 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 239886 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356617 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10108 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3664 # number of overall hits -system.l2c.overall_hits::cpu0.inst 418356 # number of overall hits -system.l2c.overall_hits::cpu0.data 245103 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9807 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits -system.l2c.overall_hits::cpu1.inst 426125 # number of overall hits -system.l2c.overall_hits::cpu1.data 239886 # number of overall hits -system.l2c.overall_hits::total 1356617 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 60509 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114489 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9702 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3502 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 462087 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 248512 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9966 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3602 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 382555 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 236677 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356603 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9702 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3502 # number of overall hits +system.l2c.overall_hits::cpu0.inst 462087 # number of overall hits +system.l2c.overall_hits::cpu0.data 248512 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9966 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3602 # number of overall hits +system.l2c.overall_hits::cpu1.inst 382555 # number of overall hits +system.l2c.overall_hits::cpu1.data 236677 # number of overall hits +system.l2c.overall_hits::total 1356603 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4266 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5262 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4381 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5534 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6325 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4967 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20823 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1468 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1421 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2889 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 66168 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 66809 # 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Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596521 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2903 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2903 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247694 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247694 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49988 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549283 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54763036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83799850 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 78676 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138669986 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138669986 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170112 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808749000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3866196743 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420580083 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12904000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30319250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48131413 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution +system.iobus.throughput 48225066 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715396 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715396 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7948 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) @@ -784,14 +783,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447156 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447160 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15896 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) @@ -811,18 +810,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390550 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390558 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646806 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646806 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646814 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3979000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -864,9 +863,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374912000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39164946750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -891,25 +890,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7447963 # DTB read hits -system.cpu0.dtb.read_misses 7119 # DTB read misses -system.cpu0.dtb.write_hits 5549645 # DTB write hits -system.cpu0.dtb.write_misses 1815 # DTB write misses -system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6652404 # DTB read hits +system.cpu0.dtb.read_misses 6867 # DTB read misses +system.cpu0.dtb.write_hits 5702862 # DTB write hits +system.cpu0.dtb.write_misses 1758 # DTB write misses +system.cpu0.dtb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6327 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 129 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7455082 # DTB read accesses -system.cpu0.dtb.write_accesses 5551460 # DTB write accesses +system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6659271 # DTB read accesses +system.cpu0.dtb.write_accesses 5704620 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12997608 # DTB hits -system.cpu0.dtb.misses 8934 # DTB misses -system.cpu0.dtb.accesses 13006542 # DTB accesses +system.cpu0.dtb.hits 12355266 # DTB hits +system.cpu0.dtb.misses 8625 # DTB misses +system.cpu0.dtb.accesses 12363891 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -931,160 +930,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30500446 # ITB inst hits -system.cpu0.itb.inst_misses 3756 # ITB inst misses +system.cpu0.itb.inst_hits 30639417 # ITB inst hits +system.cpu0.itb.inst_misses 3605 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2770 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses -system.cpu0.itb.hits 30500446 # DTB hits -system.cpu0.itb.misses 3756 # DTB misses -system.cpu0.itb.accesses 30504202 # DTB accesses -system.cpu0.numCycles 2629256644 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30643022 # ITB inst accesses +system.cpu0.itb.hits 30639417 # DTB hits +system.cpu0.itb.misses 3605 # DTB misses +system.cpu0.itb.accesses 30643022 # DTB accesses +system.cpu0.numCycles 2625139831 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29876886 # Number of instructions committed -system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses -system.cpu0.num_func_calls 1058651 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34283991 # number of integer instructions -system.cpu0.num_fp_insts 4842 # number of float instructions -system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written -system.cpu0.num_mem_refs 13572889 # number of memory refs -system.cpu0.num_load_insts 7771976 # Number of load instructions -system.cpu0.num_store_insts 5800913 # Number of store instructions -system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles -system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles -system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles -system.cpu0.Branches 5129174 # Number of branches fetched -system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction -system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction -system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction -system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30062808 # Number of instructions committed +system.cpu0.committedOps 36081752 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32258130 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5851 # Number of float alu accesses +system.cpu0.num_func_calls 1105626 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3807715 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32258130 # number of integer instructions +system.cpu0.num_fp_insts 5851 # number of float instructions +system.cpu0.num_int_register_reads 58404320 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21560333 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4184 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1670 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 129650201 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14353458 # number of times the CC registers were written +system.cpu0.num_mem_refs 12793226 # number of memory refs +system.cpu0.num_load_insts 6826552 # Number of load instructions +system.cpu0.num_store_insts 5966674 # Number of store instructions +system.cpu0.num_idle_cycles 2291568668.895058 # Number of idle cycles +system.cpu0.num_busy_cycles 333571162.104942 # Number of busy cycles +system.cpu0.not_idle_fraction 0.127068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.872932 # Percentage of idle cycles +system.cpu0.Branches 5192489 # Number of branches fetched +system.cpu0.op_class::No_OpClass 12678 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23764768 64.90% 64.94% # Class of executed instruction +system.cpu0.op_class::IntMult 45316 0.12% 65.06% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1041 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.06% # Class of executed instruction +system.cpu0.op_class::MemRead 6826552 18.64% 83.71% # Class of executed instruction +system.cpu0.op_class::MemWrite 5966674 16.29% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # 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mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.713464 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627683 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.876343 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23661001 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628195 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.665058 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 147.481748 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 364.394596 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.288050 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.711708 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 627738 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.876206 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21798920 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628250 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.697843 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 154.066297 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 357.809909 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.300911 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.698847 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97784979 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97784979 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6545596 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6653610 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199206 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4917377 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 5057557 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9974934 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119123 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236189 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125242 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 122515 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247757 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11462973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11711167 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23174140 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11462973 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11711167 # number of overall hits -system.cpu0.dcache.overall_hits::total 23174140 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 186473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 182643 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369116 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 125422 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 125003 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250425 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6121 # 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number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5645844221 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11263797767 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82277250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 78257750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 160535000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8389012796 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 8350903971 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 16739916767 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8389012796 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 8350903971 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 16739916767 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6732069 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6836253 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13568322 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5042799 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5182560 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225359 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125244 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 122514 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247758 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125242 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 122515 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247757 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11774868 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12018813 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23793681 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11774868 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12018813 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23793681 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027699 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026717 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.027204 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024872 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024120 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024491 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048873 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044468 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046695 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026488 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025597 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026488 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025597 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14860.377910 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14810.640156 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14835.767076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44792.409195 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45165.669792 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44978.727232 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.798726 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14364.491557 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13876.307373 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27019.869173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26896.913371 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27144.523156 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 27019.869173 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 90464778 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90464778 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5681092 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5575113 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11256205 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23483.308575 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24362.852542 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23916.361202 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136496250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7075388507 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144952721 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14220341228 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7731762757 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7718135721 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15449898478 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91728534250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90349964750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078499000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13171576426 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13067690513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239266939 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104900110676 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103417655263 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317765939 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025375 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025794 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024550 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024456 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.406743 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.390555 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.399021 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049277 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.042769 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046179 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024987 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025076 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028298 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028130 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028215 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.780758 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.501016 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11781.331736 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41641.786823 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44102.655907 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42851.663140 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16736.129172 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16684.607324 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16712.071684 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.800906 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12626.858276 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11927.319993 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25699.621544 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26382.175652 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26038.095324 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24581.956433 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.520386 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24930.892529 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1364,25 +1401,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7552227 # DTB read hits -system.cpu1.dtb.read_misses 6971 # DTB read misses -system.cpu1.dtb.write_hits 5683121 # DTB write hits -system.cpu1.dtb.write_misses 1859 # DTB write misses -system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6516178 # DTB read hits +system.cpu1.dtb.read_misses 7066 # DTB read misses +system.cpu1.dtb.write_hits 5531450 # DTB write hits +system.cpu1.dtb.write_misses 1844 # DTB write misses +system.cpu1.dtb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6501 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7559198 # DTB read accesses -system.cpu1.dtb.write_accesses 5684980 # DTB write accesses +system.cpu1.dtb.perms_faults 238 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6523244 # DTB read accesses +system.cpu1.dtb.write_accesses 5533294 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13235348 # DTB hits -system.cpu1.dtb.misses 8830 # DTB misses -system.cpu1.dtb.accesses 13244178 # DTB accesses +system.cpu1.dtb.hits 12047628 # DTB hits +system.cpu1.dtb.misses 8910 # DTB misses +system.cpu1.dtb.accesses 12056538 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1404,85 +1441,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31007524 # ITB inst hits -system.cpu1.itb.inst_misses 3606 # ITB inst misses +system.cpu1.itb.inst_hits 30872911 # ITB inst hits +system.cpu1.itb.inst_misses 3673 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2489 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2794 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses -system.cpu1.itb.hits 31007524 # DTB hits -system.cpu1.itb.misses 3606 # DTB misses -system.cpu1.itb.accesses 31011130 # DTB accesses -system.cpu1.numCycles 2633285995 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30876584 # ITB inst accesses +system.cpu1.itb.hits 30872911 # DTB hits +system.cpu1.itb.misses 3673 # DTB misses +system.cpu1.itb.accesses 30876584 # DTB accesses +system.cpu1.numCycles 2627183277 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30336967 # Number of instructions committed -system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses -system.cpu1.num_func_calls 1081754 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34937438 # number of integer instructions -system.cpu1.num_fp_insts 5427 # number of float instructions -system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written -system.cpu1.num_mem_refs 13827657 # number of memory refs -system.cpu1.num_load_insts 7892397 # Number of load instructions -system.cpu1.num_store_insts 5935260 # Number of store instructions -system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles -system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles -system.cpu1.Branches 5180924 # Number of branches fetched -system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction -system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction +system.cpu1.committedInsts 30155336 # Number of instructions committed +system.cpu1.committedOps 35837142 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32021976 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4418 # Number of float alu accesses +system.cpu1.num_func_calls 1035067 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3744201 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32021976 # number of integer instructions +system.cpu1.num_fp_insts 4418 # number of float instructions +system.cpu1.num_int_register_reads 57765753 # number of times the integer registers were read +system.cpu1.num_int_register_writes 21325005 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3309 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1110 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 128250854 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14653287 # number of times the CC registers were written +system.cpu1.num_mem_refs 12466012 # number of memory refs +system.cpu1.num_load_insts 6694911 # Number of load instructions +system.cpu1.num_store_insts 5771101 # Number of store instructions +system.cpu1.num_idle_cycles 2287259017.662607 # Number of idle cycles +system.cpu1.num_busy_cycles 339924259.337393 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129387 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870613 # Percentage of idle cycles +system.cpu1.Branches 5118153 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15840 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 23832212 65.55% 65.59% # Class of executed instruction +system.cpu1.op_class::IntMult 42672 0.12% 65.71% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1070 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.71% # Class of executed instruction +system.cpu1.op_class::MemRead 6694911 18.41% 84.13% # Class of executed instruction +system.cpu1.op_class::MemWrite 5771101 15.87% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 39299664 # Class of executed instruction +system.cpu1.op_class::total 36357806 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1501,10 +1540,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1781125703750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index aa05e00b0..bca94218b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,136 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137926 # Number of seconds simulated -sim_ticks 5137926173000 # Number of ticks simulated -final_tick 5137926173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.129874 # Number of seconds simulated +sim_ticks 5129873616500 # Number of ticks simulated +final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165389 # Simulator instruction rate (inst/s) -host_op_rate 326926 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2083966500 # Simulator tick rate (ticks/s) -host_mem_usage 742788 # Number of bytes of host memory used -host_seconds 2465.46 # Real time elapsed on the host -sim_insts 407759509 # Number of instructions simulated -sim_ops 806020953 # Number of ops (including micro ops) simulated +host_inst_rate 122712 # Simulator instruction rate (inst/s) +host_op_rate 242564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1543734215 # Simulator tick rate (ticks/s) +host_mem_usage 750608 # Number of bytes of host memory used +host_seconds 3323.03 # Real time elapsed on the host +sim_insts 407773893 # Number of instructions simulated +sim_ops 806048632 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2427584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10808512 # Number of bytes read from this memory -system.physmem.bytes_read::total 14275968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9555328 # Number of bytes written to this memory -system.physmem.bytes_written::total 9555328 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory +system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory +system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168883 # Number of read requests responded to by this memory -system.physmem.num_reads::total 223062 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149302 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149302 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 472483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 735 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory +system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2103672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2778547 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1859764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1859764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1859764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 472483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2103672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4638310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 223062 # Number of read requests accepted -system.physmem.writeReqs 149302 # Number of write requests accepted -system.physmem.readBursts 223062 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149302 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14267968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 9553728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14275968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9555328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185938 # Number of read requests accepted +system.physmem.writeReqs 149859 # Number of write requests accepted +system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1775 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 14642 # Per bank write bursts -system.physmem.perBankRdBursts::1 13963 # Per bank write bursts -system.physmem.perBankRdBursts::2 14587 # Per bank write bursts -system.physmem.perBankRdBursts::3 13341 # Per bank write bursts -system.physmem.perBankRdBursts::4 14143 # Per bank write bursts -system.physmem.perBankRdBursts::5 13526 # Per bank write bursts -system.physmem.perBankRdBursts::6 13007 # Per bank write bursts -system.physmem.perBankRdBursts::7 13123 # Per bank write bursts -system.physmem.perBankRdBursts::8 13660 # Per bank write bursts -system.physmem.perBankRdBursts::9 13743 # Per bank write bursts -system.physmem.perBankRdBursts::10 13657 # Per bank write bursts -system.physmem.perBankRdBursts::11 13667 # Per bank write bursts -system.physmem.perBankRdBursts::12 14668 # Per bank write bursts -system.physmem.perBankRdBursts::13 14755 # Per bank write bursts -system.physmem.perBankRdBursts::14 14289 # Per bank write bursts -system.physmem.perBankRdBursts::15 14166 # Per bank write bursts -system.physmem.perBankWrBursts::0 10056 # Per bank write bursts -system.physmem.perBankWrBursts::1 9321 # Per bank write bursts -system.physmem.perBankWrBursts::2 9829 # Per bank write bursts -system.physmem.perBankWrBursts::3 8830 # Per bank write bursts -system.physmem.perBankWrBursts::4 9558 # Per bank write bursts -system.physmem.perBankWrBursts::5 8986 # Per bank write bursts -system.physmem.perBankWrBursts::6 8593 # Per bank write bursts -system.physmem.perBankWrBursts::7 8747 # Per bank write bursts -system.physmem.perBankWrBursts::8 8969 # Per bank write bursts -system.physmem.perBankWrBursts::9 9193 # Per bank write bursts -system.physmem.perBankWrBursts::10 9160 # Per bank write bursts -system.physmem.perBankWrBursts::11 9087 # Per bank write bursts -system.physmem.perBankWrBursts::12 9894 # Per bank write bursts -system.physmem.perBankWrBursts::13 9881 # Per bank write bursts -system.physmem.perBankWrBursts::14 9649 # Per bank write bursts -system.physmem.perBankWrBursts::15 9524 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11383 # Per bank write bursts +system.physmem.perBankRdBursts::1 10659 # Per bank write bursts +system.physmem.perBankRdBursts::2 11850 # Per bank write bursts +system.physmem.perBankRdBursts::3 11657 # Per bank write bursts +system.physmem.perBankRdBursts::4 11883 # Per bank write bursts +system.physmem.perBankRdBursts::5 11508 # Per bank write bursts +system.physmem.perBankRdBursts::6 11028 # Per bank write bursts +system.physmem.perBankRdBursts::7 11462 # Per bank write bursts +system.physmem.perBankRdBursts::8 11217 # Per bank write bursts +system.physmem.perBankRdBursts::9 11477 # Per bank write bursts +system.physmem.perBankRdBursts::10 11649 # Per bank write bursts +system.physmem.perBankRdBursts::11 12129 # Per bank write bursts +system.physmem.perBankRdBursts::12 11737 # Per bank write bursts +system.physmem.perBankRdBursts::13 12518 # Per bank write bursts +system.physmem.perBankRdBursts::14 12268 # Per bank write bursts +system.physmem.perBankRdBursts::15 11218 # Per bank write bursts +system.physmem.perBankWrBursts::0 10090 # Per bank write bursts +system.physmem.perBankWrBursts::1 9375 # Per bank write bursts +system.physmem.perBankWrBursts::2 9103 # Per bank write bursts +system.physmem.perBankWrBursts::3 8918 # Per bank write bursts +system.physmem.perBankWrBursts::4 9314 # Per bank write bursts +system.physmem.perBankWrBursts::5 9243 # Per bank write bursts +system.physmem.perBankWrBursts::6 8603 # Per bank write bursts +system.physmem.perBankWrBursts::7 8925 # Per bank write bursts +system.physmem.perBankWrBursts::8 9240 # Per bank write bursts +system.physmem.perBankWrBursts::9 9268 # Per bank write bursts +system.physmem.perBankWrBursts::10 9747 # Per bank write bursts +system.physmem.perBankWrBursts::11 9397 # Per bank write bursts +system.physmem.perBankWrBursts::12 9475 # Per bank write bursts +system.physmem.perBankWrBursts::13 9702 # Per bank write bursts +system.physmem.perBankWrBursts::14 10013 # Per bank write bursts +system.physmem.perBankWrBursts::15 9419 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5137926057000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 5129873502000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 223062 # Read request sizes (log2) +system.physmem.readPktSize::6 185938 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149302 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 173856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149859 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -156,287 +159,277 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 9115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75897 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.867900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.633012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.529129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 29529 38.91% 38.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16915 22.29% 61.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7566 9.97% 71.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4259 5.61% 76.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2981 3.93% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2008 2.65% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1459 1.92% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1171 1.54% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10009 13.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75897 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.835320 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 526.600201 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 8306 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8307 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8307 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.970025 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.437156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.734930 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 6174 74.32% 74.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1334 16.06% 90.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 66 0.79% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 64 0.77% 91.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 51 0.61% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 45 0.54% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 113 1.36% 94.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 87 1.05% 95.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 56 0.67% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 56 0.67% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 34 0.41% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 52 0.63% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 60 0.72% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 31 0.37% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.12% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 10 0.12% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 28 0.34% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 7 0.08% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 4 0.05% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 3 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 5 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 4 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 2 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 2 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::78-79 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::90-91 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8307 # Writes before turning the bus around for reads -system.physmem.totQLat 4966355250 # Total ticks spent queuing -system.physmem.totMemAccLat 9146424000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1114685000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22276.94 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads +system.physmem.totQLat 1988147750 # Total ticks spent queuing +system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41026.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing -system.physmem.readRowHits 185691 # Number of row buffer hits during reads -system.physmem.writeRowHits 110625 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.09 # Row buffer hit rate for writes -system.physmem.avgGap 13798127.79 # Average gap between requests -system.physmem.pageHitRate 79.60 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4930575819000 # Time in different power states -system.physmem.memoryStateTime::REF 171566460000 # Time in different power states +system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing +system.physmem.readRowHits 152685 # Number of row buffer hits during reads +system.physmem.writeRowHits 110914 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes +system.physmem.avgGap 15276710.34 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states +system.physmem.memoryStateTime::REF 171297620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35783789000 # Time in different power states +system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5117506 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662560 # Transaction distribution -system.membus.trans_dist::ReadResp 662552 # Transaction distribution -system.membus.trans_dist::WriteReq 13764 # Transaction distribution -system.membus.trans_dist::WriteResp 13764 # Transaction distribution -system.membus.trans_dist::Writeback 149302 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2261 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1794 # Transaction distribution -system.membus.trans_dist::ReadExReq 180173 # Transaction distribution -system.membus.trans_dist::ReadExResp 180170 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723733 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1859247 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241801 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550149 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18417024 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20208974 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414272 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5414272 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25629818 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25629818 # Total data (bytes) -system.membus.snoop_data_through_bus 663552 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250523000 # Layer occupancy (ticks) +system.membus.throughput 4545861 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662568 # Transaction distribution +system.membus.trans_dist::ReadResp 662557 # Transaction distribution +system.membus.trans_dist::WriteReq 13776 # Transaction distribution +system.membus.trans_dist::WriteResp 13776 # Transaction distribution +system.membus.trans_dist::Writeback 103139 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution +system.membus.trans_dist::ReadExReq 133156 # Transaction distribution +system.membus.trans_dist::ReadExResp 133153 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution +system.membus.trans_dist::BadAddressError 11 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 23289549 # Total data (bytes) +system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583102000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1620731000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3164060842 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429649499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.116331 # Cycle average of tags in use +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992948576000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116331 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007271 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007271 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses -system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses -system.iocache.demand_misses::total 47630 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses -system.iocache.overall_misses::total 47630 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151620185 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 151620185 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 11039278588 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11039278588 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 11190898773 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11190898773 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 11190898773 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11190898773 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428706 # Number of tag accesses +system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses +system.iocache.ReadReq_misses::total 914 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses +system.iocache.demand_misses::total 914 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses +system.iocache.overall_misses::total 914 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles +system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166615.587912 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166615.587912 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 236285.928682 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 236285.928682 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 234954.834621 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 234954.834621 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 234954.834621 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 159238 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 14593 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.911944 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104274685 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104274685 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8607905090 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8607905090 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8712179775 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8712179775 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8712179775 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114587.565934 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114587.565934 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 184244.543878 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 184244.543878 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 182913.705123 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 182913.705123 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -446,22 +439,22 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 637650 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225557 # Transaction distribution -system.iobus.trans_dist::ReadResp 225557 # Transaction distribution -system.iobus.trans_dist::WriteReq 57591 # Transaction distribution -system.iobus.trans_dist::WriteResp 57591 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 638663 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225570 # Transaction distribution +system.iobus.trans_dist::ReadResp 225570 # Transaction distribution +system.iobus.trans_dist::WriteReq 57606 # Transaction distribution +system.iobus.trans_dist::WriteResp 57606 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -471,21 +464,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569582 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -495,20 +488,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241801 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276197 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3919904 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276260 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -520,7 +513,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213678000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -538,274 +531,273 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424855274 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460165000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53596501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 85854110 # Number of BP lookups -system.cpu.branchPred.condPredicted 85854110 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 890492 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79431123 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77651636 # Number of BTB hits +system.cpu.branchPred.lookups 86877356 # Number of BP lookups +system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.759711 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1460640 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 181048 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 452853570 # number of cpu cycles simulated +system.cpu.numCycles 449309558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25683785 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 423946474 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85854110 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79112276 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162997927 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4233083 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 105681 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 69250991 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42777 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 91487 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 266 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8611652 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 409614 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2534 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 261469410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.201181 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.413215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98890192 37.82% 37.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1558006 0.60% 38.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71842115 27.48% 65.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 921619 0.35% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1585920 0.61% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2431144 0.93% 67.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1036910 0.40% 68.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1345104 0.51% 68.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81858400 31.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 261469410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.189585 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.936167 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29046589 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 66961601 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159616384 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2548340 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3296496 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 834624632 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3296496 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31320829 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 35759496 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12826241 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159575235 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 18691113 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 831621243 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 271968 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7201596 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 103405 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 9490411 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 993545092 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1805477878 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1109904628 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 111 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963933701 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29611389 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 457228 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 464601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 24223020 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16966534 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9968316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1221781 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 988150 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 826572087 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1194475 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 821819105 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 208862 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20915933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32275833 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 139879 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 261469410 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.143079 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.407689 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76437702 29.23% 29.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14614697 5.59% 34.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10065724 3.85% 38.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7027094 2.69% 41.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75658650 28.94% 70.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3979218 1.52% 71.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72575299 27.76% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 879014 0.34% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 232012 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 261469410 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 395534 35.48% 35.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 246 0.02% 35.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 260 0.02% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 578947 51.93% 87.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 139812 12.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 313841 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 794169455 96.64% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150148 0.02% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125336 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17790783 2.16% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9269542 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 821819105 # Type of FU issued -system.cpu.iq.rate 1.814757 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1114799 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001357 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1906543911 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 848693742 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 817833447 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 176 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 822619981 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1787791 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued +system.cpu.iq.rate 1.833972 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2974113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1545780 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1935112 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35450 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3296496 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15966541 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12762115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 827766562 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 204474 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16966534 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9968316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 698992 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1766485 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10560079 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 503157 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 519909 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1023066 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 820377360 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17471183 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1441744 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26545601 # number of memory reference insts executed -system.cpu.iew.exec_branches 83164783 # Number of branches executed -system.cpu.iew.exec_stores 9074418 # Number of stores executed -system.cpu.iew.exec_rate 1.811573 # Inst execution rate -system.cpu.iew.wb_sent 819943769 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 817833497 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640559141 # num instructions producing a value -system.cpu.iew.wb_consumers 1047723157 # num instructions consuming a value +system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed +system.cpu.iew.exec_branches 83281301 # Number of branches executed +system.cpu.iew.exec_stores 9170301 # Number of stores executed +system.cpu.iew.exec_rate 1.830351 # Inst execution rate +system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640810294 # num instructions producing a value +system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805956 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611382 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21640086 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054596 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 900184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258172914 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.122020 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.868515 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87519981 33.90% 33.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11178946 4.33% 38.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3524931 1.37% 39.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74556840 28.88% 68.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2487891 0.96% 69.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1503617 0.58% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865491 0.34% 70.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70822706 27.43% 97.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5712511 2.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258172914 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407759509 # Number of instructions committed -system.cpu.commit.committedOps 806020953 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407773893 # Number of instructions committed +system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22414956 # Number of memory references committed -system.cpu.commit.loads 13992420 # Number of loads committed -system.cpu.commit.membars 474659 # Number of memory barriers committed -system.cpu.commit.branches 82156165 # Number of branches committed +system.cpu.commit.refs 22417793 # Number of memory references committed +system.cpu.commit.loads 13993103 # Number of loads committed +system.cpu.commit.membars 474875 # Number of memory barriers committed +system.cpu.commit.branches 82158924 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734866809 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155346 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174342 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783165220 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144784 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121651 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734892496 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155452 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -832,213 +824,214 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13992420 1.74% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8422536 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806020953 # Class of committed instruction -system.cpu.commit.bw_lim_events 5712511 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction +system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1080043164 # The number of ROB reads -system.cpu.rob.rob_writes 1658634797 # The number of ROB writes -system.cpu.timesIdled 1275471 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191384160 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823003775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407759509 # Number of Instructions Simulated -system.cpu.committedOps 806020953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.110590 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.110590 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.900422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1089597141 # number of integer regfile reads -system.cpu.int_regfile_writes 654482969 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.cc_regfile_reads 415870022 # number of cc regfile reads -system.cpu.cc_regfile_writes 321677512 # number of cc regfile writes -system.cpu.misc_regfile_reads 264445635 # number of misc regfile reads -system.cpu.misc_regfile_writes 402422 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53724216 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3026047 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3025482 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1581183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 156212 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8229172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61697728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207710542 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 574144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5436928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 275419342 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 275396046 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 635008 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4043112921 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1267985613 # The number of ROB reads +system.cpu.rob.rob_writes 1664458820 # The number of ROB writes +system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407773893 # Number of Instructions Simulated +system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads +system.cpu.int_regfile_writes 655889202 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads +system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes +system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads +system.cpu.misc_regfile_writes 402606 # number of misc regfile writes +system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 546000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1449735220 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3140330868 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 14620748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 106945143 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 963566 # number of replacements -system.cpu.icache.tags.tagsinuse 509.311037 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7590970 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 964078 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.873813 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147613206250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.311037 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994748 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994748 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 997506 # number of replacements +system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9575846 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9575846 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7590970 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7590970 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7590970 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7590970 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7590970 # number of overall hits -system.cpu.icache.overall_hits::total 7590970 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1020680 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1020680 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1020680 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1020680 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1020680 # number of overall misses -system.cpu.icache.overall_misses::total 1020680 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179701612 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14179701612 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14179701612 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14179701612 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14179701612 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14179701612 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8611650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8611650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8611650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8611650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8611650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8611650 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118523 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.118523 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.118523 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.118523 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.118523 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.118523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13892.406643 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13892.406643 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13892.406643 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13892.406643 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13892.406643 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13892.406643 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4723 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8120756 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # 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number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 198 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.853535 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56484 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56484 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56484 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56484 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12125.031654 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12125.031654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12125.031654 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8862 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.026427 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 19635 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8877 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.211896 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5109382719500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.026427 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376652 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376652 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.827244 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104029760000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.005977 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375374 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375374 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 68718 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 68718 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 19738 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 19738 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 19740 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 19740 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 19740 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 19740 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9746 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 9746 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9746 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 9746 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9746 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 9746 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 105945749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 105945749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 105945749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 105945749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 105945749 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 105945749 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 29484 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 29484 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 29486 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 29486 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 29486 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 29486 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.330552 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.330552 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.330530 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.330530 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.330530 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.330530 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10870.690437 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10870.690437 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10870.690437 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10870.690437 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10870.690437 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1047,85 +1040,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1636 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1636 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9746 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9746 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9746 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 9746 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9746 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 9746 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86450253 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86450253 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86450253 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86450253 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86450253 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86450253 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.330552 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.330552 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.330530 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.330530 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.330530 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8870.331726 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8870.331726 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8870.331726 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 70197 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 14.820412 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92434 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 70211 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.316517 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101611575500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.820412 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.926276 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.926276 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 398660 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 398660 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92440 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92440 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92440 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92440 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92440 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92440 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71260 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 71260 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71260 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 71260 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71260 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 71260 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 875246716 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 875246716 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 875246716 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 875246716 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 875246716 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 875246716 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 163700 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 163700 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 163700 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 163700 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 163700 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 163700 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.435308 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.435308 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.435308 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.435308 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.435308 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.435308 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12282.440584 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12282.440584 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12282.440584 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12282.440584 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12282.440584 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1134,153 +1127,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 20047 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 20047 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71260 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71260 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71260 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 71260 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71260 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 71260 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 732616430 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 732616430 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 732616430 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 732616430 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 732616430 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 732616430 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.435308 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.435308 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.435308 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.435308 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10280.892927 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10280.892927 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10280.892927 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1657713 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996506 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19009946 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1658225 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.464033 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 39778250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996506 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1659582 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87793833 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87793833 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10909808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10909808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8097329 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8097329 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19007137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19007137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19007137 # number of overall hits -system.cpu.dcache.overall_hits::total 19007137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2211100 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2211100 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315662 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2526762 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2526762 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2526762 # number of overall misses -system.cpu.dcache.overall_misses::total 2526762 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32878750930 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32878750930 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12078727781 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12078727781 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44957478711 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44957478711 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44957478711 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44957478711 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13120908 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13120908 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8412991 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8412991 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21533899 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21533899 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21533899 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21533899 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037521 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037521 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117339 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117339 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117339 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117339 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14869.861576 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14869.861576 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38264.750844 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38264.750844 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17792.526052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17792.526052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17792.526052 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 428041 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits +system.cpu.dcache.overall_hits::total 19128122 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses +system.cpu.dcache.overall_misses::total 2540999 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 36530 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40145 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.717520 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559500 # number of writebacks -system.cpu.dcache.writebacks::total 1559500 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840350 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840350 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25845 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1660567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17852039460 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17852039460 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11191134624 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11191134624 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29043174084 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29043174084 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29043174084 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29043174084 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363185500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363185500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99899391000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99899391000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104471 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034449 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077114 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077114 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077114 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077114 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13023.556053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13023.556053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38614.486466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38614.486466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17489.914038 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17489.914038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17489.914038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17489.914038 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks +system.cpu.dcache.writebacks::total 1560667 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 875195 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 875195 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 875195 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970313 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 970313 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289146 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402890 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402890 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1259459 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1259459 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1662349 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1662349 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12260897766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12260897766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11156657127 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11156657127 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584385500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584385500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23417554893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23417554893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29001940393 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29001940393 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364665000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364665000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539423000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539423000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99904088000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99904088000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075909 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # 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average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1288,150 +1297,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64820.835708 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3791752 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176203 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.519225 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112856 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64816.166677 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3836348 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176998 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.674527 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50598.140423 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.189472 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125676 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2974.923375 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11234.456763 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.772066 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.855148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3265.471036 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768917 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045394 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.171424 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 534 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6277 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53619 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 34689659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 34689659 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64846 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 947840 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1333918 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2353934 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1581183 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1581183 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10036553884 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11063857145 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4137750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1051024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006962531 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11062648531 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4346250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 315250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1022850261 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10036553884 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11063857145 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250074000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250074000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370675000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370675000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91620749000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91620749000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026357 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021759 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.825337 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.825337 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464940 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464940 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069072 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000909 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000682 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016788 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102450 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.069072 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1051024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006962531 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11062648531 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251423000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251423000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373128500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373128500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624551500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624551500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021368 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823631 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823631 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464896 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464896 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016429 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102033 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067878 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 63050 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63201.326063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66455.955442 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65453.757057 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10641.745265 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10641.745265 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57113.589053 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57113.589053 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64102.494511 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66651.187065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65851.632170 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.591323 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.591323 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57070.297166 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57070.297166 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 70131.355932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65852.272727 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 63050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63201.326063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.085878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59460.405678 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64102.494511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59100.889033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59544.793398 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 307acd090..f26bf1c54 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.135764 # Number of seconds simulated -sim_ticks 5135763847500 # Number of ticks simulated -final_tick 5135763847500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137881 # Number of seconds simulated +sim_ticks 5137881357500 # Number of ticks simulated +final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 259782 # Simulator instruction rate (inst/s) -host_op_rate 516376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5470381356 # Simulator tick rate (ticks/s) -host_mem_usage 959692 # Number of bytes of host memory used -host_seconds 938.83 # Real time elapsed on the host -sim_insts 243891279 # Number of instructions simulated -sim_ops 484789360 # Number of ops (including micro ops) simulated +host_inst_rate 401147 # Simulator instruction rate (inst/s) +host_op_rate 797370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8430324111 # Simulator tick rate (ticks/s) +host_mem_usage 944704 # Number of bytes of host memory used +host_seconds 609.45 # Real time elapsed on the host +sim_insts 244480058 # Number of instructions simulated +sim_ops 485958826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2442432 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 470912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6169536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 114240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1582592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 379456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2632640 # Number of bytes read from this memory -system.physmem.bytes_read::total 13794368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 470912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 114240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 379456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9131520 # Number of bytes written to this memory -system.physmem.bytes_written::total 9131520 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38163 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory +system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory +system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory +system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7358 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 96399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24728 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41135 # Number of read requests responded to by this memory -system.physmem.num_reads::total 215537 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142680 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142680 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475573 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory +system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 91693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1201289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 22244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 308151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 512609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2685943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 91693 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 22244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73885 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1778026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1778026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1778026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 91693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1201289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 22244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 308151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 512609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4463968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 94056 # Number of read requests accepted -system.physmem.writeReqs 72760 # Number of write requests accepted -system.physmem.readBursts 94056 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 72760 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6015488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4096 # Total number of bytes read from write queue -system.physmem.bytesWritten 4656640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6019584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4656640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 64 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83494 # Number of read requests accepted +system.physmem.writeReqs 76163 # Number of write requests accepted +system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue +system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 766 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5609 # Per bank write bursts -system.physmem.perBankRdBursts::1 5668 # Per bank write bursts -system.physmem.perBankRdBursts::2 5585 # Per bank write bursts -system.physmem.perBankRdBursts::3 5594 # Per bank write bursts -system.physmem.perBankRdBursts::4 6037 # Per bank write bursts -system.physmem.perBankRdBursts::5 6612 # Per bank write bursts -system.physmem.perBankRdBursts::6 5733 # Per bank write bursts -system.physmem.perBankRdBursts::7 5990 # Per bank write bursts -system.physmem.perBankRdBursts::8 5523 # Per bank write bursts -system.physmem.perBankRdBursts::9 5460 # Per bank write bursts -system.physmem.perBankRdBursts::10 5647 # Per bank write bursts -system.physmem.perBankRdBursts::11 6128 # Per bank write bursts -system.physmem.perBankRdBursts::12 6059 # Per bank write bursts -system.physmem.perBankRdBursts::13 6267 # Per bank write bursts -system.physmem.perBankRdBursts::14 6194 # Per bank write bursts -system.physmem.perBankRdBursts::15 5886 # Per bank write bursts -system.physmem.perBankWrBursts::0 4545 # Per bank write bursts -system.physmem.perBankWrBursts::1 4402 # Per bank write bursts -system.physmem.perBankWrBursts::2 4127 # Per bank write bursts -system.physmem.perBankWrBursts::3 4299 # Per bank write bursts -system.physmem.perBankWrBursts::4 4675 # Per bank write bursts -system.physmem.perBankWrBursts::5 5126 # Per bank write bursts -system.physmem.perBankWrBursts::6 4327 # Per bank write bursts -system.physmem.perBankWrBursts::7 4679 # Per bank write bursts -system.physmem.perBankWrBursts::8 4360 # Per bank write bursts -system.physmem.perBankWrBursts::9 4207 # Per bank write bursts -system.physmem.perBankWrBursts::10 4528 # Per bank write bursts -system.physmem.perBankWrBursts::11 4822 # Per bank write bursts -system.physmem.perBankWrBursts::12 4836 # Per bank write bursts -system.physmem.perBankWrBursts::13 4641 # Per bank write bursts -system.physmem.perBankWrBursts::14 4944 # Per bank write bursts -system.physmem.perBankWrBursts::15 4242 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4736 # Per bank write bursts +system.physmem.perBankRdBursts::1 4757 # Per bank write bursts +system.physmem.perBankRdBursts::2 5051 # Per bank write bursts +system.physmem.perBankRdBursts::3 5281 # Per bank write bursts +system.physmem.perBankRdBursts::4 5400 # Per bank write bursts +system.physmem.perBankRdBursts::5 4765 # Per bank write bursts +system.physmem.perBankRdBursts::6 4961 # Per bank write bursts +system.physmem.perBankRdBursts::7 5223 # Per bank write bursts +system.physmem.perBankRdBursts::8 5069 # Per bank write bursts +system.physmem.perBankRdBursts::9 5177 # Per bank write bursts +system.physmem.perBankRdBursts::10 4953 # Per bank write bursts +system.physmem.perBankRdBursts::11 4660 # Per bank write bursts +system.physmem.perBankRdBursts::12 5195 # Per bank write bursts +system.physmem.perBankRdBursts::13 6216 # Per bank write bursts +system.physmem.perBankRdBursts::14 6082 # Per bank write bursts +system.physmem.perBankRdBursts::15 5780 # Per bank write bursts +system.physmem.perBankWrBursts::0 4915 # Per bank write bursts +system.physmem.perBankWrBursts::1 4846 # Per bank write bursts +system.physmem.perBankWrBursts::2 4413 # Per bank write bursts +system.physmem.perBankWrBursts::3 4685 # Per bank write bursts +system.physmem.perBankWrBursts::4 5227 # Per bank write bursts +system.physmem.perBankWrBursts::5 4409 # Per bank write bursts +system.physmem.perBankWrBursts::6 4642 # Per bank write bursts +system.physmem.perBankWrBursts::7 4533 # Per bank write bursts +system.physmem.perBankWrBursts::8 4328 # Per bank write bursts +system.physmem.perBankWrBursts::9 4737 # Per bank write bursts +system.physmem.perBankWrBursts::10 4592 # Per bank write bursts +system.physmem.perBankWrBursts::11 4470 # Per bank write bursts +system.physmem.perBankWrBursts::12 4760 # Per bank write bursts +system.physmem.perBankWrBursts::13 5234 # Per bank write bursts +system.physmem.perBankWrBursts::14 5550 # Per bank write bursts +system.physmem.perBankWrBursts::15 4796 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5131947184500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5136881165000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 94056 # Read request sizes (log2) +system.physmem.readPktSize::6 83494 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 72760 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1995 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 76163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,474 +168,475 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4114 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 35723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.746690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.799684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.095227 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14318 40.08% 40.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8282 23.18% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3507 9.82% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1954 5.47% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1307 3.66% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 922 2.58% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 623 1.74% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 530 1.48% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4280 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 35723 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.627954 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 119.433357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 3969 99.77% 99.77% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 7 0.18% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38507 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 264.993274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 160.426697 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.053955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15907 41.31% 41.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9655 25.07% 66.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3981 10.34% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2127 5.52% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1469 3.81% 86.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1046 2.72% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 664 1.72% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 555 1.44% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 121.265146 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 8 0.21% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3978 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.290598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.208175 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.685696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 45 1.13% 1.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 5 0.13% 1.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 3 0.08% 1.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 4 0.10% 1.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.03% 1.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 5 0.13% 1.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2627 66.04% 67.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 818 20.56% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 28 0.70% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 32 0.80% 89.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 32 0.80% 90.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 35 0.88% 91.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 65 1.63% 93.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 48 1.21% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 35 0.88% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 29 0.73% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 29 0.73% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 26 0.65% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 31 0.78% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 18 0.45% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 10 0.25% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 17 0.43% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.20% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 6 0.15% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.05% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 7 0.18% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 3 0.08% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 4 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::66-67 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3978 # Writes before turning the bus around for reads -system.physmem.totQLat 2424873249 # Total ticks spent queuing -system.physmem.totMemAccLat 4187223249 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 469960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25798.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.599143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.462049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.21% 1.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.26% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3269 84.84% 87.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads +system.physmem.totQLat 942120750 # Total ticks spent queuing +system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44548.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.97 # Average write queue length when enqueuing -system.physmem.readRowHits 76538 # Number of row buffer hits during reads -system.physmem.writeRowHits 54491 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.89 # Row buffer hit rate for writes -system.physmem.avgGap 30764118.46 # Average gap between requests -system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942425043001 # Time in different power states -system.physmem.memoryStateTime::REF 171494180000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing +system.physmem.readRowHits 65566 # Number of row buffer hits during reads +system.physmem.writeRowHits 55368 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes +system.physmem.avgGap 32174481.33 # Average gap between requests +system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states +system.physmem.memoryStateTime::REF 171564900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21844559499 # Time in different power states +system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 6452408 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 421921 # Transaction distribution -system.membus.trans_dist::ReadResp 421919 # Transaction distribution -system.membus.trans_dist::WriteReq 5915 # Transaction distribution -system.membus.trans_dist::WriteResp 5915 # Transaction distribution -system.membus.trans_dist::Writeback 72760 # Transaction distribution -system.membus.trans_dist::UpgradeReq 778 # Transaction distribution -system.membus.trans_dist::UpgradeResp 778 # Transaction distribution -system.membus.trans_dist::ReadExReq 75224 # Transaction distribution -system.membus.trans_dist::ReadExResp 75224 # Transaction distribution -system.membus.trans_dist::MessageReq 825 # Transaction distribution -system.membus.trans_dist::MessageResp 825 # Transaction distribution -system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 308134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1002050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1075932 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 157715 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995169 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7734720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 8887604 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2941504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2941504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11832408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32744958 # Total data (bytes) -system.membus.snoop_data_through_bus 393088 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 161596500 # Layer occupancy (ticks) +system.membus.throughput 5877722 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 425622 # Transaction distribution +system.membus.trans_dist::ReadResp 425619 # Transaction distribution +system.membus.trans_dist::WriteReq 7303 # Transaction distribution +system.membus.trans_dist::WriteResp 7303 # Transaction distribution +system.membus.trans_dist::Writeback 54691 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution +system.membus.trans_dist::UpgradeReq 873 # Transaction distribution +system.membus.trans_dist::UpgradeResp 873 # Transaction distribution +system.membus.trans_dist::ReadExReq 56661 # Transaction distribution +system.membus.trans_dist::ReadExResp 56661 # Transaction distribution +system.membus.trans_dist::MessageReq 1005 # Transaction distribution +system.membus.trans_dist::MessageResp 1005 # Transaction distribution +system.membus.trans_dist::BadAddressError 3 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30180989 # Total data (bytes) +system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315113000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1650000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 794070497 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 825000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1569908183 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 236956000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104346 # number of replacements -system.l2c.tags.tagsinuse 64811.945905 # Cycle average of tags in use -system.l2c.tags.total_refs 3669840 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168730 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.749778 # Average number of references to valid blocks. +system.l2c.tags.replacements 105452 # number of replacements +system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use +system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51276.768453 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121941 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1221.298902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4234.138382 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 249.507225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1581.676468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.253356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1493.843089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4747.335130 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.782421 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.018636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064608 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.024134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000111 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.022794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.072439 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988952 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2861 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7799 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53379 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33692585 # Number of tag accesses -system.l2c.tags.data_accesses 33692585 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 348846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 522725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9533 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5021 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 144714 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 221166 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 56163 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10079 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 347465 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 563204 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2259696 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.015867 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058859 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004534 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023271 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.027352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.081308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64192 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 605 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3319 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7395 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52837 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979492 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33876235 # Number of tag accesses +system.l2c.tags.data_accesses 33876235 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20790 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10881 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 323642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493790 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 11848 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 159823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 243124 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 53625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12570 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 372046 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 571492 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2280010 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1546042 # number of Writeback hits -system.l2c.Writeback_hits::total 1546042 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 139 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 47 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 73 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 259 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 69718 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 41748 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 55006 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166472 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 348846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 592443 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 144714 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 262914 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 56163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 347465 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 618210 # number of demand (read+write) hits -system.l2c.demand_hits::total 2426170 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19944 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10838 # number of overall hits -system.l2c.overall_hits::cpu0.inst 348846 # number of overall hits -system.l2c.overall_hits::cpu0.data 592443 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9533 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5021 # number of overall hits -system.l2c.overall_hits::cpu1.inst 144714 # number of overall hits -system.l2c.overall_hits::cpu1.data 262914 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 56163 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10079 # number of overall hits -system.l2c.overall_hits::cpu2.inst 347465 # number of overall hits -system.l2c.overall_hits::cpu2.data 618210 # number of overall hits -system.l2c.overall_hits::total 2426170 # number of overall hits +system.l2c.Writeback_hits::writebacks 1547750 # number of Writeback hits +system.l2c.Writeback_hits::total 1547750 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 119 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 62 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 66 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 247 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 66599 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 37683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 62729 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167011 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 20790 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10883 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 323642 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 560389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 159823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 280807 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 53625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 12570 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 372046 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 634221 # number of demand (read+write) hits +system.l2c.demand_hits::total 2447023 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 20790 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10883 # number of overall hits +system.l2c.overall_hits::cpu0.inst 323642 # number of overall hits +system.l2c.overall_hits::cpu0.data 560389 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 11848 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6379 # number of overall hits +system.l2c.overall_hits::cpu1.inst 159823 # number of overall hits +system.l2c.overall_hits::cpu1.data 280807 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 53625 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 12570 # number of overall hits +system.l2c.overall_hits::cpu2.inst 372046 # number of overall hits +system.l2c.overall_hits::cpu2.data 634221 # number of overall hits +system.l2c.overall_hits::total 2447023 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7359 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 16415 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1785 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4252 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 35 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5929 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12239 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48019 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 765 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 259 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1375 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 80419 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 20642 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 29214 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130275 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 6200 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 15808 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2342 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4299 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 6737 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 12987 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48409 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 731 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 353 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 335 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1419 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 73318 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 24339 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 32507 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130164 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7359 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 96834 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1785 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 24894 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 35 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5929 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 41453 # number of demand (read+write) misses -system.l2c.demand_misses::total 178294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6200 # 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number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 735 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 25536 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 25536 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 26271 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 26271 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 26271 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 26271 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92456791 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92456791 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4688241758 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4688241758 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4780698549 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4780698549 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4780698549 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.809471 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.809471 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.546575 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.546575 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.551587 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.551587 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.551587 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125791.552381 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 125791.552381 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 183593.427240 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 183593.427240 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 181976.268471 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 181976.268471 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -879,511 +884,555 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52407719 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1793633 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1793101 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 5915 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 5915 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 899960 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 730 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 730 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 172146 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 146613 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 999818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3602290 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 141650 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4778107 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31993152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119401652 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 120808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525848 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 152041460 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 269011854 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 141816 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5025953302 # Layer occupancy (ticks) +system.toL2Bus.throughput 53202678 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 270199237 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 936000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2251918114 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4677619434 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 19272449 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 76057203 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1276582 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149714 # Transaction distribution -system.iobus.trans_dist::ReadResp 149714 # Transaction distribution -system.iobus.trans_dist::WriteReq 30624 # Transaction distribution -system.iobus.trans_dist::WriteResp 30624 # Transaction distribution -system.iobus.trans_dist::MessageReq 825 # Transaction distribution -system.iobus.trans_dist::MessageResp 825 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4890 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1275815 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 151004 # Transaction distribution +system.iobus.trans_dist::ReadResp 151004 # Transaction distribution +system.iobus.trans_dist::WriteReq 27777 # Transaction distribution +system.iobus.trans_dist::WriteResp 27777 # Transaction distribution +system.iobus.trans_dist::MessageReq 1005 # Transaction distribution +system.iobus.trans_dist::MessageResp 1005 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 588 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287208 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 156 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 13026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 308134 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 52542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 52542 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1650 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 362326 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2760 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 294 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 12 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143604 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 6513 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 157715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1670648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1670648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3300 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1831663 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6556225 # Total data (bytes) -system.iobus.reqLayer0.occupancy 1987954 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1188 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 160913 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1410472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 4020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6554984 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4046000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 387000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 143605000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 124000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9774000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 232428549 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 303046000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31488000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 825000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1167096017 # number of cpu cycles simulated +system.cpu0.numCycles 1069887436 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72932334 # Number of instructions committed -system.cpu0.committedOps 148186849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 136173063 # Number of integer alu accesses +system.cpu0.committedInsts 70857782 # Number of instructions committed +system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1014433 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14332221 # number of instructions that are conditional controls -system.cpu0.num_int_insts 136173063 # number of integer instructions +system.cpu0.num_func_calls 941314 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls +system.cpu0.num_int_insts 132405898 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 250637191 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116800630 # number of times the integer registers were written +system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84487712 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56367816 # number of times the CC registers were written -system.cpu0.num_mem_refs 14369378 # number of memory refs -system.cpu0.num_load_insts 10451844 # Number of load instructions -system.cpu0.num_store_insts 3917534 # Number of store instructions -system.cpu0.num_idle_cycles 1108227141.183960 # Number of idle cycles -system.cpu0.num_busy_cycles 58868875.816040 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050440 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949560 # Percentage of idle cycles -system.cpu0.Branches 15712912 # Number of branches fetched -system.cpu0.op_class::No_OpClass 100385 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 133601927 90.16% 90.23% # Class of executed instruction -system.cpu0.op_class::IntMult 62763 0.04% 90.27% # Class of executed instruction -system.cpu0.op_class::IntDiv 53014 0.04% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.30% # Class of executed instruction -system.cpu0.op_class::MemRead 10451844 7.05% 97.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 3917534 2.64% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written +system.cpu0.num_mem_refs 13631596 # number of memory refs +system.cpu0.num_load_insts 10001277 # Number of load instructions +system.cpu0.num_store_insts 3630319 # Number of store instructions +system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles +system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles +system.cpu0.Branches 15304700 # Number of branches fetched +system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction +system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction +system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 148187467 # Class of executed instruction +system.cpu0.op_class::total 144308194 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 855609 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.820181 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129797062 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856121 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 151.610651 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147456803500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.387192 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 131.510981 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 82.922008 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.578881 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.256857 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.161957 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997696 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 870298 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.224543 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128999874 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 870810 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 148.137796 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131529533 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131529533 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 88736608 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38254506 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2805948 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129797062 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 88736608 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38254506 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2805948 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129797062 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 88736608 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38254506 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2805948 # number of overall hits -system.cpu0.icache.overall_hits::total 129797062 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 356206 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 146499 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 373635 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 876340 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 356206 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 146499 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 373635 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 876340 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 356206 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 146499 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 373635 # number of overall misses -system.cpu0.icache.overall_misses::total 876340 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 10823350039 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15515184486 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30492689000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33165040000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63657729000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 394150500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 725206000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1119356500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30886839500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33890246000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64777085500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.118564 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.060350 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037581 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017533 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.043751 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.067885 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086016 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.043751 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12282.105892 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14017.294350 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13528.913557 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30675.429070 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32581.924924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31770.476056 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16284.645824 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16396.853807 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16362.759042 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1547750 # number of writebacks +system.cpu0.dcache.writebacks::total 1547750 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 72 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 345273 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 345345 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1671 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26387 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 28058 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 371660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 373403 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 371660 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 373403 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171687 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 405767 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 577454 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62425 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95586 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 158011 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75736 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 178762 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 254498 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 234112 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 501353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 735465 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309848 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 680115 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 989963 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2023850750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5632729880 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7656580630 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2144841050 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3093501359 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5238342409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 984108500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2694382756 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3678491256 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4168691800 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8726231239 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12894923039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5152800300 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11420613995 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16573414295 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30657477000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33314384500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63971861500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 501111500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 893222000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394333500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31158588500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34207606500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65366195000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060792 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085267 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045070 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034642 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032158 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018807 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.863187 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.843348 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.546074 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050606 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064849 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034669 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065731 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085623 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11788.025593 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13881.685499 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13259.204421 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34358.687225 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32363.540257 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33151.757846 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12993.932872 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15072.458106 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14453.910270 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17806.399501 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17405.363564 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17533.020659 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16630.090561 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16792.180727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1394,377 +1443,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604023259 # number of cpu cycles simulated +system.cpu1.numCycles 2606024060 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 34762499 # Number of instructions committed -system.cpu1.committedOps 67606793 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 62736553 # Number of integer alu accesses +system.cpu1.committedInsts 35944624 # Number of instructions committed +system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 437056 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6403696 # number of instructions that are conditional controls -system.cpu1.num_int_insts 62736553 # number of integer instructions +system.cpu1.num_func_calls 484528 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64937038 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 115724590 # number of times the integer registers were read -system.cpu1.num_int_register_writes 54164636 # number of times the integer registers were written +system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35537675 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26584960 # number of times the CC registers were written -system.cpu1.num_mem_refs 4433444 # number of memory refs -system.cpu1.num_load_insts 2764122 # Number of load instructions -system.cpu1.num_store_insts 1669322 # Number of store instructions -system.cpu1.num_idle_cycles 2476870816.288117 # Number of idle cycles -system.cpu1.num_busy_cycles 127152442.711883 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048829 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951171 # Percentage of idle cycles -system.cpu1.Branches 7001569 # Number of branches fetched -system.cpu1.op_class::No_OpClass 28648 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 63095899 93.33% 93.37% # Class of executed instruction -system.cpu1.op_class::IntMult 28577 0.04% 93.41% # Class of executed instruction -system.cpu1.op_class::IntDiv 20525 0.03% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.44% # Class of executed instruction -system.cpu1.op_class::MemRead 2764122 4.09% 97.53% # Class of executed instruction -system.cpu1.op_class::MemWrite 1669322 2.47% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written +system.cpu1.num_mem_refs 4904439 # number of memory refs +system.cpu1.num_load_insts 3100845 # Number of load instructions +system.cpu1.num_store_insts 1803594 # Number of store instructions +system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles +system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles +system.cpu1.Branches 7263647 # Number of branches fetched +system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction +system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction +system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction +system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 67607093 # Class of executed instruction +system.cpu1.op_class::total 69816412 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28894520 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28894520 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 314484 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26386768 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25807983 # Number of BTB hits +system.cpu2.branchPred.lookups 29512659 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.806533 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 541788 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 61672 # Number of incorrect RAS predictions. -system.cpu2.numCycles 154118891 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155365551 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9526926 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142222809 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28894520 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26349771 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54464711 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1558370 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 64917 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 23183087 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 4981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 6096 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 25004 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 241 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3179586 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 151181 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1925 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 88503258 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.167922 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.413230 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 34173678 38.61% 38.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 596420 0.67% 39.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23721602 26.80% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 320974 0.36% 66.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 619988 0.70% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 815233 0.92% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 353145 0.40% 68.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 523827 0.59% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27378391 30.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 88503258 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.187482 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.922812 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10770329 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 22316529 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 33210052 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 993418 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1230628 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279539625 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 15 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1230628 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11632631 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 11620518 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4366536 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 33251587 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 6419117 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278526444 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 145793 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2942087 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 39888 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 2722851 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 332982462 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 606515542 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372413837 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 42 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 321866415 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11116047 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 145000 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 146469 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 9034946 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6263244 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3375371 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 381006 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 309187 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276743563 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 411647 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274777165 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83308 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7862427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12385425 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 57804 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 88503258 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.104712 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.400001 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 25772149 29.12% 29.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5479119 6.19% 35.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3780646 4.27% 39.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2658058 3.00% 42.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25098242 28.36% 70.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1415095 1.60% 72.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23897363 27.00% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 310729 0.35% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 91857 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 88503258 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 130084 34.74% 34.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 34.74% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 103 0.03% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 196279 52.42% 87.18% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 48005 12.82% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 79957 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264964709 96.43% 96.46% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 54296 0.02% 96.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50937 0.02% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.50% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6495012 2.36% 98.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3132254 1.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268083598 96.29% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 47134 0.02% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274777165 # Type of FU issued -system.cpu2.iq.rate 1.782891 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 374471 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001363 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 638559252 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285021199 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273394851 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 74 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 14 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275071659 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 655974 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued +system.cpu2.iq.rate 1.791929 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1102337 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6308 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4079 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 550460 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656385 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 7890 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1230628 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6003858 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 2680102 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277155210 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55656 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6263266 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3375371 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 233323 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 631738 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1840063 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4079 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 177700 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 182074 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 359774 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274266101 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6377623 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 511064 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9440682 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27899539 # Number of branches executed -system.cpu2.iew.exec_stores 3063059 # Number of stores executed -system.cpu2.iew.exec_rate 1.779575 # Inst execution rate -system.cpu2.iew.wb_sent 274107922 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273394865 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213810949 # num instructions producing a value -system.cpu2.iew.wb_consumers 349940477 # num instructions consuming a value +system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28210243 # Number of branches executed +system.cpu2.iew.exec_stores 3262728 # Number of stores executed +system.cpu2.iew.exec_rate 1.788200 # Inst execution rate +system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215923076 # num instructions producing a value +system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.773922 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.610992 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8157845 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 353843 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 317282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 87272630 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 3.082246 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.874009 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 30201439 34.61% 34.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4017102 4.60% 39.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1154677 1.32% 40.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24628965 28.22% 68.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 905267 1.04% 69.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 589610 0.68% 70.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 344278 0.39% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23302755 26.70% 97.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2128537 2.44% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 87272630 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 136196446 # Number of instructions committed -system.cpu2.commit.committedOps 268995718 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137677652 # Number of instructions committed +system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 7985840 # Number of memory references committed -system.cpu2.commit.loads 5160929 # Number of loads committed -system.cpu2.commit.membars 163767 # Number of memory barriers committed -system.cpu2.commit.branches 27540439 # Number of branches committed +system.cpu2.commit.refs 8244394 # Number of memory references committed +system.cpu2.commit.loads 5266658 # Number of loads committed +system.cpu2.commit.membars 166791 # Number of memory barriers committed +system.cpu2.commit.branches 27802655 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 245590309 # Number of committed integer instructions. -system.cpu2.commit.function_calls 428081 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46387 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 260861796 96.98% 96.99% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 52266 0.02% 97.01% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 49429 0.02% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.03% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5160929 1.92% 98.95% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2824911 1.05% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions. +system.cpu2.commit.function_calls 440588 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268995718 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2128537 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 362270810 # The number of ROB reads -system.cpu2.rob.rob_writes 555542201 # The number of ROB writes -system.cpu2.timesIdled 475518 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65615633 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908375985 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 136196446 # Number of Instructions Simulated -system.cpu2.committedOps 268995718 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.131593 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.131593 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.883710 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.883710 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364616127 # number of integer regfile reads -system.cpu2.int_regfile_writes 219111496 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72926 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139466740 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107376389 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88828545 # number of misc regfile reads -system.cpu2.misc_regfile_writes 129118 # number of misc regfile writes +system.cpu2.rob.rob_reads 431889681 # The number of ROB reads +system.cpu2.rob.rob_writes 563202973 # The number of ROB writes +system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137677652 # Number of Instructions Simulated +system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads +system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads +system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |