diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/fs | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/fs')
28 files changed, 43508 insertions, 43380 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 3b6b51422..a07783bfc 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906037 # Number of seconds simulated -sim_ticks 1906037467000 # Number of ticks simulated -final_tick 1906037467000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906049 # Number of seconds simulated +sim_ticks 1906048606500 # Number of ticks simulated +final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252781 # Simulator instruction rate (inst/s) -host_op_rate 252781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8583432112 # Simulator tick rate (ticks/s) -host_mem_usage 376892 # Number of bytes of host memory used -host_seconds 222.06 # Real time elapsed on the host -sim_insts 56132533 # Number of instructions simulated -sim_ops 56132533 # Number of ops (including micro ops) simulated +host_inst_rate 269376 # Simulator instruction rate (inst/s) +host_op_rate 269376 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9144869235 # Simulator tick rate (ticks/s) +host_mem_usage 376080 # Number of bytes of host memory used +host_seconds 208.43 # Real time elapsed on the host +sim_insts 56145568 # Number of instructions simulated +sim_ops 56145568 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1050496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25909440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1050496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1050496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7563136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7563136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404835 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118142 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118142 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 551141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13041708 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404756 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118174 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118174 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13042035 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13593353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 551141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 551141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3966915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3966915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3966915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 551141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13041708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13590621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3967966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3967966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3967966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13042035 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17560268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404835 # Number of read requests accepted -system.physmem.writeReqs 118142 # Number of write requests accepted -system.physmem.readBursts 404835 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118142 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25902720 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 7559680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25909440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7561088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17558587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404756 # Number of read requests accepted +system.physmem.writeReqs 118174 # Number of write requests accepted +system.physmem.readBursts 404756 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118174 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25897280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7561536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25904384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41709 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25494 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts -system.physmem.perBankRdBursts::2 25829 # Per bank write bursts -system.physmem.perBankRdBursts::3 25773 # Per bank write bursts -system.physmem.perBankRdBursts::4 25090 # Per bank write bursts -system.physmem.perBankRdBursts::5 25012 # Per bank write bursts -system.physmem.perBankRdBursts::6 24715 # Per bank write bursts -system.physmem.perBankRdBursts::7 24579 # Per bank write bursts -system.physmem.perBankRdBursts::8 25194 # Per bank write bursts -system.physmem.perBankRdBursts::9 25292 # Per bank write bursts -system.physmem.perBankRdBursts::10 25390 # Per bank write bursts -system.physmem.perBankRdBursts::11 24989 # Per bank write bursts -system.physmem.perBankRdBursts::12 24533 # Per bank write bursts -system.physmem.perBankRdBursts::13 25560 # Per bank write bursts -system.physmem.perBankRdBursts::14 25835 # Per bank write bursts -system.physmem.perBankRdBursts::15 25740 # Per bank write bursts -system.physmem.perBankWrBursts::0 7824 # Per bank write bursts -system.physmem.perBankWrBursts::1 7665 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7733 # Per bank write bursts -system.physmem.perBankWrBursts::4 7203 # Per bank write bursts -system.physmem.perBankWrBursts::5 7017 # Per bank write bursts -system.physmem.perBankWrBursts::6 6707 # Per bank write bursts -system.physmem.perBankWrBursts::7 6431 # Per bank write bursts -system.physmem.perBankWrBursts::8 7312 # Per bank write bursts -system.physmem.perBankWrBursts::9 6902 # Per bank write bursts -system.physmem.perBankWrBursts::10 7273 # Per bank write bursts -system.physmem.perBankWrBursts::11 6973 # Per bank write bursts -system.physmem.perBankWrBursts::12 7066 # Per bank write bursts -system.physmem.perBankWrBursts::13 8009 # Per bank write bursts -system.physmem.perBankWrBursts::14 7985 # Per bank write bursts -system.physmem.perBankWrBursts::15 7949 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303809 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25477 # Per bank write bursts +system.physmem.perBankRdBursts::1 25704 # Per bank write bursts +system.physmem.perBankRdBursts::2 25816 # Per bank write bursts +system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::4 25083 # Per bank write bursts +system.physmem.perBankRdBursts::5 25011 # Per bank write bursts +system.physmem.perBankRdBursts::6 24709 # Per bank write bursts +system.physmem.perBankRdBursts::7 24576 # Per bank write bursts +system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::9 25297 # Per bank write bursts +system.physmem.perBankRdBursts::10 25389 # Per bank write bursts +system.physmem.perBankRdBursts::11 25021 # Per bank write bursts +system.physmem.perBankRdBursts::12 24535 # Per bank write bursts +system.physmem.perBankRdBursts::13 25530 # Per bank write bursts +system.physmem.perBankRdBursts::14 25795 # Per bank write bursts +system.physmem.perBankRdBursts::15 25725 # Per bank write bursts +system.physmem.perBankWrBursts::0 7822 # Per bank write bursts +system.physmem.perBankWrBursts::1 7672 # Per bank write bursts +system.physmem.perBankWrBursts::2 8075 # Per bank write bursts +system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::4 7196 # Per bank write bursts +system.physmem.perBankWrBursts::5 7016 # Per bank write bursts +system.physmem.perBankWrBursts::6 6702 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts +system.physmem.perBankWrBursts::8 7310 # Per bank write bursts +system.physmem.perBankWrBursts::9 6908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7272 # Per bank write bursts +system.physmem.perBankWrBursts::11 7002 # Per bank write bursts +system.physmem.perBankWrBursts::12 7086 # Per bank write bursts +system.physmem.perBankWrBursts::13 7981 # Per bank write bursts +system.physmem.perBankWrBursts::14 7993 # Per bank write bursts +system.physmem.perBankWrBursts::15 7943 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 1906028705500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1906039923500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404835 # Read request sizes (log2) +system.physmem.readPktSize::6 404756 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118142 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 64 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118174 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,122 +148,124 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.304127 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.318074 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.802576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14872 23.08% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11053 17.15% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5024 7.80% 48.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3269 5.07% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2580 4.00% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1937 3.01% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4194 6.51% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1317 2.04% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20191 31.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64437 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.190700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2898.366893 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5309 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5312 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.236446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.912972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.909399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4665 87.82% 87.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.36% 88.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 18 0.34% 88.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 199 3.75% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.09% 92.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.47% 92.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 40 0.75% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 6 0.11% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.43% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.11% 94.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.08% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.17% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.38% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.45% 95.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 32 0.60% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 171 3.22% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 8 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5312 # Writes before turning the bus around for reads -system.physmem.totQLat 2653633250 # Total ticks spent queuing -system.physmem.totMemAccLat 10242320750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6556.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.283855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.156721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4666 88.00% 88.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.41% 88.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 20 0.38% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 187 3.53% 92.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.11% 92.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.47% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.81% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 93.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.15% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.34% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 6 0.11% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 18 0.34% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.47% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 27 0.51% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 172 3.24% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 7 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads +system.physmem.totQLat 2636864500 # Total ticks spent queuing +system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25306.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -273,71 +275,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.01 # Average write queue length when enqueuing -system.physmem.readRowHits 362859 # Number of row buffer hits during reads -system.physmem.writeRowHits 95554 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing +system.physmem.readRowHits 362818 # Number of row buffer hits during reads +system.physmem.writeRowHits 95583 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes -system.physmem.avgGap 3644574.63 # Average gap between requests -system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238049280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129888000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577136600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380058480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67941192465 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084023651750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278782921775 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912502 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803110214250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63646700000 # Time in different power states +system.physmem.avgGap 3644923.65 # Average gap between requests +system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.912661 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39278414500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249094440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135914625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579757400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385359120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124492945200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68603580630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083442617750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278889269165 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.968292 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802146960250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63646700000 # Time in different power states +system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.955290 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 40241682250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15005157 # Number of BP lookups -system.cpu.branchPred.condPredicted 13016352 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370563 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9544476 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5200630 # Number of BTB hits +system.cpu.branchPred.lookups 15009028 # Number of BP lookups +system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.488376 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807259 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30802 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807911 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31459 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242284 # DTB read hits -system.cpu.dtb.read_misses 17197 # DTB read misses +system.cpu.dtb.read_hits 9243045 # DTB read hits +system.cpu.dtb.read_misses 17179 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765766 # DTB read accesses -system.cpu.dtb.write_hits 6387071 # DTB write hits -system.cpu.dtb.write_misses 2294 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298411 # DTB write accesses -system.cpu.dtb.data_hits 15629355 # DTB hits -system.cpu.dtb.data_misses 19491 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064177 # DTB accesses -system.cpu.itb.fetch_hits 4015320 # ITB hits -system.cpu.itb.fetch_misses 6841 # ITB misses -system.cpu.itb.fetch_acv 659 # ITB acv -system.cpu.itb.fetch_accesses 4022161 # ITB accesses +system.cpu.dtb.read_accesses 765860 # DTB read accesses +system.cpu.dtb.write_hits 6388437 # DTB write hits +system.cpu.dtb.write_misses 2336 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298458 # DTB write accesses +system.cpu.dtb.data_hits 15631482 # DTB hits +system.cpu.dtb.data_misses 19515 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1064318 # DTB accesses +system.cpu.itb.fetch_hits 4012772 # ITB hits +system.cpu.itb.fetch_misses 6839 # ITB misses +system.cpu.itb.fetch_acv 666 # ITB acv +system.cpu.itb.fetch_accesses 4019611 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -350,39 +352,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 223168437 # number of cpu cycles simulated +system.cpu.numCycles 221706697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56132533 # Number of instructions committed -system.cpu.committedOps 56132533 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2504504 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5489 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590815720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.975741 # CPI: cycles per instruction -system.cpu.ipc 0.251525 # IPC: instructions per cycle +system.cpu.committedInsts 56145568 # Number of instructions committed +system.cpu.committedOps 56145568 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2506376 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5532 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590390516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.948784 # CPI: cycles per instruction +system.cpu.ipc 0.253243 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211546 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74811 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211538 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105910 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182756 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73444 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73444 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148923 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837436986000 96.40% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 81017000 0.00% 96.41% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 682412000 0.04% 96.44% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67836062500 3.56% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906036477500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981727 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693457 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814873 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -421,112 +423,112 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175591 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175581 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5129 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192481 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 192472 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.325047 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393243 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38636753000 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4528404000 0.24% 2.26% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862871310500 97.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 86394668 # Number of cycles that the object actually ticked -system.cpu.idleCycles 136773769 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395457 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.977331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13772866 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395969 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866169 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 121717500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.977331 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy +system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395430 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63663599 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63663599 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575814 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575814 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182834 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182834 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199026 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199026 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13390973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13390973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13390973 # number of overall hits -system.cpu.dcache.overall_hits::total 13390973 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201770 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201770 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575091 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575091 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17213 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17213 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776861 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776861 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776861 # number of overall misses -system.cpu.dcache.overall_misses::total 1776861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46961675000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46961675000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33993891500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33993891500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 235176000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 235176000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80955566500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80955566500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80955566500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80955566500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9016929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150905 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150905 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199026 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167834 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167834 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167834 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167834 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133279 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133279 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093497 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093497 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117147 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39077.090458 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39077.090458 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59110.456432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59110.456432 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13662.696799 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13662.696799 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45561.001395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45561.001395 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45561.001395 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63671171 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63671171 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576846 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182827 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182827 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13392891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392891 # number of overall hits +system.cpu.dcache.overall_hits::total 13392891 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201631 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201631 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses +system.cpu.dcache.overall_misses::total 1776836 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15169727 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15169727 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15169727 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15169727 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,129 +537,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838295 # number of writebacks -system.cpu.dcache.writebacks::total 838295 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127341 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127341 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270722 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270722 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838232 # number of writebacks +system.cpu.dcache.writebacks::total 838232 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127276 # number of ReadReq MSHR hits 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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,132 +817,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76630 # number of writebacks -system.cpu.l2cache.writebacks::total 76630 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16415 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16415 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272186 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272186 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16415 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388836 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405251 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16415 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388836 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405251 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9622 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9622 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16552 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16552 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1214500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1214500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13695042500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13695042500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1987583500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1987583500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30951837500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30951837500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1987583500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44646880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46634463500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1987583500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44646880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46634463500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364010000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364010000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931836500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931836500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3295846500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3295846500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383239 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383239 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011240 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249344 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249344 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141874 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011240 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278538 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141874 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71441.176471 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71441.176471 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117402.850407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117402.850407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121083.368870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121083.368870 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113715.758709 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113715.758709 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121083.368870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114821.878633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115075.505057 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196826.839827 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196826.839827 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200772.864269 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200772.864269 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199120.740696 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199120.740696 # average overall mshr uncacheable latency +system.cpu.l2cache.writebacks::writebacks 76662 # number of writebacks +system.cpu.l2cache.writebacks::total 76662 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388866 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405190 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388866 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405190 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5711775 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2855459 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304379 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304379 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1460498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559702 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1459802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 818923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091718 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4380147 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219373 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8599520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93467712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143047028 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236514740 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422969 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6151080 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000871 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029504 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4381906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8601216 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186932672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041565 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 329974237 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423215 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3296619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001032 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032108 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6145721 99.91% 99.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5359 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3293217 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3402 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6151080 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3707269500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 284383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3296619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5168164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2190955582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2191892463 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105716998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105680997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -948,81 +953,81 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51174 # Transaction distribution -system.iobus.trans_dist::WriteResp 51174 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5100 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7107 # Transaction distribution +system.iobus.trans_dist::ReadResp 7107 # Transaction distribution +system.iobus.trans_dist::WriteReq 51176 # Transaction distribution +system.iobus.trans_dist::WriteResp 51176 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116554 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44340 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705948 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4711000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215087245 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23482000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290787 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748608829000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290787 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080674 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080674 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748612865000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290814 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080676 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080676 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1036,14 +1041,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21943883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21943883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427163362 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427163362 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21943883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21943883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21943883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21943883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21944383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21944383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429292608 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5429292608 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21944383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21944383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21944383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21944383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1060,19 +1065,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126843.254335 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126843.254335 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130611.363159 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130611.363159 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126843.254335 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126843.254335 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126843.254335 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126846.144509 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126846.144509 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126846.144509 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.833333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1086,14 +1091,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13293883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13293883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3349563362 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3349563362 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13293883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13293883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13293883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13293883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13294383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351692608 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351692608 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13294383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13294383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13294383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13294383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1102,63 +1107,63 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76843.254335 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80611.363159 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80611.363159 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76843.254335 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76843.254335 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295688 # Transaction distribution -system.membus.trans_dist::WriteReq 9622 # Transaction distribution -system.membus.trans_dist::WriteResp 9622 # Transaction distribution -system.membus.trans_dist::Writeback 118142 # Transaction distribution -system.membus.trans_dist::CleanEvict 262192 # Transaction distribution -system.membus.trans_dist::UpgradeReq 159 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159 # Transaction distribution -system.membus.trans_dist::ReadExReq 116508 # Transaction distribution -system.membus.trans_dist::ReadExResp 116508 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288774 # Transaction distribution +system.membus.trans_dist::ReadReq 6934 # Transaction distribution +system.membus.trans_dist::ReadResp 295622 # Transaction distribution +system.membus.trans_dist::WriteReq 9624 # Transaction distribution +system.membus.trans_dist::WriteResp 9624 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118174 # Transaction distribution +system.membus.trans_dist::CleanEvict 262081 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::UpgradeResp 178 # Transaction distribution +system.membus.trans_dist::ReadExReq 116499 # Transaction distribution +system.membus.trans_dist::ReadExResp 116499 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288704 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1149038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148839 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1182174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181987 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306991 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30812800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30857140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306804 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854173 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33514868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33511901 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 844052 # Request fanout histogram +system.membus.snoop_fanout::samples 843925 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 844052 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843925 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 844052 # Request fanout histogram -system.membus.reqLayer0.occupancy 29776500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843925 # Request fanout histogram +system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319401645 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160603841 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69882415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index c3ff68c1f..4156232eb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.921764 # Number of seconds simulated -sim_ticks 1921763645000 # Number of ticks simulated -final_tick 1921763645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922762 # Number of seconds simulated +sim_ticks 1922761887500 # Number of ticks simulated +final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133766 # Simulator instruction rate (inst/s) -host_op_rate 133766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4532754153 # Simulator tick rate (ticks/s) -host_mem_usage 384052 # Number of bytes of host memory used -host_seconds 423.97 # Real time elapsed on the host -sim_insts 56713315 # Number of instructions simulated -sim_ops 56713315 # Number of ops (including micro ops) simulated +host_inst_rate 132982 # Simulator instruction rate (inst/s) +host_op_rate 132982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4507220686 # Simulator tick rate (ticks/s) +host_mem_usage 384024 # Number of bytes of host memory used +host_seconds 426.60 # Real time elapsed on the host +sim_insts 56729467 # Number of instructions simulated +sim_ops 56729467 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 874240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24774144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 869760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24778624 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 514944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 515712 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26267328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 874240 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26268096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 869760 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7875136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7875136 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387096 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::total 972800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7882944 # Number of bytes written to this memory +system.physmem.bytes_written::total 7882944 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387166 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8058 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123049 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123049 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 454915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12891358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 267954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13668345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 454915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53617 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 508533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4097869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4097869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4097869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 454915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12891358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 267954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17766214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410427 # Number of read requests accepted -system.physmem.writeReqs 123049 # Number of write requests accepted -system.physmem.readBursts 410427 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123049 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26259904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7874176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26267328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7875136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410439 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123171 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123171 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 452349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12886996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 268214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13661648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 452349 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53590 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4099803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4099803 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4099803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 452349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12886996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 268214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17761450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410439 # Number of read requests accepted +system.physmem.writeReqs 123171 # Number of write requests accepted +system.physmem.readBursts 410439 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123171 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7881088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26268096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7882944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 46661 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25500 # Per bank write bursts -system.physmem.perBankRdBursts::1 25969 # Per bank write bursts -system.physmem.perBankRdBursts::2 26011 # Per bank write bursts -system.physmem.perBankRdBursts::3 25727 # Per bank write bursts -system.physmem.perBankRdBursts::4 25508 # Per bank write bursts -system.physmem.perBankRdBursts::5 25811 # Per bank write bursts -system.physmem.perBankRdBursts::6 25519 # Per bank write bursts -system.physmem.perBankRdBursts::7 25160 # Per bank write bursts -system.physmem.perBankRdBursts::8 25451 # Per bank write bursts -system.physmem.perBankRdBursts::9 25839 # Per bank write bursts -system.physmem.perBankRdBursts::10 25659 # Per bank write bursts -system.physmem.perBankRdBursts::11 25030 # Per bank write bursts -system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25978 # Per bank write bursts -system.physmem.perBankRdBursts::14 25473 # Per bank write bursts -system.physmem.perBankRdBursts::15 25600 # Per bank write bursts -system.physmem.perBankWrBursts::0 8066 # Per bank write bursts -system.physmem.perBankWrBursts::1 8046 # Per bank write bursts -system.physmem.perBankWrBursts::2 8027 # Per bank write bursts -system.physmem.perBankWrBursts::3 7668 # Per bank write bursts -system.physmem.perBankWrBursts::4 7376 # Per bank write bursts -system.physmem.perBankWrBursts::5 7761 # Per bank write bursts -system.physmem.perBankWrBursts::6 7583 # Per bank write bursts -system.physmem.perBankWrBursts::7 6991 # Per bank write bursts -system.physmem.perBankWrBursts::8 7326 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 309493 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25497 # Per bank write bursts +system.physmem.perBankRdBursts::1 25956 # Per bank write bursts +system.physmem.perBankRdBursts::2 26004 # Per bank write bursts +system.physmem.perBankRdBursts::3 25724 # Per bank write bursts +system.physmem.perBankRdBursts::4 25504 # Per bank write bursts +system.physmem.perBankRdBursts::5 25939 # Per bank write bursts +system.physmem.perBankRdBursts::6 25634 # Per bank write bursts +system.physmem.perBankRdBursts::7 25247 # Per bank write bursts +system.physmem.perBankRdBursts::8 25446 # Per bank write bursts +system.physmem.perBankRdBursts::9 25836 # Per bank write bursts +system.physmem.perBankRdBursts::10 25660 # Per bank write bursts +system.physmem.perBankRdBursts::11 25037 # Per bank write bursts +system.physmem.perBankRdBursts::12 26054 # Per bank write bursts +system.physmem.perBankRdBursts::13 25864 # Per bank write bursts +system.physmem.perBankRdBursts::14 25329 # Per bank write bursts +system.physmem.perBankRdBursts::15 25594 # Per bank write bursts +system.physmem.perBankWrBursts::0 8072 # Per bank write bursts +system.physmem.perBankWrBursts::1 8040 # Per bank write bursts +system.physmem.perBankWrBursts::2 8032 # Per bank write bursts +system.physmem.perBankWrBursts::3 7672 # Per bank write bursts +system.physmem.perBankWrBursts::4 7388 # Per bank write bursts +system.physmem.perBankWrBursts::5 7843 # Per bank write bursts +system.physmem.perBankWrBursts::6 7702 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7329 # Per bank write bursts system.physmem.perBankWrBursts::9 7600 # Per bank write bursts -system.physmem.perBankWrBursts::10 7532 # Per bank write bursts -system.physmem.perBankWrBursts::11 7413 # Per bank write bursts -system.physmem.perBankWrBursts::12 7962 # Per bank write bursts -system.physmem.perBankWrBursts::13 8267 # Per bank write bursts -system.physmem.perBankWrBursts::14 7722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7538 # Per bank write bursts +system.physmem.perBankWrBursts::11 7420 # Per bank write bursts +system.physmem.perBankWrBursts::12 7961 # Per bank write bursts +system.physmem.perBankWrBursts::13 8153 # Per bank write bursts +system.physmem.perBankWrBursts::14 7615 # Per bank write bursts system.physmem.perBankWrBursts::15 7694 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1921759329500 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 1922757529500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410427 # Read request sizes (log2) +system.physmem.readPktSize::6 410439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123049 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123171 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,199 +158,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6385 # What write queue length does an incoming req see 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# What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 96 # What write queue length does an incoming req see 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accessed per row activation -system.physmem.bytesPerActivate::128-255 11344 17.37% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5465 8.37% 48.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2873 4.40% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2572 3.94% 56.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1636 2.51% 59.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3782 5.79% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1204 1.84% 67.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21501 32.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65305 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5548 # Reads before turning the bus around for writes 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see 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40.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5448 8.34% 48.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2603 3.98% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1650 2.53% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3828 5.86% 65.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21460 32.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65327 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5556 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5548 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.176280 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.947134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.868875 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4772 86.01% 86.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 155 2.79% 88.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.34% 89.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 186 3.35% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 8 0.14% 92.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.38% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.74% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 18 0.32% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.49% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.36% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.43% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 29 0.52% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 158 2.85% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5559 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5559 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.151826 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921629 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.873132 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4760 85.63% 85.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 185 3.33% 88.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.47% 89.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 178 3.20% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.11% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.31% 93.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 0.81% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.27% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.36% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.16% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 23 0.41% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 22 0.40% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.61% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 160 2.88% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.04% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.05% 99.32% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.07% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 14 0.25% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.20% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5548 # Writes before turning the bus around for reads -system.physmem.totQLat 4465229000 # Total ticks spent queuing -system.physmem.totMemAccLat 12158560250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10882.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads +system.physmem.totQLat 4492977750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186571500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10949.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29632.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29699.80 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.67 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.31 # Average write queue length when enqueuing -system.physmem.readRowHits 369445 # Number of row buffer hits during reads -system.physmem.writeRowHits 98595 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes -system.physmem.avgGap 3602335.12 # Average gap between requests +system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing +system.physmem.readRowHits 369433 # Number of row buffer hits during reads +system.physmem.writeRowHits 98707 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes +system.physmem.avgGap 3603301.16 # Average gap between requests system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245919240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134182125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1600599000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 398636640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63180018945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097637063000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1288716655350 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.590642 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1825809460500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64171900000 # Time in different power states +system.physmem_0.actEnergy 247242240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134904000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63449600445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097998572000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289419261125 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.608464 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1826410636250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31782207000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32144391250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247786560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135201000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1599826800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398623680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125520236400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62993858085 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1097800353750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288695886275 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.579840 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1826084104500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64171900000 # Time in different power states +system.physmem_1.actEnergy 246629880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134569875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62800369875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1098568064250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289329850760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.561968 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1827364141250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31507549250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31190872500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16172722 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14147320 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 315974 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10263532 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5327857 # Number of BTB hits +system.cpu0.branchPred.lookups 16164803 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 313974 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10204663 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5324382 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.910561 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 805529 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17788 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 52.175971 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 806868 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17359 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9178933 # DTB read hits -system.cpu0.dtb.read_misses 32423 # DTB read misses -system.cpu0.dtb.read_acv 530 # DTB read access violations -system.cpu0.dtb.read_accesses 683199 # DTB read accesses -system.cpu0.dtb.write_hits 5878949 # DTB write hits -system.cpu0.dtb.write_misses 7260 # DTB write misses -system.cpu0.dtb.write_acv 384 # DTB write access violations -system.cpu0.dtb.write_accesses 235377 # DTB write accesses -system.cpu0.dtb.data_hits 15057882 # DTB hits -system.cpu0.dtb.data_misses 39683 # DTB misses -system.cpu0.dtb.data_acv 914 # DTB access violations -system.cpu0.dtb.data_accesses 918576 # DTB accesses -system.cpu0.itb.fetch_hits 1433805 # ITB hits -system.cpu0.itb.fetch_misses 20098 # ITB misses -system.cpu0.itb.fetch_acv 602 # ITB acv -system.cpu0.itb.fetch_accesses 1453903 # ITB accesses +system.cpu0.dtb.read_hits 9175640 # DTB read hits +system.cpu0.dtb.read_misses 32141 # DTB read misses +system.cpu0.dtb.read_acv 535 # DTB read access violations +system.cpu0.dtb.read_accesses 683139 # DTB read accesses +system.cpu0.dtb.write_hits 5880520 # DTB write hits +system.cpu0.dtb.write_misses 7287 # DTB write misses +system.cpu0.dtb.write_acv 388 # DTB write access violations +system.cpu0.dtb.write_accesses 235457 # DTB write accesses +system.cpu0.dtb.data_hits 15056160 # DTB hits +system.cpu0.dtb.data_misses 39428 # DTB misses +system.cpu0.dtb.data_acv 923 # DTB access violations +system.cpu0.dtb.data_accesses 918596 # DTB accesses +system.cpu0.itb.fetch_hits 1432352 # ITB hits +system.cpu0.itb.fetch_misses 20066 # ITB misses +system.cpu0.itb.fetch_acv 603 # ITB acv +system.cpu0.itb.fetch_accesses 1452418 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -363,256 +363,255 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 146988157 # number of cpu cycles simulated +system.cpu0.numCycles 147492353 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26434329 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70323281 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16172722 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6133386 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112438747 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1062414 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 847 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 925731 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 462393 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 403 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8125656 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 231201 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 140823886 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.499370 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.736005 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26474453 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 112661982 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 929577 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 229144 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 141086791 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.498241 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.734215 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 127673480 90.66% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 835079 0.59% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1817427 1.29% 92.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 778983 0.55% 93.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2600412 1.85% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 568090 0.40% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 652333 0.46% 95.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 824353 0.59% 96.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5073729 3.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 127943316 90.68% 90.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2595829 1.84% 94.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 572321 0.41% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 651682 0.46% 95.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 825551 0.59% 96.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 140823886 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.110027 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478428 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21407057 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108692435 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8462793 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1765937 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 495663 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 515138 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35957 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61540375 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 109013 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 495663 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22243524 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77757616 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19856258 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9307175 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11163648 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59419645 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 199110 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2023904 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 235068 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7176378 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39704161 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72277966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72138515 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129817 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34987460 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4716693 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1464722 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211632 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12540163 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9262921 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6150917 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1355884 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 997025 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52994830 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1876718 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52216371 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52644 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6477091 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2861227 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1292062 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 140823886 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.370792 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088351 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 141086791 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21397284 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108971969 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61523411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22231623 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77943277 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19950150 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11164601 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59421423 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 224739 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7186522 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39708138 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72284773 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72145342 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4728766 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9257817 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53010072 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52220775 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6501427 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2875305 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 141086791 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.370132 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.087511 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 119350315 84.75% 84.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9307127 6.61% 91.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3871720 2.75% 94.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2724493 1.93% 96.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2821208 2.00% 98.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1374944 0.98% 99.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 898986 0.64% 99.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 361887 0.26% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 113206 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 119618317 84.78% 84.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9300566 6.59% 91.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3865351 2.74% 94.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2821391 2.00% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1375833 0.98% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 902269 0.64% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 140823886 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 141086791 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 180499 18.19% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 473486 47.73% 65.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 338115 34.08% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 471621 47.60% 65.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35829212 68.62% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56563 0.11% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28580 0.05% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35835166 68.62% 68.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9526937 18.25% 87.04% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5949680 11.39% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819736 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52216371 # Type of FU issued -system.cpu0.iq.rate 0.355242 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 992101 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019000 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 245730281 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61098362 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50826597 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 571091 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267903 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262355 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52896880 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307812 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 579556 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52220775 # Type of FU issued +system.cpu0.iq.rate 0.354058 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 245999962 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61137242 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52900144 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1070231 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2809 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17956 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 496898 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1065241 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3900 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17685 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 500436 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18718 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 406168 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 408208 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 495663 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74229287 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1063310 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58247929 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 119878 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9262921 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6150917 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1658630 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39535 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 822687 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17956 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 156887 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351474 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 508361 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51713827 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9234499 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 502543 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58259516 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 116557 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39988 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 817674 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17685 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 153306 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 351909 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 503478 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3376381 # number of nop insts executed -system.cpu0.iew.exec_refs 15134335 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8213447 # Number of branches executed -system.cpu0.iew.exec_stores 5899836 # Number of stores executed -system.cpu0.iew.exec_rate 0.351823 # Inst execution rate -system.cpu0.iew.wb_sent 51204042 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51088952 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26321891 # num instructions producing a value -system.cpu0.iew.wb_consumers 36458900 # num instructions consuming a value +system.cpu0.iew.exec_nop 3373289 # number of nop insts executed +system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8216790 # Number of branches executed +system.cpu0.iew.exec_stores 5901411 # Number of stores executed +system.cpu0.iew.exec_rate 0.350644 # Inst execution rate +system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26334207 # num instructions producing a value +system.cpu0.iew.wb_consumers 36473944 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.347572 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.721961 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6803374 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584656 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 464905 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 139620670 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.367725 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.257359 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6824839 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 139882457 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.366962 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.256012 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 121488072 87.01% 87.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7189020 5.15% 92.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3942453 2.82% 94.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2051651 1.47% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1610967 1.15% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 576073 0.41% 98.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 437348 0.31% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 435843 0.31% 98.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1889243 1.35% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 121750983 87.04% 87.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7187616 5.14% 92.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2051217 1.47% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1611428 1.15% 97.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 139620670 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51342045 # Number of instructions committed -system.cpu0.commit.committedOps 51342045 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 139882457 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51331530 # Number of instructions committed +system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13846709 # Number of memory references committed -system.cpu0.commit.loads 8192690 # Number of loads committed -system.cpu0.commit.membars 198882 # Number of memory barriers committed -system.cpu0.commit.branches 7762297 # Number of branches committed -system.cpu0.commit.fp_insts 259271 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47551840 # Number of committed integer instructions. -system.cpu0.commit.function_calls 657143 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2951360 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33433980 65.12% 70.87% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55376 0.11% 70.98% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28117 0.05% 71.03% # Class of committed instruction +system.cpu0.commit.refs 13845248 # Number of memory references committed +system.cpu0.commit.loads 8192576 # Number of loads committed +system.cpu0.commit.membars 198790 # Number of memory barriers committed +system.cpu0.commit.branches 7761926 # Number of branches committed +system.cpu0.commit.fp_insts 259003 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47542487 # Number of committed integer instructions. +system.cpu0.commit.function_calls 656882 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2950502 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33426097 65.12% 70.87% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55327 0.11% 70.97% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.97% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28109 0.05% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction @@ -638,324 +637,326 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8391572 16.34% 87.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5660021 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819736 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8391366 16.35% 87.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5658677 11.02% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51342045 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1889243 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 195675599 # The number of ROB reads -system.cpu0.rob.rob_writes 117488366 # The number of ROB writes -system.cpu0.timesIdled 519286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6164271 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3696539134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48394452 # Number of Instructions Simulated -system.cpu0.committedOps 48394452 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.037294 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.037294 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329240 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67992315 # number of integer regfile reads -system.cpu0.int_regfile_writes 36972661 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128885 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130381 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1712039 # number of misc regfile reads -system.cpu0.misc_regfile_writes 819549 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1282830 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.258957 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10531989 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283342 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.206689 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.258957 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988787 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988787 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 195950193 # The number of ROB reads +system.cpu0.rob.rob_writes 117511428 # The number of ROB writes +system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6405562 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48384795 # Number of Instructions Simulated +system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.048320 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.048320 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.328050 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.328050 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67995096 # number of integer regfile reads +system.cpu0.int_regfile_writes 36974255 # number of integer regfile writes +system.cpu0.fp_regfile_reads 128760 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130249 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads +system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1282737 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.160384 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160384 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56925383 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56925383 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6490454 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6490454 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3680062 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3680062 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162917 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162917 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187619 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187619 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10170516 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10170516 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10170516 # number of overall hits -system.cpu0.dcache.overall_hits::total 10170516 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1594902 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1594902 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1768783 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1768783 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20957 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20957 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2842 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2842 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3363685 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3363685 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3363685 # number of overall misses -system.cpu0.dcache.overall_misses::total 3363685 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54779472000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54779472000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114120076576 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114120076576 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 388638000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 388638000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44723000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44723000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 168899548576 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 168899548576 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 168899548576 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 168899548576 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8085356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8085356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5448845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5448845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183874 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183874 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13534201 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13534201 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13534201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13534201 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197258 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197258 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324616 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324616 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113975 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113975 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014922 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014922 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248532 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248532 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34346.606876 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34346.606876 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64518.980890 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64518.980890 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18544.543589 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18544.543589 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15736.453202 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15736.453202 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50212.653259 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50212.653259 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50212.653259 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6977235 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 18493 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 125 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.354674 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 147.944000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 56891628 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56891628 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6483780 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6483780 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3678701 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3678701 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162607 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 162607 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187520 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 187520 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10162481 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10162481 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10162481 # number of overall hits +system.cpu0.dcache.overall_hits::total 10162481 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1594725 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1594725 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1768883 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1768883 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21044 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21044 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2856 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2856 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3363608 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses +system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54837998000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 54837998000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114303059042 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 389087500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45510000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45510000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 169141057042 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 169141057042 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8078505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8078505 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5447584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5447584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183651 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183651 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 190376 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13526089 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13526089 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13526089 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13526089 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197403 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197403 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324710 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324710 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114587 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114587 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6995611 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 14546 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 119540 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 103 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.521089 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 141.223301 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 756224 # number of writebacks -system.cpu0.dcache.writebacks::total 756224 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579464 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 579464 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502811 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1502811 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5193 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5193 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082275 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2082275 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082275 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2082275 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015438 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1015438 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265972 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 265972 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15764 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15764 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2841 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2841 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1281410 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281410 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1281410 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 756067 # number of writebacks +system.cpu0.dcache.writebacks::total 756067 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579442 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 579442 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502906 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1502906 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5209 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5209 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082348 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2082348 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082348 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2082348 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015283 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1015283 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265977 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 265977 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15835 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15835 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2856 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2856 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281260 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1281260 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281260 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1281260 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10125 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10125 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17170 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17170 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43462270000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43462270000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18192812239 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18192812239 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186019000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186019000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41882000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41882000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61655082239 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61655082239 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61655082239 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61655082239 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1482526500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1482526500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2174117500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2174117500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3656644000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3656644000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048813 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048813 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085733 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014916 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014916 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094679 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094679 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094679 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42801.500436 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42801.500436 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68401.231103 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68401.231103 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11800.241056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11800.241056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14741.992256 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14741.992256 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48115.031285 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210436.692690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210436.692690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214727.654321 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214727.654321 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212967.035527 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212967.035527 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43466083500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43466083500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18236016784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18236016784 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61702100284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61702100284 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61702100284 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61702100284 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563410000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563410000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3862426000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3862426000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048825 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086223 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086223 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 909478 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.072720 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7170024 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909987 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.879260 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42291813500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.072720 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992330 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992330 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 908501 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7168696 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909010 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.886267 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.069795 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992324 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992324 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9035950 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9035950 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7170024 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7170024 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7170024 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7170024 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7170024 # number of overall hits -system.cpu0.icache.overall_hits::total 7170024 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 955631 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 955631 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 955631 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 955631 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 955631 # number of overall misses -system.cpu0.icache.overall_misses::total 955631 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14538250986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14538250986 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14538250986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14538250986 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14538250986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14538250986 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8125655 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8125655 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8125655 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8125655 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8125655 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8125655 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117607 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117607 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117607 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117607 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117607 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117607 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15213.247567 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15213.247567 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15213.247567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15213.247567 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15213.247567 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8860 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9032627 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9032627 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7168696 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7168696 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7168696 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7168696 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7168696 # number of overall hits +system.cpu0.icache.overall_hits::total 7168696 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 954611 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 954611 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 954611 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses +system.cpu0.icache.overall_misses::total 954611 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14636609987 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14636609987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14636609987 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14636609987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14636609987 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14636609987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8123307 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8123307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8123307 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117515 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117515 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15332.538581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15332.538581 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 285 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 31.087719 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.834532 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45336 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45336 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45336 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45336 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45336 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45336 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 910295 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 910295 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 910295 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 910295 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 910295 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 910295 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12844771491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12844771491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12844771491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12844771491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12844771491 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12844771491 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112027 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112027 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112027 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112027 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14110.559204 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14110.559204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14110.559204 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 908501 # number of writebacks +system.cpu0.icache.writebacks::total 908501 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45291 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45291 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45291 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45291 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45291 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45291 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909320 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 909320 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12934939493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12934939493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12934939493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12934939493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12934939493 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12934939493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3566695 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3123821 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 62988 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1777720 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 839763 # Number of BTB hits +system.cpu1.branchPred.lookups 3578846 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63586 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2063930 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 845641 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 47.238204 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 169438 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5003 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 40.972368 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 169933 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4992 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1880373 # DTB read hits -system.cpu1.dtb.read_misses 9576 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 286028 # DTB read accesses -system.cpu1.dtb.write_hits 1172828 # DTB write hits -system.cpu1.dtb.write_misses 2034 # DTB write misses +system.cpu1.dtb.read_hits 1885255 # DTB read hits +system.cpu1.dtb.read_misses 9531 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 285831 # DTB read accesses +system.cpu1.dtb.write_hits 1175917 # DTB write hits +system.cpu1.dtb.write_misses 2028 # DTB write misses system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 108538 # DTB write accesses -system.cpu1.dtb.data_hits 3053201 # DTB hits -system.cpu1.dtb.data_misses 11610 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 394566 # DTB accesses -system.cpu1.itb.fetch_hits 516269 # ITB hits -system.cpu1.itb.fetch_misses 4737 # ITB misses -system.cpu1.itb.fetch_acv 64 # ITB acv -system.cpu1.itb.fetch_accesses 521006 # ITB accesses +system.cpu1.dtb.write_accesses 108552 # DTB write accesses +system.cpu1.dtb.data_hits 3061172 # DTB hits +system.cpu1.dtb.data_misses 11559 # DTB misses +system.cpu1.dtb.data_acv 40 # DTB access violations +system.cpu1.dtb.data_accesses 394383 # DTB accesses +system.cpu1.itb.fetch_hits 516958 # ITB hits +system.cpu1.itb.fetch_misses 4674 # ITB misses +system.cpu1.itb.fetch_acv 66 # ITB acv +system.cpu1.itb.fetch_accesses 521632 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -968,255 +969,255 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14959639 # number of cpu cycles simulated +system.cpu1.numCycles 15151136 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6140426 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13703075 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3566695 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1009201 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7602996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 256204 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 312 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 176452 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 62292 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1530550 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50498 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14135722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.969393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.379564 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6180932 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13745317 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3578846 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1015574 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7699604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 257606 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 14 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 173727 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 62622 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1537985 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 51060 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14270827 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.963176 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.372632 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11742806 83.07% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 150793 1.07% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 240174 1.70% 85.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 177797 1.26% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 306821 2.17% 89.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 121463 0.86% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138409 0.98% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 186182 1.32% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1071277 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11867377 83.16% 83.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 153441 1.08% 84.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 242213 1.70% 85.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 178756 1.25% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 307848 2.16% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 121777 0.85% 90.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138851 0.97% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 186713 1.31% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1073851 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14135722 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.238421 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.916003 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5035823 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7049483 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1732735 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 195750 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 121930 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 104865 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6244 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11127162 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19879 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 121930 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5174702 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 499846 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5538858 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1790125 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1010259 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10570144 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4276 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 68050 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20115 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 516529 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6943229 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12595828 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12537363 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52773 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5938747 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1004482 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 436817 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40607 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1800852 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1926573 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1243636 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 225182 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 130261 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9311043 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502453 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9112092 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20417 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1494632 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 673391 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 369352 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14135722 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644615 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.367603 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14270827 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.236210 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.907214 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5071818 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7138589 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1741534 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 196274 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 122611 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 106199 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6268 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11163667 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19967 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 122611 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5211151 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 520290 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5613443 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1798962 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1004368 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10604371 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4257 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 67823 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18974 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 511038 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6965041 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12634725 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12576141 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52884 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5956129 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1008912 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 437815 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 40748 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1803693 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1932664 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1246799 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 224198 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 128085 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9340268 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 503829 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9138713 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20420 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1499424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 677663 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 370337 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14270827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.640377 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.363961 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10331729 73.09% 73.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1677616 11.87% 84.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 710014 5.02% 89.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 492260 3.48% 93.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 443396 3.14% 96.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 237464 1.68% 98.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 151784 1.07% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65612 0.46% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25847 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10455091 73.26% 73.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1683189 11.79% 85.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 712225 4.99% 90.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 493511 3.46% 93.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 444759 3.12% 96.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 238311 1.67% 98.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 152079 1.07% 99.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65820 0.46% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25842 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14135722 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14270827 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 23101 9.34% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 135152 54.66% 64.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 89008 36.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22910 9.24% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 135436 54.62% 63.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 89607 36.14% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5665609 62.18% 62.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16110 0.18% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10836 0.12% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1960524 21.52% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1194738 13.11% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 258998 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5683316 62.19% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16216 0.18% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10845 0.12% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.52% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.54% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1965659 21.51% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1197875 13.11% 97.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 259525 2.84% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9112092 # Type of FU issued -system.cpu1.iq.rate 0.609112 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 247261 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027135 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32423377 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11214835 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8782259 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 204207 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 97217 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 94699 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9246642 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 109193 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94025 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9138713 # Type of FU issued +system.cpu1.iq.rate 0.603170 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 247953 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027132 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 32611679 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11249940 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8808383 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 204947 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 97488 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 94992 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9273516 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 109632 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94173 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 261324 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4031 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 123982 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 262201 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 474 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4003 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 124065 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 65647 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.cacheBlocked 65383 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 121930 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 296920 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 166801 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10329862 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 27466 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1926573 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1243636 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 455903 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4091 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 161850 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4031 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28253 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 94223 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 122476 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8997942 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1896570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 114150 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 122611 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 306675 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 177978 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10362316 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 27137 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1932664 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1246799 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 457137 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4115 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 173001 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4003 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 29001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 94231 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 123232 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9024161 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1901420 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 114552 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 516366 # number of nop insts executed -system.cpu1.iew.exec_refs 3077114 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1335580 # Number of branches executed -system.cpu1.iew.exec_stores 1180544 # Number of stores executed -system.cpu1.iew.exec_rate 0.601481 # Inst execution rate -system.cpu1.iew.wb_sent 8905860 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8876958 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4235192 # num instructions producing a value -system.cpu1.iew.wb_consumers 6022422 # num instructions consuming a value +system.cpu1.iew.exec_nop 518219 # number of nop insts executed +system.cpu1.iew.exec_refs 3085060 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1341299 # Number of branches executed +system.cpu1.iew.exec_stores 1183640 # Number of stores executed +system.cpu1.iew.exec_rate 0.595610 # Inst execution rate +system.cpu1.iew.wb_sent 8932335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8903375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4245423 # num instructions producing a value +system.cpu1.iew.wb_consumers 6036438 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.593394 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703237 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.587637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.703299 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1521482 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133101 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 111980 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13855601 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.631015 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.609308 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1526496 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 133492 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 112683 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13989586 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626917 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.604217 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10693520 77.18% 77.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1462734 10.56% 87.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 528018 3.81% 91.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 318233 2.30% 93.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 242012 1.75% 95.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 100894 0.73% 96.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 90931 0.66% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102553 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 316706 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10816267 77.32% 77.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1467149 10.49% 87.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 531154 3.80% 91.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 320114 2.29% 93.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 241905 1.73% 95.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 101551 0.73% 96.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 91287 0.65% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 103861 0.74% 97.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316298 2.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13855601 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8743092 # Number of instructions committed -system.cpu1.commit.committedOps 8743092 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13989586 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8770307 # Number of instructions committed +system.cpu1.commit.committedOps 8770307 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2784903 # Number of memory references committed -system.cpu1.commit.loads 1665249 # Number of loads committed -system.cpu1.commit.membars 42287 # Number of memory barriers committed -system.cpu1.commit.branches 1247450 # Number of branches committed -system.cpu1.commit.fp_insts 93039 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8096711 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139604 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 427747 4.89% 4.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5200103 59.48% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 15945 0.18% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.55% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10829 0.12% 64.68% # Class of committed instruction +system.cpu1.commit.refs 2793197 # Number of memory references committed +system.cpu1.commit.loads 1670463 # Number of loads committed +system.cpu1.commit.membars 42427 # Number of memory barriers committed +system.cpu1.commit.branches 1252873 # Number of branches committed +system.cpu1.commit.fp_insts 93374 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8120952 # Number of committed integer instructions. +system.cpu1.commit.function_calls 139980 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 429153 4.89% 4.89% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5216835 59.48% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16050 0.18% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10839 0.12% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction @@ -1242,290 +1243,292 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1707536 19.53% 84.23% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1120175 12.81% 97.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 258998 2.96% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1712890 19.53% 84.23% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1123256 12.81% 97.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 259525 2.96% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8743092 # Class of committed instruction -system.cpu1.commit.bw_lim_events 316706 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23719092 # The number of ROB reads -system.cpu1.rob.rob_writes 20805392 # The number of ROB writes -system.cpu1.timesIdled 122607 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 823917 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3827854089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8318863 # Number of Instructions Simulated -system.cpu1.committedOps 8318863 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.798279 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.798279 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556087 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556087 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11586341 # number of integer regfile reads -system.cpu1.int_regfile_writes 6325577 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52057 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51356 # number of floating regfile writes -system.cpu1.misc_regfile_reads 501983 # number of misc regfile reads -system.cpu1.misc_regfile_writes 207801 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 98586 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.617617 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2459541 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 98896 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.869975 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 61777830500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.617617 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.950425 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.950425 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11508888 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11508888 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1514240 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1514240 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 887339 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 887339 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 31145 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 31145 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29838 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29838 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2401579 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2401579 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2401579 # number of overall hits -system.cpu1.dcache.overall_hits::total 2401579 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 186104 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 186104 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 193582 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 193582 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4934 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4934 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2994 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2994 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 379686 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 379686 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 379686 # number of overall misses -system.cpu1.dcache.overall_misses::total 379686 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2502679500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2502679500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9084892318 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9084892318 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46731500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46731500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 48320000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 48320000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11587571818 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11587571818 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11587571818 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11587571818 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1700344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1700344 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1080921 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1080921 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 36079 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 36079 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2781265 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2781265 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2781265 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2781265 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109451 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109451 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179090 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.179090 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136755 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.091192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.091192 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136516 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.136516 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136516 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.136516 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13447.746959 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13447.746959 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46930.460053 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 46930.460053 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9471.321443 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9471.321443 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16138.944556 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16138.944556 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30518.828237 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30518.828237 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30518.828237 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 537858 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1114 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 16003 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.609823 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 123.777778 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8770307 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316298 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 23885701 # The number of ROB reads +system.cpu1.rob.rob_writes 20870962 # The number of ROB writes +system.cpu1.timesIdled 125875 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 880309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3829642661 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8344672 # Number of Instructions Simulated +system.cpu1.committedOps 8344672 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.815666 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.815666 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550762 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550762 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11618114 # number of integer regfile reads +system.cpu1.int_regfile_writes 6343189 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52190 # number of floating regfile reads +system.cpu1.fp_regfile_writes 51516 # number of floating regfile writes +system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads +system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 98962 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.970751 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970751 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.603516 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11541624 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11541624 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1517477 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1517477 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 889696 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 889696 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32286 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 32286 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29965 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 29965 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2407173 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2407173 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2407173 # number of overall hits +system.cpu1.dcache.overall_hits::total 2407173 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 194181 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 194181 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4996 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4996 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2988 # number of StoreCondReq misses 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13525.431900 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9527.922338 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9527.922338 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 543818 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1735 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 16052 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.878520 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 173.500000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 63787 # number of writebacks -system.cpu1.dcache.writebacks::total 63787 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 112960 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 112960 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 158580 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 158580 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 454 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 271540 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 271540 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 271540 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 271540 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73144 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 73144 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35002 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 35002 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4480 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4480 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2993 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2993 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 108146 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 108146 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 108146 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 108146 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 64059 # number of writebacks +system.cpu1.dcache.writebacks::total 64059 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 113306 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 113306 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 159042 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 159042 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 272348 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 272348 # number of demand (read+write) MSHR hits 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MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 108508 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 108508 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 108508 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2930 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2930 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3080 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3080 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 925590000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 925590000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553309551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1553309551 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37834000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37834000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45327000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45327000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2478899551 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2478899551 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2478899551 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2478899551 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 28469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 28469500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 648479500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 648479500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676949000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676949000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043017 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043017 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032382 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032382 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124172 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124172 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.091161 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.091161 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038884 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038884 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038884 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12654.353057 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12654.353057 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44377.737015 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44377.737015 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8445.089286 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8445.089286 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15144.336786 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15144.336786 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22921.786760 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189796.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189796.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221324.061433 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 221324.061433 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 219788.636364 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 219788.636364 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2931 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2931 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3081 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3081 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 931066500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 931066500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1566203053 # number of WriteReq MSHR miss cycles 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+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032420 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121319 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121319 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090675 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090675 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038919 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038919 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8510.944064 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8510.944064 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682 # average overall mshr uncacheable latency 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occupancy +system.cpu1.icache.tags.replacements 223833 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.351638 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1306354 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 224343 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.823021 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1896743746500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.351638 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912796 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.912796 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1753949 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1753949 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1300089 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1300089 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1300089 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1300089 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1300089 # number of overall hits -system.cpu1.icache.overall_hits::total 1300089 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 230461 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 230461 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 230461 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 230461 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 230461 # number of overall misses -system.cpu1.icache.overall_misses::total 230461 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3280299500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3280299500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3280299500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3280299500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3280299500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3280299500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1530550 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1530550 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1530550 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1530550 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1530550 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1530550 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150574 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.150574 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150574 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.150574 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150574 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.150574 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14233.642569 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14233.642569 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14233.642569 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14233.642569 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14233.642569 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 780 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1762389 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1762389 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1306354 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1306354 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1306354 # number of demand (read+write) hits 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(read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3331435000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3331435000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3331435000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1537985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1537985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1537985 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1537985 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1537985 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1537985 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150607 # miss rate for ReadReq accesses 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average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 764 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.571429 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.105263 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7062 # number of ReadReq MSHR hits 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-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2948315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2948315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2948315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2948315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2948315500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2948315500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.145960 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145960 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.145960 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13197.532218 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13197.532218 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13197.532218 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 223833 # number of writebacks +system.cpu1.icache.writebacks::total 223833 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7227 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7227 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7227 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7227 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7227 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7227 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 224404 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 224404 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 224404 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 224404 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 224404 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 224404 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2997413500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2997413500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2997413500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2997413500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2997413500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2997413500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145908 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.145908 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145908 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.145908 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13357.219568 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1541,9 +1544,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7371 # Transaction distribution system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54607 # Transaction distribution -system.iobus.trans_dist::WriteResp 54607 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11900 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54609 # Transaction distribution +system.iobus.trans_dist::WriteResp 54609 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1555,11 +1558,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40500 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1571,49 +1574,49 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73826 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11255000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 448000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14420500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 217500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 87000 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 131500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215099741 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215061495 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27445000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.507802 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.507724 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725999022000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.507802 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031738 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031738 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981783000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.507724 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031733 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031733 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1627,14 +1630,14 @@ system.iocache.demand_misses::tsunami.ide 176 # n system.iocache.demand_misses::total 176 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 176 # number of overall misses system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22249883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22249883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427997858 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427997858 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22249883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22249883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22249883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22249883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22155383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22155383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5431231112 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5431231112 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22155383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22155383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22155383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22155383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1651,19 +1654,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126419.789773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126419.789773 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.446332 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130631.446332 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126419.789773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126419.789773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126419.789773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125882.857955 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125882.857955 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125882.857955 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 15.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.411765 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1677,14 +1680,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 176 system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13449883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13449883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350397858 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350397858 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13449883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13449883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13449883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13449883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13355383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13355383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353631112 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3353631112 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13355383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13355383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13355383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13355383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1693,195 +1696,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76419.789773 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.446332 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.446332 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76419.789773 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76419.789773 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 344948 # number of replacements -system.l2c.tags.tagsinuse 65190.787367 # Cycle average of tags in use -system.l2c.tags.total_refs 3990905 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410112 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.731256 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 11174884000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53006.163408 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5332.464187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6575.010887 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 209.732945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 67.415939 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.808810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081367 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.100327 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.replacements 345304 # number of replacements +system.l2c.tags.tagsinuse 65190.216948 # Cycle average of tags in use +system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53120.456427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5260.305215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6531.960123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.099670 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001049 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994724 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1750 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6246 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5661 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1730 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6285 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6556 # Occupied blocks per task id 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-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938372 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.810089 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.898016 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.893709 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.945263 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.919872 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424719 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.243604 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.406588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013474 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270321 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012303 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254274 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015012 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.302911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007208 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.083951 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71779.934688 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71691.391941 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71754.807692 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71285.194175 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71790.645880 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71548.780488 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129416.394357 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 148234.089047 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130545.015195 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124263.473250 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114195.362953 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130834.344660 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114245.434061 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124054.498207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118700.129721 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126036.645963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 146474.036337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119456.998636 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197936.692690 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177296.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197506.393329 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203210.666667 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209194.197952 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204553.581003 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201046.709377 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 207640.746753 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202049.654321 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941457 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.817982 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.902229 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.891720 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946352 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.918890 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425138 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242973 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406842 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013412 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270311 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012327 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254204 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163770 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163770 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 296388 # Transaction distribution -system.membus.trans_dist::WriteReq 13055 # Transaction distribution -system.membus.trans_dist::WriteResp 13055 # Transaction distribution -system.membus.trans_dist::Writeback 123049 # Transaction distribution -system.membus.trans_dist::CleanEvict 262884 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10279 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5759 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5112 # Transaction distribution -system.membus.trans_dist::ReadExReq 122086 # Transaction distribution -system.membus.trans_dist::ReadExResp 121678 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289268 # Transaction distribution -system.membus.trans_dist::BadAddressError 75 # Transaction distribution +system.membus.trans_dist::ReadResp 296301 # Transaction distribution +system.membus.trans_dist::WriteReq 13057 # Transaction distribution +system.membus.trans_dist::WriteResp 13057 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123171 # Transaction distribution +system.membus.trans_dist::CleanEvict 262771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10335 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5768 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5173 # Transaction distribution +system.membus.trans_dist::ReadExReq 122191 # Transaction distribution +system.membus.trans_dist::ReadExResp 121777 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289182 # Transaction distribution +system.membus.trans_dist::BadAddressError 76 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1227712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1227883 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1352540 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73826 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31484224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31558050 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1352711 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73842 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31492800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31566642 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34216290 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11781 # Total snoops (count) -system.membus.snoop_fanout::samples 875308 # Request fanout histogram +system.membus.pkt_size::total 34224882 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11791 # Total snoops (count) +system.membus.snoop_fanout::samples 875399 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875308 # Request fanout histogram -system.membus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875399 # Request fanout histogram +system.membus.reqLayer0.occupancy 36670000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1356119148 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1357207403 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 92500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187698407 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187694355 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69909650 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5063061 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2531463 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 338644 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1334 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1266 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5063738 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2531809 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 339719 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1340 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2238892 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13055 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 943078 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1635745 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10313 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5834 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16147 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301580 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301580 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1133694 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098094 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2239104 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13057 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13057 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 943311 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 859282 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 775827 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10329 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16173 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301707 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301707 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1133724 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098277 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2554026 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3861302 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 573119 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 309440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7297887 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58240320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130381048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 14295680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10315306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213232354 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462162 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5511701 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.123436 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.329209 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2546826 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3860959 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 579596 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 310532 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7297913 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 104800384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130368640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22732288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10357298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 268258610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462469 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2998699 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.119628 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.324813 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4831850 87.67% 87.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 679365 12.33% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 482 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2640250 88.05% 88.05% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 358173 11.94% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 274 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5511701 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3368234918 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2998699 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4501023919 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1366825726 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1365634171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1954242307 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1954807358 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 335428339 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 338746615 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 167784154 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 168528157 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2172,32 +2180,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6535 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184475 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65083 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.20% 41.79% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 184433 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65060 40.50% 40.50% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.20% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93355 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160682 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64077 49.21% 49.21% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 93335 58.10% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 160640 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64056 49.21% 49.21% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.48% 50.79% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63891 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130212 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864797723000 97.04% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61900500 0.00% 97.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 553477500 0.03% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 85562000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56264153500 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1921762816500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984543 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865607975500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56422873000 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684388 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810371 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684309 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810327 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed @@ -2233,56 +2241,56 @@ system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3533 2.09% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3530 2.09% 2.26% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153850 90.93% 93.22% # number of callpals executed -system.cpu0.kern.callpal::rdps 6345 3.75% 96.97% # number of callpals executed +system.cpu0.kern.callpal::swpipl 153808 90.93% 93.22% # number of callpals executed +system.cpu0.kern.callpal::rdps 6346 3.75% 96.97% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rti 4587 2.71% 99.69% # number of callpals executed +system.cpu0.kern.callpal::rti 4586 2.71% 99.69% # number of callpals executed system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169199 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7137 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1347 # number of protection mode switches +system.cpu0.kern.callpal::total 169154 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7135 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1348 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1346 -system.cpu0.kern.mode_good::user 1347 +system.cpu0.kern.mode_good::kernel 1347 +system.cpu0.kern.mode_good::user 1348 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188595 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188788 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317421 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1919561135500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2201673000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317694 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1920558467500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2202571000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3534 # number of times the context was actually changed +system.cpu0.kern.swap_context 3531 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55164 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17245 36.53% 36.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.08% 40.61% # number of times we switched to this ipl +system.cpu1.kern.inst.hwrei 55289 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17293 36.54% 36.54% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 4.07% 40.61% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27750 58.79% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47204 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16874 47.30% 47.30% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.40% 52.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.80% 53.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16590 46.51% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35673 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874997277000 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 538569500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 135298500 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45735704500 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1921406849500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978487 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_count::31 27821 58.79% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 47324 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16920 47.31% 47.31% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 5.39% 52.69% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.79% 53.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16636 46.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 35766 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875921374000 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 562894500 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 139598000 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45773010000 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1922396876500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978431 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.597838 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.755720 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.597966 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.755769 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed @@ -2301,32 +2309,32 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1056 2.16% 2.55% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1060 2.16% 2.55% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 42024 86.04% 88.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2414 4.94% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.56% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 2970 6.08% 99.65% # number of callpals executed +system.cpu1.kern.callpal::swpipl 42140 86.06% 88.63% # number of callpals executed +system.cpu1.kern.callpal::rdps 2415 4.93% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.57% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.58% # number of callpals executed +system.cpu1.kern.callpal::rti 2973 6.07% 99.65% # number of callpals executed system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48843 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1253 # number of protection mode switches -system.cpu1.kern.mode_switch::user 392 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2414 # number of protection mode switches +system.cpu1.kern.callpal::total 48967 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1257 # number of protection mode switches +system.cpu1.kern.mode_switch::user 391 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2415 # number of protection mode switches system.cpu1.kern.mode_good::kernel 600 -system.cpu1.kern.mode_good::user 392 -system.cpu1.kern.mode_good::idle 208 -system.cpu1.kern.mode_switch_good::kernel 0.478851 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::user 391 +system.cpu1.kern.mode_good::idle 209 +system.cpu1.kern.mode_switch_good::kernel 0.477327 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086164 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.295639 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4354098000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 702561000 0.04% 0.26% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1916032066000 99.74% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1057 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086542 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.295348 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4412319000 0.23% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 702202000 0.04% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1916962357500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1061 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3a598fe00..30a63d50f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.875745 # Number of seconds simulated -sim_ticks 1875745192000 # Number of ticks simulated -final_tick 1875745192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875760 # Number of seconds simulated +sim_ticks 1875760362000 # Number of ticks simulated +final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131976 # Simulator instruction rate (inst/s) -host_op_rate 131976 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4672432142 # Simulator tick rate (ticks/s) -host_mem_usage 378172 # Number of bytes of host memory used -host_seconds 401.45 # Real time elapsed on the host -sim_insts 52981683 # Number of instructions simulated -sim_ops 52981683 # Number of ops (including micro ops) simulated +host_inst_rate 133605 # Simulator instruction rate (inst/s) +host_op_rate 133605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4730094094 # Simulator tick rate (ticks/s) +host_mem_usage 378388 # Number of bytes of host memory used +host_seconds 396.56 # Real time elapsed on the host +sim_insts 52982087 # Number of instructions simulated +sim_ops 52982087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 962112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25844608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7523648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7523648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15033 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388774 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25840256 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403822 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 512923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13264881 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403754 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117574 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13778315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512923 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4011018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4011018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4011018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13264881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17789333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403822 # Number of read requests accepted -system.physmem.writeReqs 117557 # Number of write requests accepted -system.physmem.readBursts 403822 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117557 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836864 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7522176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25844608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7523648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403754 # Number of read requests accepted +system.physmem.writeReqs 117574 # Number of write requests accepted +system.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25633 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25565 # Per bank write bursts -system.physmem.perBankRdBursts::3 25492 # Per bank write bursts -system.physmem.perBankRdBursts::4 25387 # Per bank write bursts -system.physmem.perBankRdBursts::5 24737 # Per bank write bursts -system.physmem.perBankRdBursts::6 24937 # Per bank write bursts -system.physmem.perBankRdBursts::7 25080 # Per bank write bursts -system.physmem.perBankRdBursts::8 24933 # Per bank write bursts -system.physmem.perBankRdBursts::9 25019 # Per bank write bursts -system.physmem.perBankRdBursts::10 25561 # Per bank write bursts -system.physmem.perBankRdBursts::11 24878 # Per bank write bursts -system.physmem.perBankRdBursts::12 24487 # Per bank write bursts -system.physmem.perBankRdBursts::13 25242 # Per bank write bursts -system.physmem.perBankRdBursts::14 25745 # Per bank write bursts -system.physmem.perBankRdBursts::15 25584 # Per bank write bursts -system.physmem.perBankWrBursts::0 7946 # Per bank write bursts -system.physmem.perBankWrBursts::1 7515 # Per bank write bursts -system.physmem.perBankWrBursts::2 7960 # Per bank write bursts -system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7330 # Per bank write bursts -system.physmem.perBankWrBursts::5 6676 # Per bank write bursts -system.physmem.perBankWrBursts::6 6762 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25610 # Per bank write bursts +system.physmem.perBankRdBursts::1 25424 # Per bank write bursts +system.physmem.perBankRdBursts::2 25555 # Per bank write bursts +system.physmem.perBankRdBursts::3 25501 # Per bank write bursts +system.physmem.perBankRdBursts::4 25379 # Per bank write bursts +system.physmem.perBankRdBursts::5 24724 # Per bank write bursts +system.physmem.perBankRdBursts::6 24941 # Per bank write bursts +system.physmem.perBankRdBursts::7 25082 # Per bank write bursts +system.physmem.perBankRdBursts::8 24938 # Per bank write bursts +system.physmem.perBankRdBursts::9 25020 # Per bank write bursts +system.physmem.perBankRdBursts::10 25562 # Per bank write bursts +system.physmem.perBankRdBursts::11 24881 # Per bank write bursts +system.physmem.perBankRdBursts::12 24459 # Per bank write bursts +system.physmem.perBankRdBursts::13 25275 # Per bank write bursts +system.physmem.perBankRdBursts::14 25708 # Per bank write bursts +system.physmem.perBankRdBursts::15 25569 # Per bank write bursts +system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankWrBursts::1 7523 # Per bank write bursts +system.physmem.perBankWrBursts::2 7959 # Per bank write bursts +system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::4 7322 # Per bank write bursts +system.physmem.perBankWrBursts::5 6662 # Per bank write bursts +system.physmem.perBankWrBursts::6 6770 # Per bank write bursts system.physmem.perBankWrBursts::7 6719 # Per bank write bursts -system.physmem.perBankWrBursts::8 7146 # Per bank write bursts -system.physmem.perBankWrBursts::9 6702 # Per bank write bursts -system.physmem.perBankWrBursts::10 7407 # Per bank write bursts -system.physmem.perBankWrBursts::11 6970 # Per bank write bursts -system.physmem.perBankWrBursts::12 7148 # Per bank write bursts -system.physmem.perBankWrBursts::13 7861 # Per bank write bursts -system.physmem.perBankWrBursts::14 8061 # Per bank write bursts -system.physmem.perBankWrBursts::15 7814 # Per bank write bursts +system.physmem.perBankWrBursts::8 7147 # Per bank write bursts +system.physmem.perBankWrBursts::9 6703 # Per bank write bursts +system.physmem.perBankWrBursts::10 7409 # Per bank write bursts +system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 7893 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1875739913500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1875755162500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403822 # Read request sizes (log2) +system.physmem.readPktSize::6 403754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117557 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117574 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,123 +148,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.822002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.292900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.615573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13686 22.02% 22.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10474 16.86% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4974 8.00% 46.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2759 4.44% 51.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2428 3.91% 55.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1656 2.66% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3743 6.02% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1149 1.85% 65.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21272 34.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.350259 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2906.647984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5216 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5219 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5219 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.520406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.103659 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.296995 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4441 85.09% 85.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 172 3.30% 88.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 18 0.34% 88.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 180 3.45% 92.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.08% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.40% 92.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.69% 93.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.04% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.23% 93.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 25 0.48% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.08% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 11 0.21% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.08% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.38% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.56% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 29 0.56% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 164 3.14% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.06% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5219 # Writes before turning the bus around for reads -system.physmem.totQLat 4201414500 # Total ticks spent queuing -system.physmem.totMemAccLat 11770808250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10407.24 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.237934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 330.496904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.905259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13738 22.09% 22.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10541 16.95% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2730 4.39% 51.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2467 3.97% 55.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 2.56% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3726 5.99% 63.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1160 1.86% 65.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21290 34.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62202 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2240.859567 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads +system.physmem.totQLat 4177241750 # Total ticks spent queuing +system.physmem.totMemAccLat 11745266750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10349.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29157.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29099.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s @@ -273,72 +276,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing -system.physmem.readRowHits 363834 # Number of row buffer hits during reads -system.physmem.writeRowHits 95259 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing +system.physmem.readRowHits 363742 # Number of row buffer hits during reads +system.physmem.writeRowHits 95234 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.03 # Row buffer hit rate for writes -system.physmem.avgGap 3597651.45 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577565600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378594000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61659983700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071355704750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257846562020 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.587193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782093997750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62635040000 # Time in different power states +system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes +system.physmem.avgGap 3598032.64 # Average gap between requests +system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232553160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126889125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61473435525 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071528687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257832501770 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.574130 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782381530500 # Time in different power states +system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31009992250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30737512000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236499480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129042375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571255400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383026320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 122514138240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61488464715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071506168250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257828594780 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.577609 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782344410500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62635040000 # Time in different power states +system.physmem_1.actEnergy 237693960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129694125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61441070355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071557085750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257834900030 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.575404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782427454500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30760024500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30691601750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17977610 # Number of BP lookups -system.cpu.branchPred.condPredicted 15676073 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11479744 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5859077 # Number of BTB hits +system.cpu.branchPred.lookups 17943789 # Number of BP lookups +system.cpu.branchPred.condPredicted 15652252 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11526734 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5853564 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.038394 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 912903 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21206 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10250294 # DTB read hits -system.cpu.dtb.read_misses 41452 # DTB read misses -system.cpu.dtb.read_acv 531 # DTB read access violations -system.cpu.dtb.read_accesses 965916 # DTB read accesses -system.cpu.dtb.write_hits 6642949 # DTB write hits -system.cpu.dtb.write_misses 9723 # DTB write misses -system.cpu.dtb.write_acv 398 # DTB write access violations -system.cpu.dtb.write_accesses 342082 # DTB write accesses -system.cpu.dtb.data_hits 16893243 # DTB hits -system.cpu.dtb.data_misses 51175 # DTB misses -system.cpu.dtb.data_acv 929 # DTB access violations -system.cpu.dtb.data_accesses 1307998 # DTB accesses -system.cpu.itb.fetch_hits 1771116 # ITB hits -system.cpu.itb.fetch_misses 27251 # ITB misses -system.cpu.itb.fetch_acv 655 # ITB acv -system.cpu.itb.fetch_accesses 1798367 # ITB accesses +system.cpu.dtb.read_hits 10250861 # DTB read hits +system.cpu.dtb.read_misses 41155 # DTB read misses +system.cpu.dtb.read_acv 533 # DTB read access violations +system.cpu.dtb.read_accesses 965519 # DTB read accesses +system.cpu.dtb.write_hits 6643163 # DTB write hits +system.cpu.dtb.write_misses 9679 # DTB write misses +system.cpu.dtb.write_acv 405 # DTB write access violations +system.cpu.dtb.write_accesses 341919 # DTB write accesses +system.cpu.dtb.data_hits 16894024 # DTB hits +system.cpu.dtb.data_misses 50834 # DTB misses +system.cpu.dtb.data_acv 938 # DTB access violations +system.cpu.dtb.data_accesses 1307438 # DTB accesses +system.cpu.itb.fetch_hits 1771509 # ITB hits +system.cpu.itb.fetch_misses 27218 # ITB misses +system.cpu.itb.fetch_acv 651 # ITB acv +system.cpu.itb.fetch_accesses 1798727 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,136 +354,136 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 153807945 # number of cpu cycles simulated +system.cpu.numCycles 154312476 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29589963 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78082078 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17977610 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6771980 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115315004 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1233982 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2306 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1247451 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 470617 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 460 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8997640 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 271780 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147272342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.530188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.786973 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29589684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78040473 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17943789 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6765691 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115537778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8990852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147506364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.529065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.785295 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132738967 90.13% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 930397 0.63% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1956016 1.33% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 907001 0.62% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772714 1.88% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 615474 0.42% 95.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 727209 0.49% 95.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009346 0.69% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5615218 3.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132982346 90.15% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905254 0.61% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772061 1.88% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 613974 0.42% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009556 0.68% 96.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5613005 3.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147272342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116883 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.507660 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24002291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111345789 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9440793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1908530 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 574938 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 581140 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42414 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68062016 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132549 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 574938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24926396 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78168566 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21593766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10339140 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11669534 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65637228 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204564 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2092706 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 229144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7400964 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43743792 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79597549 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79416724 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168373 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181235 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5562549 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689699 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239435 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13568621 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10378795 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6951631 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1513940 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1098335 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58473138 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2139162 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57493462 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7630612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3411321 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1477941 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147272342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.390389 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.114131 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 147506364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23997501 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111590886 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9436404 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1909016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68051611 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24921357 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78408678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21682628 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10334897 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11586246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65629261 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2094496 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 230878 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7314004 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43742271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79592757 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79412100 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5560685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13566674 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58467931 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2138048 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57495227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7623887 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147506364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.389781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113625 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123663895 83.97% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10186331 6.92% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4292878 2.91% 93.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3019293 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3081041 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1488323 1.01% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011420 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404091 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125070 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123908569 84.00% 84.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10178941 6.90% 90.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4283785 2.90% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3020720 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3080791 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1492273 1.01% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011784 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404685 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124816 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147272342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147506364 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210189 18.68% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 539111 47.92% 66.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375615 33.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210138 18.65% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 541379 48.04% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375311 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39049173 67.92% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61879 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39050505 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued @@ -508,97 +511,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10660314 18.54% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723536 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949085 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57493462 # Type of FU issued -system.cpu.iq.rate 0.373800 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1124915 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019566 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262728196 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67925320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55850502 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336604 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329051 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58228243 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382848 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 635438 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57495227 # Type of FU issued +system.cpu.iq.rate 0.372590 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1126828 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262968198 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67912529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55849103 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58232052 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1285740 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3115 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19427 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573353 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18203 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 457581 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 460620 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 574938 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74485816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1122121 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64302959 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140159 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10378795 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6951631 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1891041 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 44126 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 874685 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19427 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 179710 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409314 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 589024 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56907888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10319427 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 585573 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74664170 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1189821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64295080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890560 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 943025 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56909008 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3690659 # number of nop insts executed -system.cpu.iew.exec_refs 16987198 # number of memory reference insts executed -system.cpu.iew.exec_branches 8973802 # Number of branches executed -system.cpu.iew.exec_stores 6667771 # Number of stores executed -system.cpu.iew.exec_rate 0.369993 # Inst execution rate -system.cpu.iew.wb_sent 56315493 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56179553 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28757989 # num instructions producing a value -system.cpu.iew.wb_consumers 39945326 # num instructions consuming a value +system.cpu.iew.exec_nop 3689101 # number of nop insts executed +system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed +system.cpu.iew.exec_branches 8974026 # Number of branches executed +system.cpu.iew.exec_stores 6667947 # Number of stores executed +system.cpu.iew.exec_rate 0.368791 # Inst execution rate +system.cpu.iew.wb_sent 56315336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56178054 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756989 # num instructions producing a value +system.cpu.iew.wb_consumers 39942344 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.365258 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719934 # average fanout of values written-back +system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719962 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8014233 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661221 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 539644 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145865842 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.385097 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.287358 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8005033 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146103821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286210 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126089885 86.44% 86.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7851403 5.38% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272179 2.93% 94.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235192 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1747101 1.20% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615790 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 475839 0.33% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 478833 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2099620 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126321778 86.46% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7855301 5.38% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4275066 2.93% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2236699 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745226 1.19% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615725 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 478401 0.33% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 477554 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2098071 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145865842 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172516 # Number of instructions committed -system.cpu.commit.committedOps 56172516 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146103821 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172911 # Number of instructions committed +system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471333 # Number of memory references committed -system.cpu.commit.loads 9093055 # Number of loads committed -system.cpu.commit.membars 226352 # Number of memory barriers committed -system.cpu.commit.branches 8440752 # Number of branches committed +system.cpu.commit.refs 15471230 # Number of memory references committed +system.cpu.commit.loads 9092979 # Number of loads committed +system.cpu.commit.membars 226353 # Number of memory barriers committed +system.cpu.commit.branches 8440862 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021823 # Number of committed integer instructions. -system.cpu.commit.function_calls 740586 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198106 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36219281 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60683 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52022252 # Number of committed integer instructions. +system.cpu.commit.function_calls 740590 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -626,36 +629,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319407 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384233 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949085 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56172516 # Class of committed instruction -system.cpu.commit.bw_lim_events 2099620 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207703277 # The number of ROB reads -system.cpu.rob.rob_writes 129775597 # The number of ROB writes -system.cpu.timesIdled 576321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6535603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597682440 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52981683 # Number of Instructions Simulated -system.cpu.committedOps 52981683 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.903040 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.903040 # CPI: Total CPI of All Threads -system.cpu.ipc 0.344466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.344466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74566924 # number of integer regfile reads -system.cpu.int_regfile_writes 40527176 # number of integer regfile writes -system.cpu.fp_regfile_reads 167101 # number of floating regfile reads -system.cpu.fp_regfile_writes 167535 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985778 # number of misc regfile reads -system.cpu.misc_regfile_writes 939467 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1402095 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992786 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11832212 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402607 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.435871 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36097500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992786 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction +system.cpu.commit.bw_lim_events 2098071 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207934044 # The number of ROB reads +system.cpu.rob.rob_writes 129754094 # The number of ROB writes +system.cpu.timesIdled 581359 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6806112 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52982087 # Number of Instructions Simulated +system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.912541 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74569026 # number of integer regfile reads +system.cpu.int_regfile_writes 40527111 # number of integer regfile writes +system.cpu.fp_regfile_reads 166982 # number of floating regfile reads +system.cpu.fp_regfile_writes 167538 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads +system.cpu.misc_regfile_writes 939432 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1401817 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -663,380 +666,386 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63847952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63847952 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7239475 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7239475 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4190405 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4190405 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186164 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186164 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215734 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215734 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11429880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11429880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11429880 # number of overall hits -system.cpu.dcache.overall_hits::total 11429880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1798792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1798792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957410 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957410 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23330 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23330 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3756202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3756202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3756202 # number of overall misses -system.cpu.dcache.overall_misses::total 3756202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57198715500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57198715500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116967363039 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116967363039 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 446591500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 446591500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 850000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 850000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174166078539 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174166078539 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174166078539 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174166078539 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9038267 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9038267 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147815 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147815 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209494 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209494 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215760 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215760 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15186082 # number of demand (read+write) accesses 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-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 32692.307692 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 32692.307692 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46367.601779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46367.601779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46367.601779 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7156530 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5457 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133923 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437647 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 188.172414 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215725 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11429044 # number of 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# average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59669.079344 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46343.936364 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.936364 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46343.936364 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7142845 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 134029 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.293280 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841276 # number of writebacks -system.cpu.dcache.writebacks::total 841276 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 704782 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 704782 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 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WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18046 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18046 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384771 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384771 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384771 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384771 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 841132 # number of writebacks +system.cpu.dcache.writebacks::total 841132 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits 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ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44554526500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 44554526500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18468782348 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18468782348 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 228783500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 228783500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 824000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 824000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63023308848 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63023308848 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63023308848 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63023308848 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450570000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450570000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2036143500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2036143500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486713500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486713500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086141 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086141 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091187 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091187 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091187 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40725.885961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40725.885961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63518.774347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63518.774347 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12677.795633 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12677.795633 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 31692.307692 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 31692.307692 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45511.719156 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45511.719156 # average overall mshr miss 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16294267486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16294267486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8997638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8997638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8997638 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997638 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8997638 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997638 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121514 # miss rate for demand accesses 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number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373491482 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16373491482 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16373491482 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16373491482 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16373491482 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16373491482 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8990849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8990849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8990849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8990849 # number of demand (read+write) accesses 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access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53508 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53508 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53508 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53508 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53508 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53508 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039828 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1039828 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1039828 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1039828 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1039828 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1039828 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14359854493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14359854493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14359854493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14359854493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14359854493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14359854493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115567 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.115567 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115567 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.115567 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13809.836332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13809.836332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13809.836332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13809.836332 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1036098 # number of writebacks +system.cpu.icache.writebacks::total 1036098 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53275 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53275 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53275 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53275 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53275 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53275 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036979 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1036979 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1036979 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1036979 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1036979 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1036979 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14441674990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14441674990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14441674990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14441674990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14441674990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14441674990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115337 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.115337 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115337 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.115337 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13926.680280 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13926.680280 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13926.680280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13926.680280 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338309 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65280.236813 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4173910 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403476 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.344878 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 9183094000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53277.296150 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.937838 # Average occupied blocks per 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+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 14973 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 273860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 273860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 14973 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389371 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404344 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 14973 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389371 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404344 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7022000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7022000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 499500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 499500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14977801000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14977801000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1868614000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1868614000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31274184500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31274184500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1868614000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46251985500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 48120599500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1868614000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46251985500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 48120599500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363945000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363945000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925742500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925742500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289687500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289687500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.765625 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.765625 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.269231 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.269231 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383087 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383087 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248696 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248696 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277585 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165588 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71653.061224 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71653.061224 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71357.142857 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71357.142857 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129665.581633 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129665.581633 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124292.536916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124292.536916 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114199.793686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114199.793686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124292.536916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118787.941166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118992.580366 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196817.460317 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196817.460317 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.977079 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.977079 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199037.239835 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199037.239835 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 7246500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 7246500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 500000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 500000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14946254500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14946254500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1866612000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1866612000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31277372000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31277372000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1866612000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46223626500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48090238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1866612000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46223626500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 48090238500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443206500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443206500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2043789000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2043789000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486995500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486995500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.776923 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.776923 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.241379 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.241379 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383169 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383169 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248749 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248749 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165778 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014443 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165778 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71747.524752 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71747.524752 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71428.571429 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71428.571429 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129392.477773 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.477773 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124665.197355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124665.197355 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114209.347842 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114209.347842 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124665.197355 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118713.582932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118933.973300 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208254.906205 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208254.906205 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210975.042352 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210975.042352 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4883718 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2441508 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4877464 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438379 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2147995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2144933 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 958852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1860290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 154 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301527 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301527 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039828 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3117755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4239617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7357372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66528832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143662708 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210191540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422209 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5321984 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032932 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7347980 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276257140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422449 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2878054 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5316206 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5778 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2874297 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5321984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296198000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2878054 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4329025000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1561216545 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556715501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115809899 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115441305 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1235,45 +1241,45 @@ system.iobus.pkt_size_system.bridge.master::total 44148 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 444000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 219000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 132500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215079498 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215036503 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249403 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725991887000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249403 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078088 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078088 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1287,14 +1293,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21903883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21903883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427983615 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427983615 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21903883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21903883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21903883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21903883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21806383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1311,19 +1317,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126612.040462 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126612.040462 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130631.103557 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130631.103557 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126612.040462 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126612.040462 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126612.040462 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1337,14 +1343,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13253883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13253883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350383615 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350383615 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13253883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13253883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13253883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13253883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13156383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1353,64 +1359,64 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76612.040462 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80631.103557 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80631.103557 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76612.040462 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76612.040462 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295909 # Transaction distribution +system.membus.trans_dist::ReadResp 295855 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117557 # Transaction distribution -system.membus.trans_dist::CleanEvict 261789 # Transaction distribution -system.membus.trans_dist::UpgradeReq 334 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117574 # Transaction distribution +system.membus.trans_dist::CleanEvict 261706 # Transaction distribution +system.membus.trans_dist::UpgradeReq 351 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 341 # Transaction distribution -system.membus.trans_dist::ReadExReq 115275 # Transaction distribution -system.membus.trans_dist::ReadExResp 115275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289062 # Transaction distribution -system.membus.trans_dist::BadAddressError 83 # Transaction distribution +system.membus.trans_dist::UpgradeResp 358 # Transaction distribution +system.membus.trans_dist::ReadExReq 115261 # Transaction distribution +system.membus.trans_dist::ReadExResp 115261 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution +system.membus.trans_dist::BadAddressError 81 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146388 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754676 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33412404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842283 # Request fanout histogram +system.membus.snoop_fanout::samples 842165 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842283 # Request fanout histogram -system.membus.reqLayer0.occupancy 28662500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842165 # Request fanout histogram +system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313672631 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314315898 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139416664 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139099889 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69895667 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1444,28 +1450,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74668 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182251 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73301 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73301 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148613 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818203066500 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62700500 0.00% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 538036000 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 56940563000 3.04% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1875744366000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818035067000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57098083500 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815430 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1504,7 +1510,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175134 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1513,20 +1519,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191979 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.callpal::total 191970 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29901576500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2896080000 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842946701500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 8f58e32e6..54688b406 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841615 # Number of seconds simulated -sim_ticks 1841615117500 # Number of ticks simulated -final_tick 1841615117500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.843590 # Number of seconds simulated +sim_ticks 1843589966000 # Number of ticks simulated +final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220643 # Simulator instruction rate (inst/s) -host_op_rate 220643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5550131764 # Simulator tick rate (ticks/s) -host_mem_usage 377148 # Number of bytes of host memory used -host_seconds 331.81 # Real time elapsed on the host -sim_insts 73212541 # Number of instructions simulated -sim_ops 73212541 # Number of ops (including micro ops) simulated +host_inst_rate 220463 # Simulator instruction rate (inst/s) +host_op_rate 220463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5656183181 # Simulator tick rate (ticks/s) +host_mem_usage 378132 # Number of bytes of host memory used +host_seconds 325.94 # Real time elapsed on the host +sim_insts 71858146 # Number of instructions simulated +sim_ops 71858146 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 495296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20794752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 141504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1560960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 279936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25786880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 495296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 141504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 279936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 916736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7468864 # Number of bytes written to this memory -system.physmem.bytes_written::total 7468864 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7739 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 324918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24390 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39273 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 142016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 270784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 911552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7470272 # Number of bytes written to this memory +system.physmem.bytes_written::total 7470272 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 268947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 11291584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 76837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 847604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 152006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1364819 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116723 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14002318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 268947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 76837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 152006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 497789 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4055605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4055605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 268947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 11291584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 76837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 847604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 152006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1364819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 146879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494444 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052025 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18057923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 70263 # Number of read requests accepted -system.physmem.writeReqs 43985 # Number of write requests accepted -system.physmem.readBursts 70263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 43985 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 4495872 # Total number of bytes read from DRAM +system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 69838 # Number of read requests accepted +system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2813888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 4496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2815040 # Total written bytes from the system interface side +system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17213 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4359 # Per bank write bursts -system.physmem.perBankRdBursts::1 4121 # Per bank write bursts -system.physmem.perBankRdBursts::2 4307 # Per bank write bursts -system.physmem.perBankRdBursts::3 4650 # Per bank write bursts -system.physmem.perBankRdBursts::4 3946 # Per bank write bursts -system.physmem.perBankRdBursts::5 4779 # Per bank write bursts -system.physmem.perBankRdBursts::6 4258 # Per bank write bursts -system.physmem.perBankRdBursts::7 4152 # Per bank write bursts -system.physmem.perBankRdBursts::8 4721 # Per bank write bursts -system.physmem.perBankRdBursts::9 4422 # Per bank write bursts -system.physmem.perBankRdBursts::10 4675 # Per bank write bursts -system.physmem.perBankRdBursts::11 4103 # Per bank write bursts -system.physmem.perBankRdBursts::12 4083 # Per bank write bursts -system.physmem.perBankRdBursts::13 4580 # Per bank write bursts -system.physmem.perBankRdBursts::14 4738 # Per bank write bursts -system.physmem.perBankRdBursts::15 4354 # Per bank write bursts -system.physmem.perBankWrBursts::0 2794 # Per bank write bursts -system.physmem.perBankWrBursts::1 2415 # Per bank write bursts -system.physmem.perBankWrBursts::2 2758 # Per bank write bursts -system.physmem.perBankWrBursts::3 3153 # Per bank write bursts -system.physmem.perBankWrBursts::4 2458 # Per bank write bursts -system.physmem.perBankWrBursts::5 2922 # Per bank write bursts -system.physmem.perBankWrBursts::6 2626 # Per bank write bursts -system.physmem.perBankWrBursts::7 2424 # Per bank write bursts -system.physmem.perBankWrBursts::8 3273 # Per bank write bursts -system.physmem.perBankWrBursts::9 2590 # Per bank write bursts -system.physmem.perBankWrBursts::10 2930 # Per bank write bursts -system.physmem.perBankWrBursts::11 2458 # Per bank write bursts -system.physmem.perBankWrBursts::12 2433 # Per bank write bursts -system.physmem.perBankWrBursts::13 2833 # Per bank write bursts -system.physmem.perBankWrBursts::14 3042 # Per bank write bursts -system.physmem.perBankWrBursts::15 2858 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4348 # Per bank write bursts +system.physmem.perBankRdBursts::1 4129 # Per bank write bursts +system.physmem.perBankRdBursts::2 4337 # Per bank write bursts +system.physmem.perBankRdBursts::3 4598 # Per bank write bursts +system.physmem.perBankRdBursts::4 3888 # Per bank write bursts +system.physmem.perBankRdBursts::5 4661 # Per bank write bursts +system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::7 4148 # Per bank write bursts +system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::9 4417 # Per bank write bursts +system.physmem.perBankRdBursts::10 4595 # Per bank write bursts +system.physmem.perBankRdBursts::11 4084 # Per bank write bursts +system.physmem.perBankRdBursts::12 4057 # Per bank write bursts +system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::14 4705 # Per bank write bursts +system.physmem.perBankRdBursts::15 4338 # Per bank write bursts +system.physmem.perBankWrBursts::0 2799 # Per bank write bursts +system.physmem.perBankWrBursts::1 2436 # Per bank write bursts +system.physmem.perBankWrBursts::2 2776 # Per bank write bursts +system.physmem.perBankWrBursts::3 2976 # Per bank write bursts +system.physmem.perBankWrBursts::4 2273 # Per bank write bursts +system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::6 2480 # Per bank write bursts +system.physmem.perBankWrBursts::7 2289 # Per bank write bursts +system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::9 2510 # Per bank write bursts +system.physmem.perBankWrBursts::10 2861 # Per bank write bursts +system.physmem.perBankWrBursts::11 2441 # Per bank write bursts +system.physmem.perBankWrBursts::12 2439 # Per bank write bursts +system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::14 3033 # Per bank write bursts +system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1840603135000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1842578089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 70263 # Read request sizes (log2) +system.physmem.readPktSize::6 69838 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 43985 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 42816 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,195 +153,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an 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queue length does an incoming req see -system.physmem.wrQLenPdf::23 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req 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req see -system.physmem.wrQLenPdf::47 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.690812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.028180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 371.433574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7252 35.78% 35.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4628 22.84% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1637 8.08% 66.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 935 4.61% 71.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 704 3.47% 74.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 532 2.63% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 447 2.21% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 402 1.98% 81.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3729 18.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20266 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.186342 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 837.829732 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1887 99.89% 99.89% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see 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req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1889 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.275278 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.746797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.833114 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.80% 1.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.48% 2.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.11% 2.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.11% 2.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1521 80.52% 83.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 2.70% 85.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.48% 86.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 92 4.87% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.11% 91.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 5 0.26% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.90% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.64% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.42% 93.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.11% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.11% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.21% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 10 0.53% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.85% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 73 3.86% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.05% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 6 0.32% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.11% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1889 # Writes before turning the bus around for reads -system.physmem.totQLat 866118250 # Total ticks spent queuing -system.physmem.totMemAccLat 2183268250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 351240000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12329.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads +system.physmem.totQLat 871326250 # Total ticks spent queuing +system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31079.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.98 # Average write queue length when enqueuing -system.physmem.readRowHits 59265 # Number of row buffer hits during reads -system.physmem.writeRowHits 34684 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes -system.physmem.avgGap 16110593.93 # Average gap between requests -system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75993120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 41365500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 269661600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 139644000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36119290320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 800836482750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 926543498730 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.762999 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308404512000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing +system.physmem.readRowHits 58948 # Number of row buffer hits during reads +system.physmem.writeRowHits 33602 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes +system.physmem.avgGap 16356082.24 # Average gap between requests +system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.948938 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9805597500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 77217840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41955375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 278272800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 145262160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89061061440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35704397295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801349556250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926657723160 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.725709 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1308993682000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45532240000 # Time in different power states +system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.002289 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9217388750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4860395 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428546 # DTB read accesses -system.cpu0.dtb.write_hits 3431856 # DTB write hits -system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.read_accesses 429298 # DTB read accesses +system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 164529 # DTB write accesses -system.cpu0.dtb.data_hits 8292251 # DTB hits -system.cpu0.dtb.data_misses 6847 # DTB misses +system.cpu0.dtb.write_accesses 165213 # DTB write accesses +system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 593075 # DTB accesses -system.cpu0.itb.fetch_hits 2736971 # ITB hits -system.cpu0.itb.fetch_misses 3081 # ITB misses +system.cpu0.dtb.data_accesses 594511 # DTB accesses +system.cpu0.itb.fetch_hits 2740787 # ITB hits +system.cpu0.itb.fetch_misses 3088 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2740052 # ITB accesses +system.cpu0.itb.fetch_accesses 2743875 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,87 +358,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 927057463 # number of cpu cycles simulated +system.cpu0.numCycles 928566651 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31701170 # Number of instructions committed -system.cpu0.committedOps 31701170 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29591762 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163845 # Number of float alu accesses -system.cpu0.num_func_calls 797475 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4044448 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29591762 # number of integer instructions -system.cpu0.num_fp_insts 163845 # number of float instructions -system.cpu0.num_int_register_reads 41150829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21753171 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84843 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86199 # number of times the floating registers were written -system.cpu0.num_mem_refs 8322031 # number of memory refs -system.cpu0.num_load_insts 4881580 # Number of load instructions -system.cpu0.num_store_insts 3440451 # Number of store instructions -system.cpu0.num_idle_cycles 904905994.152015 # Number of idle cycles -system.cpu0.num_busy_cycles 22151468.847985 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023894 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976106 # Percentage of idle cycles -system.cpu0.Branches 5099323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1600258 5.05% 5.05% # Class of executed instruction -system.cpu0.op_class::IntAlu 21086062 66.50% 71.55% # Class of executed instruction -system.cpu0.op_class::IntMult 31841 0.10% 71.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12946 0.04% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1618 0.01% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 5012305 15.81% 87.50% # Class of executed instruction -system.cpu0.op_class::MemWrite 3443548 10.86% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 519649 1.64% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31708227 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211399 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211440 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818498105000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39129500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 356633500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22720515500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841614383500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -473,451 +422,508 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192207 # number of callpals executed +system.cpu0.kern.callpal::total 192243 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1739 system.cpu0.kern.mode_good::idle 169 system.cpu0.kern.mode_switch_good::kernel 0.322243 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29940410000 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2625898500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809048073000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393243 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13232435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393755 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.494090 # Average number of references to valid blocks. +system.cpu0.committedInsts 32582067 # Number of instructions committed +system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses +system.cpu0.num_func_calls 798063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30467910 # number of integer instructions +system.cpu0.num_fp_insts 163902 # number of float instructions +system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written +system.cpu0.num_mem_refs 8329685 # number of memory refs +system.cpu0.num_load_insts 4886081 # Number of load instructions +system.cpu0.num_store_insts 3443604 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles +system.cpu0.Branches 5381713 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction +system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1630 0.01% 72.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction +system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 32589155 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to 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rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331086 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.142305 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130858 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094317 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000072 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000025 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110500 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065521 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.239315 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.148709 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110500 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065521 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.239315 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.148709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 27018.047547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16062.292270 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8217.293576 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55908.832915 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43769.600059 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36107.824520 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13297.706198 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19510.491761 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9301.107990 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 31250 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35895.588365 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31306.691546 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19147.215050 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35895.588365 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31306.691546 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19147.215050 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1653965 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2392 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59941 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065299 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065299 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26616.966981 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16212.555367 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8226.037701 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55545.300615 # average WriteReq miss latency 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19154.858191 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1652146 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 59796 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.593217 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 199.333333 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.629708 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835815 # number of writebacks -system.cpu0.dcache.writebacks::total 835815 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 291179 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 291179 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 576940 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 576940 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 835859 # number of writebacks +system.cpu0.dcache.writebacks::total 835859 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288357 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 288357 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572581 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 572581 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1582 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 868119 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 868119 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 868119 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 868119 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86189 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 262124 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 348313 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38232 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99850 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 138082 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2049 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6186 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8235 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 124421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 361974 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 486395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 124421 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 361974 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 486395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1341 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1578 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2919 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1620 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 1904 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3524 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2961 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3482 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6443 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2242469500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4680386500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6922856000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2099274500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4628925917 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6728200417 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25198000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77699000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102897000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 121000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 121000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4341744000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9309312417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13651056417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4341744000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9309312417 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13651056417 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 280410000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 323287500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 603697500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 352231500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 401647500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 753879000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 632641500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 724935000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1357576500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078565 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084593 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038949 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047677 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048912 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022451 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101270 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104338 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040484 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000072 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032226 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065521 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070422 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032226 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 26018.047547 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17855.619859 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19875.387941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54908.832915 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46358.797366 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.122282 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12297.706198 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12560.459101 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12495.081967 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34895.588365 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25718.179806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28065.782784 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 209105.145414 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 204871.673004 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206816.546763 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 217426.851852 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 210949.317227 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213927.071510 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 213658.054711 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 208195.002872 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210705.649542 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860938 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860938 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86798 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260253 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38388 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99272 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137660 # number of WriteReq MSHR misses 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misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 25771500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103207500 # number of LoadLockedReq MSHR miss cycles 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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses 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ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency 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uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964359 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.170929 # Cycle average of tags in use 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0.998381 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963474 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy 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+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017496 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123886 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023069 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15167.105936 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14733.732475 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7095.913382 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7095.913382 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7095.913382 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8552 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 357 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.058651 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.955182 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16739 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16739 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16739 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16739 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16739 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16739 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123075 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 452856 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 123075 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 329781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 452856 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 123075 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 329781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 452856 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1746541000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4501465478 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6248006478 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1746541000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4501465478 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6248006478 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1746541000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4501465478 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6248006478 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010881 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010881 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017267 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.118428 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010881 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13796.894549 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14190.867357 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13649.863024 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13796.894549 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 963474 # number of writebacks +system.cpu0.icache.writebacks::total 963474 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16678 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16678 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16678 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16678 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16678 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16678 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125208 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326815 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 452023 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 125208 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326815 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 452023 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 125208 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326815 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 452023 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1773835000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4488659473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6262494473 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1773835000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4488659473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6262494473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1773835000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4488659473 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6262494473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010631 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010631 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010631 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13854.371289 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1115382 # DTB read hits -system.cpu1.dtb.read_misses 1270 # DTB read misses -system.cpu1.dtb.read_acv 33 # DTB read access violations -system.cpu1.dtb.read_accesses 123322 # DTB read accesses -system.cpu1.dtb.write_hits 822469 # DTB write hits +system.cpu1.dtb.read_hits 1125427 # DTB read hits +system.cpu1.dtb.read_misses 1262 # DTB read misses +system.cpu1.dtb.read_acv 31 # DTB read access violations +system.cpu1.dtb.read_accesses 117717 # DTB read accesses +system.cpu1.dtb.write_hits 832316 # DTB write hits system.cpu1.dtb.write_misses 154 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 50514 # DTB write accesses -system.cpu1.dtb.data_hits 1937851 # DTB hits -system.cpu1.dtb.data_misses 1424 # DTB misses -system.cpu1.dtb.data_acv 51 # DTB access violations -system.cpu1.dtb.data_accesses 173836 # DTB accesses -system.cpu1.itb.fetch_hits 768661 # ITB hits +system.cpu1.dtb.write_accesses 48434 # DTB write accesses +system.cpu1.dtb.data_hits 1957743 # DTB hits +system.cpu1.dtb.data_misses 1416 # DTB misses +system.cpu1.dtb.data_acv 49 # DTB access violations +system.cpu1.dtb.data_accesses 166151 # DTB accesses +system.cpu1.itb.fetch_hits 753702 # ITB hits system.cpu1.itb.fetch_misses 636 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 769297 # ITB accesses +system.cpu1.itb.fetch_accesses 754338 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -930,64 +936,9 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409174 # number of cpu cycles simulated +system.cpu1.numCycles 953452897 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7126126 # Number of instructions committed -system.cpu1.committedOps 7126126 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6614481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39892 # Number of float alu accesses -system.cpu1.num_func_calls 202987 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849967 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6614481 # number of integer instructions -system.cpu1.num_fp_insts 39892 # number of float instructions -system.cpu1.num_int_register_reads 9205425 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4843983 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 21026 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21409 # number of times the floating registers were written -system.cpu1.num_mem_refs 1944596 # number of memory refs -system.cpu1.num_load_insts 1119921 # Number of load instructions -system.cpu1.num_store_insts 824675 # Number of store instructions -system.cpu1.num_idle_cycles 926242764.786654 # Number of idle cycles -system.cpu1.num_busy_cycles 27166409.213346 # Number of busy cycles -system.cpu1.not_idle_fraction 0.028494 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.971506 # Percentage of idle cycles -system.cpu1.Branches 1116663 # Number of branches fetched -system.cpu1.op_class::No_OpClass 388723 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4626654 64.91% 70.37% # Class of executed instruction -system.cpu1.op_class::IntMult 7726 0.11% 70.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3756 0.05% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatDiv 538 0.01% 70.53% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.53% # Class of executed instruction -system.cpu1.op_class::MemRead 1147644 16.10% 86.64% # Class of executed instruction -system.cpu1.op_class::MemWrite 825879 11.59% 98.22% # Class of executed instruction -system.cpu1.op_class::IprAccess 126681 1.78% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7127601 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1005,35 +956,90 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 11557403 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10821969 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 122344 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 9245404 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 7393469 # Number of BTB hits +system.cpu1.committedInsts 7155032 # Number of instructions committed +system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses +system.cpu1.num_func_calls 205327 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6639972 # number of integer instructions +system.cpu1.num_fp_insts 39507 # number of float instructions +system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written +system.cpu1.num_mem_refs 1964570 # number of memory refs +system.cpu1.num_load_insts 1130012 # Number of load instructions +system.cpu1.num_store_insts 834558 # Number of store instructions +system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles +system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles +system.cpu1.Branches 1119214 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction +system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction +system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction +system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 7156497 # Class of executed instruction +system.cpu2.branchPred.lookups 10791906 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.969128 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299976 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7838 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3543723 # DTB read hits -system.cpu2.dtb.read_misses 12250 # DTB read misses -system.cpu2.dtb.read_acv 123 # DTB read access violations -system.cpu2.dtb.read_accesses 249931 # DTB read accesses -system.cpu2.dtb.write_hits 2185333 # DTB write hits -system.cpu2.dtb.write_misses 2753 # DTB write misses -system.cpu2.dtb.write_acv 125 # DTB write access violations -system.cpu2.dtb.write_accesses 92110 # DTB write accesses -system.cpu2.dtb.data_hits 5729056 # DTB hits -system.cpu2.dtb.data_misses 15003 # DTB misses -system.cpu2.dtb.data_acv 248 # DTB access violations -system.cpu2.dtb.data_accesses 342041 # DTB accesses -system.cpu2.itb.fetch_hits 552866 # ITB hits -system.cpu2.itb.fetch_misses 5354 # ITB misses -system.cpu2.itb.fetch_acv 182 # ITB acv -system.cpu2.itb.fetch_accesses 558220 # ITB accesses +system.cpu2.dtb.read_hits 3520448 # DTB read hits +system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_acv 125 # DTB read access violations +system.cpu2.dtb.read_accesses 256305 # DTB read accesses +system.cpu2.dtb.write_hits 2173477 # DTB write hits +system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.write_acv 124 # DTB write access violations +system.cpu2.dtb.write_accesses 93625 # DTB write accesses +system.cpu2.dtb.data_hits 5693925 # DTB hits +system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.data_acv 249 # DTB access violations +system.cpu2.dtb.data_accesses 349930 # DTB accesses +system.cpu2.itb.fetch_hits 553155 # ITB hits +system.cpu2.itb.fetch_misses 5226 # ITB misses +system.cpu2.itb.fetch_acv 187 # ITB acv +system.cpu2.itb.fetch_accesses 558381 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1046,304 +1052,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 33083271 # number of cpu cycles simulated +system.cpu2.numCycles 32236279 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9301099 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 42932048 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 11557403 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 7693445 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 21583805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 404638 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 962 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10456 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 197395 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 92170 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2784665 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90858 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367664 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.311444 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21183291 67.48% 67.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 297740 0.95% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 468841 1.49% 69.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5764163 18.36% 88.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 882544 2.81% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193394 0.62% 91.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 232558 0.74% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434405 1.38% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1933851 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 31390787 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.349343 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.297697 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7618981 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14231209 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8576643 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 528584 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 189420 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174742 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13252 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 39552027 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41601 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 189420 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7898470 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4727919 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6647041 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8797977 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2884017 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 38737545 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 58522 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 372966 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93481 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1809588 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 25849349 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 48570643 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 48506980 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 59488 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 23977354 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1871995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535640 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63418 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3866497 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3518835 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2279192 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 461417 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 331685 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 36218811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 686292 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 35933838 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15798 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2519858 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1130776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 490718 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 31390787 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.144726 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.617565 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18577248 59.18% 59.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2723782 8.68% 67.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1358088 4.33% 72.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 6489843 20.67% 92.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1045865 3.33% 96.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 589790 1.88% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396015 1.26% 99.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 165397 0.53% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44759 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 31390787 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81235 20.78% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 20.78% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 183347 46.90% 67.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126357 32.32% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2960 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 29699192 82.65% 82.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21615 0.06% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 21814 0.06% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1480 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3672081 10.22% 93.00% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2209398 6.15% 99.15% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305298 0.85% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 35933838 # Type of FU issued -system.cpu2.iq.rate 1.086163 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 390939 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.010879 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 103401518 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39305388 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 35307106 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 263682 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125410 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122335 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36181025 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140792 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 202971 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued +system.cpu2.iq.rate 1.044198 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 432355 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1077 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5954 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178558 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4490 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 225000 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 189420 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4054480 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 208473 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 38277538 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51152 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3518835 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2279192 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 610930 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12812 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 160010 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5954 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 60508 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134714 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 35737943 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3564708 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195895 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1372435 # number of nop insts executed -system.cpu2.iew.exec_refs 5757521 # number of memory reference insts executed -system.cpu2.iew.exec_branches 8471480 # Number of branches executed -system.cpu2.iew.exec_stores 2192813 # Number of stores executed -system.cpu2.iew.exec_rate 1.080242 # Inst execution rate -system.cpu2.iew.wb_sent 35472276 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 35429441 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 20887132 # num instructions producing a value -system.cpu2.iew.wb_consumers 24638595 # num instructions consuming a value +system.cpu2.iew.exec_nop 1364255 # number of nop insts executed +system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732316 # Number of branches executed +system.cpu2.iew.exec_stores 2180861 # Number of stores executed +system.cpu2.iew.exec_rate 1.038124 # Inst execution rate +system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19395256 # num instructions producing a value +system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.070917 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.847740 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2638965 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 195574 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 178349 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30927462 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.150843 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846358 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19331784 62.51% 62.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2240622 7.24% 69.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1164134 3.76% 73.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6211408 20.08% 93.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 591221 1.91% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197085 0.64% 96.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 163594 0.53% 96.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 163249 0.53% 97.21% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 864365 2.79% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30927462 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 35592650 # Number of instructions committed -system.cpu2.commit.committedOps 35592650 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33322350 # Number of instructions committed +system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5187114 # Number of memory references committed -system.cpu2.commit.loads 3086480 # Number of loads committed -system.cpu2.commit.membars 68869 # Number of memory barriers committed -system.cpu2.commit.branches 8299152 # Number of branches committed -system.cpu2.commit.fp_insts 120520 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 34085086 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241488 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1210365 3.40% 3.40% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 28775352 80.85% 84.25% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 21144 0.06% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21379 0.06% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1480 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.37% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3155349 8.87% 93.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2102283 5.91% 99.14% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305298 0.86% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5160547 # Number of memory references committed +system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.membars 67946 # Number of memory barriers committed +system.cpu2.commit.branches 7560075 # Number of branches committed +system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240099 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 35592650 # Class of committed instruction -system.cpu2.commit.bw_lim_events 864365 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 68219321 # The number of ROB reads -system.cpu2.rob.rob_writes 76925100 # The number of ROB writes -system.cpu2.timesIdled 177793 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1692484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1742724515 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 34385245 # Number of Instructions Simulated -system.cpu2.committedOps 34385245 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.962136 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.962136 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.039354 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.039354 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 46956630 # number of integer regfile reads -system.cpu2.int_regfile_writes 24762728 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74199 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74347 # number of floating regfile writes -system.cpu2.misc_regfile_reads 6109617 # number of misc regfile reads -system.cpu2.misc_regfile_writes 275370 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65049813 # The number of ROB reads +system.cpu2.rob.rob_writes 72365341 # The number of ROB writes +system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32121047 # Number of Instructions Simulated +system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads +system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1358,9 +1365,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 51362 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51364 # Transaction distribution +system.iobus.trans_dist::WriteResp 51364 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1372,11 +1379,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1388,37 +1395,37 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2206000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 116500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5525000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2084000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 88878376 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 84230549 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9362000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17358000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254039 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693946387000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254039 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078377 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078377 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1432,14 +1439,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9722962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9722962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2243179414 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2243179414 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9722962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9722962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9722962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9722962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1456,266 +1463,270 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56202.092486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 56202.092486 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 53984.872305 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 53984.872305 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 56202.092486 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 56202.092486 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 71 # number of ReadReq MSHR misses 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WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6172962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6172962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6172962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.410405 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.413169 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.410405 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.410405 # 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miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency 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system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 717 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2728 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55352 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 713 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38426412 # Number of tag accesses -system.l2c.tags.data_accesses 38426412 # Number of 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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 202427.071510 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 201705.167173 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 196241.815049 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 198752.599721 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294893 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116701 # Transaction distribution -system.membus.trans_dist::CleanEvict 261800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 141 # Transaction distribution +system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::WriteReq 9812 # Transaction distribution +system.membus.trans_dist::WriteResp 9812 # Transaction distribution +system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution +system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143 # Transaction distribution -system.membus.trans_dist::ReadExReq 115600 # Transaction distribution -system.membus.trans_dist::ReadExResp 115600 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288004 # Transaction distribution -system.membus.trans_dist::BadAddressError 255 # Transaction distribution +system.membus.trans_dist::UpgradeResp 162 # Transaction distribution +system.membus.trans_dist::ReadExReq 115651 # Transaction distribution +system.membus.trans_dist::ReadExResp 115651 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143509 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177927 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124919 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30608832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30654400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33318656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 161 # Total snoops (count) -system.membus.snoop_fanout::samples 840917 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 159 # Total snoops (count) +system.membus.snoop_fanout::samples 840768 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840917 # Request fanout histogram -system.membus.reqLayer0.occupancy 11282500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840768 # Request fanout histogram +system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 355534840 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 377985955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 28782491 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4716700 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2358029 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1601 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1128 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1128 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063159 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 879803 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1563697 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 38 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302846 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 965048 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091237 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 255 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 17168 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2894139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214034 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7108173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61761536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142741760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204503296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421014 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5154488 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000869 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.029472 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421214 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5150007 99.91% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4481 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5154488 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1335525500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 102462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 679735096 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 746367473 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index a32ac72f7..ba967980d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848053 # Number of seconds simulated -sim_ticks 2848053071500 # Number of ticks simulated -final_tick 2848053071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848948 # Number of seconds simulated +sim_ticks 2848948370000 # Number of ticks simulated +final_tick 2848948370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153295 # Simulator instruction rate (inst/s) -host_op_rate 185627 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3443122383 # Simulator tick rate (ticks/s) -host_mem_usage 659004 # Number of bytes of host memory used -host_seconds 827.17 # Real time elapsed on the host -sim_insts 126801159 # Number of instructions simulated -sim_ops 153545030 # Number of ops (including micro ops) simulated +host_inst_rate 158621 # Simulator instruction rate (inst/s) +host_op_rate 192077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3558804720 # Simulator tick rate (ticks/s) +host_mem_usage 665700 # Number of bytes of host memory used +host_seconds 800.54 # Real time elapsed on the host +sim_insts 126981470 # Number of instructions simulated +sim_ops 153764073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1683840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1312624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8530944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 199296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 609360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 366080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1698304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1350900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8536512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 207232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 624212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 339264 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12712960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1683840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 199296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1883136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8845504 # Number of bytes written to this memory +system.physmem.bytes_read::total 12767176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1698304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 207232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1905536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8850048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8863068 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 137 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8867612 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3114 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5720 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3238 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5301 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138211 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200031 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138282 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142602 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3079 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142673 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3145 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 591225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 460885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2995360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 213957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 128537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 596116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 474175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2996373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 119084 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4463737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 591225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 661201 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3105807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4481364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 596116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 668856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3106426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3111974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3105807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3112591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3106426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 591225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 467038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2995360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 213971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 128537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 596116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 480326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2996373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 119084 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7575711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199182 # Number of read requests accepted -system.physmem.writeReqs 142602 # Number of write requests accepted -system.physmem.readBursts 199182 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142602 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12737472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8875904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12712960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8863068 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49648 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12703 # Per bank write bursts -system.physmem.perBankRdBursts::1 12645 # Per bank write bursts -system.physmem.perBankRdBursts::2 12416 # Per bank write bursts -system.physmem.perBankRdBursts::3 12383 # Per bank write bursts -system.physmem.perBankRdBursts::4 15579 # Per bank write bursts -system.physmem.perBankRdBursts::5 12155 # Per bank write bursts -system.physmem.perBankRdBursts::6 12470 # Per bank write bursts -system.physmem.perBankRdBursts::7 12693 # Per bank write bursts -system.physmem.perBankRdBursts::8 11969 # Per bank write bursts -system.physmem.perBankRdBursts::9 11857 # Per bank write bursts -system.physmem.perBankRdBursts::10 12504 # Per bank write bursts -system.physmem.perBankRdBursts::11 11838 # Per bank write bursts -system.physmem.perBankRdBursts::12 11708 # Per bank write bursts -system.physmem.perBankRdBursts::13 12391 # Per bank write bursts -system.physmem.perBankRdBursts::14 11950 # Per bank write bursts -system.physmem.perBankRdBursts::15 11762 # Per bank write bursts -system.physmem.perBankWrBursts::0 9214 # Per bank write bursts -system.physmem.perBankWrBursts::1 9232 # Per bank write bursts -system.physmem.perBankWrBursts::2 9104 # Per bank write bursts -system.physmem.perBankWrBursts::3 8883 # Per bank write bursts -system.physmem.perBankWrBursts::4 8269 # Per bank write bursts -system.physmem.perBankWrBursts::5 8437 # Per bank write bursts -system.physmem.perBankWrBursts::6 8818 # Per bank write bursts -system.physmem.perBankWrBursts::7 8777 # Per bank write bursts -system.physmem.perBankWrBursts::8 8437 # Per bank write bursts -system.physmem.perBankWrBursts::9 8418 # Per bank write bursts -system.physmem.perBankWrBursts::10 9013 # Per bank write bursts -system.physmem.perBankWrBursts::11 8780 # Per bank write bursts -system.physmem.perBankWrBursts::12 8383 # Per bank write bursts -system.physmem.perBankWrBursts::13 8480 # Per bank write bursts -system.physmem.perBankWrBursts::14 8424 # Per bank write bursts -system.physmem.perBankWrBursts::15 8017 # Per bank write bursts +system.physmem.bw_total::total 7593956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200031 # Number of read requests accepted +system.physmem.writeReqs 142673 # Number of write requests accepted +system.physmem.readBursts 200031 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 142673 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12791872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue +system.physmem.bytesWritten 8880320 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12767176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8867612 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 68768 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12184 # Per bank write bursts +system.physmem.perBankRdBursts::1 12601 # Per bank write bursts +system.physmem.perBankRdBursts::2 13506 # Per bank write bursts +system.physmem.perBankRdBursts::3 12929 # Per bank write bursts +system.physmem.perBankRdBursts::4 15744 # Per bank write bursts +system.physmem.perBankRdBursts::5 12758 # Per bank write bursts +system.physmem.perBankRdBursts::6 12529 # Per bank write bursts +system.physmem.perBankRdBursts::7 12787 # Per bank write bursts +system.physmem.perBankRdBursts::8 11927 # Per bank write bursts +system.physmem.perBankRdBursts::9 12161 # Per bank write bursts +system.physmem.perBankRdBursts::10 11607 # Per bank write bursts +system.physmem.perBankRdBursts::11 10617 # Per bank write bursts +system.physmem.perBankRdBursts::12 11871 # Per bank write bursts +system.physmem.perBankRdBursts::13 12870 # Per bank write bursts +system.physmem.perBankRdBursts::14 12074 # Per bank write bursts +system.physmem.perBankRdBursts::15 11708 # Per bank write bursts +system.physmem.perBankWrBursts::0 8731 # Per bank write bursts +system.physmem.perBankWrBursts::1 9199 # Per bank write bursts +system.physmem.perBankWrBursts::2 9827 # Per bank write bursts +system.physmem.perBankWrBursts::3 9174 # Per bank write bursts +system.physmem.perBankWrBursts::4 8354 # Per bank write bursts +system.physmem.perBankWrBursts::5 8906 # Per bank write bursts +system.physmem.perBankWrBursts::6 8822 # Per bank write bursts +system.physmem.perBankWrBursts::7 8920 # Per bank write bursts +system.physmem.perBankWrBursts::8 8409 # Per bank write bursts +system.physmem.perBankWrBursts::9 8625 # Per bank write bursts +system.physmem.perBankWrBursts::10 8250 # Per bank write bursts +system.physmem.perBankWrBursts::11 7761 # Per bank write bursts +system.physmem.perBankWrBursts::12 8553 # Per bank write bursts +system.physmem.perBankWrBursts::13 8825 # Per bank write bursts +system.physmem.perBankWrBursts::14 8501 # Per bank write bursts +system.physmem.perBankWrBursts::15 7898 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 2848052462500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 2848947824000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 554 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198602 # Read request sizes (log2) +system.physmem.readPktSize::6 199449 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138211 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3805 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138282 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 88254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -184,157 +184,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.573648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.731983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 302.151175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46893 52.63% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17637 19.79% 72.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6363 7.14% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3624 4.07% 83.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2948 3.31% 86.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1436 1.61% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 938 1.05% 89.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 975 1.09% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8286 9.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89100 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6864 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.995047 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.916897 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6863 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6864 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6864 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.204837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.711823 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.958888 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5637 82.12% 82.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 489 7.12% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.19% 90.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 154 2.24% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 37 0.54% 93.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 124 1.81% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 47 0.68% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.23% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.31% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.28% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.15% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 153 2.23% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 30 0.44% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6864 # Writes before turning the bus around for reads -system.physmem.totQLat 5502163905 # Total ticks spent queuing -system.physmem.totMemAccLat 9233845155 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 995115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27645.87 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 86 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92034 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.479584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.901184 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.713631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 49789 54.10% 54.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17966 19.52% 73.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6251 6.79% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3568 3.88% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2967 3.22% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1449 1.57% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 893 0.97% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 932 1.01% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8219 8.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92034 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6844 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.203828 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.949624 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6843 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6844 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6844 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.273963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.786776 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.867549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5615 82.04% 82.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 464 6.78% 88.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 114 1.67% 90.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 150 2.19% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 34 0.50% 93.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 131 1.91% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 38 0.56% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.28% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.34% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 24 0.35% 96.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 141 2.06% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 23 0.34% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.07% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6844 # Writes before turning the bus around for reads +system.physmem.totQLat 5355833046 # Total ticks spent queuing +system.physmem.totMemAccLat 9103451796 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 999365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26796.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46395.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45546.18 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 165564 # Number of row buffer hits during reads -system.physmem.writeRowHits 83044 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.87 # Row buffer hit rate for writes -system.physmem.avgGap 8332901.66 # Average gap between requests -system.physmem.pageHitRate 73.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 347056920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189366375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 803743200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 458356320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84074155830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1635078931500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1906972178385 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.571882 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719967809945 # Time in different power states -system.physmem_0.memoryStateTime::REF 95102540000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing +system.physmem.readRowHits 165962 # Number of row buffer hits during reads +system.physmem.writeRowHits 80631 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes +system.physmem.avgGap 8313144.36 # Average gap between requests +system.physmem.pageHitRate 72.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 368376120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 200998875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 819296400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466125840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186079052640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85041435285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634767692000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1907742977160 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.631992 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719447345615 # Time in different power states +system.physmem_0.memoryStateTime::REF 95132440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32976648805 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34362631885 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326539080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178171125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748628400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 440328960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186020568240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83156024340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635884310000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1906754570145 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.495475 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721316836638 # Time in different power states -system.physmem_1.memoryStateTime::REF 95102540000 # Time in different power states +system.physmem_1.actEnergy 327400920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178641375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 739705200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433006560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186079052640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83645503290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635992193750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1907395503735 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.510026 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721498270016 # Time in different power states +system.physmem_1.memoryStateTime::REF 95132440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31633548862 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32317496984 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -360,15 +364,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36422708 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17757542 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1699668 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20591819 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 15078708 # Number of BTB hits +system.cpu0.branchPred.lookups 36425252 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17807915 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1745628 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20690008 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 15088743 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.226693 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11344544 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 821497 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.927681 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11310340 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 873015 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -399,56 +403,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 72997 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 72997 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47155 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25842 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 72997 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 72997 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 72997 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7509 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10509.122386 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9271.690184 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8241.046102 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7465 99.41% 99.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 36 0.48% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7509 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 581566000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 581566000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 581566000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5843 77.81% 77.81% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1666 22.19% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7509 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72997 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 73398 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 73398 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47504 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25894 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 73398 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 73398 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 73398 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7534 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12254.313778 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11412.538854 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6583.009911 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7485 99.35% 99.35% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 43 0.57% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 5 0.07% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7534 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5832 77.41% 77.41% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1702 22.59% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7534 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73398 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72997 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73398 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7534 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7509 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 80506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7534 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 80932 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24918355 # DTB read hits -system.cpu0.dtb.read_misses 66392 # DTB read misses -system.cpu0.dtb.write_hits 18544526 # DTB write hits -system.cpu0.dtb.write_misses 6605 # DTB write misses +system.cpu0.dtb.read_hits 24893776 # DTB read hits +system.cpu0.dtb.read_misses 66568 # DTB read misses +system.cpu0.dtb.write_hits 18528826 # DTB write hits +system.cpu0.dtb.write_misses 6830 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3803 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1293 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2019 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3826 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1295 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2023 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24984747 # DTB read accesses -system.cpu0.dtb.write_accesses 18551131 # DTB write accesses +system.cpu0.dtb.perms_faults 643 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24960344 # DTB read accesses +system.cpu0.dtb.write_accesses 18535656 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43462881 # DTB hits -system.cpu0.dtb.misses 72997 # DTB misses -system.cpu0.dtb.accesses 43535878 # DTB accesses +system.cpu0.dtb.hits 43422602 # DTB hits +system.cpu0.dtb.misses 73398 # DTB misses +system.cpu0.dtb.accesses 43496000 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -478,37 +482,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4165 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4165 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 4162 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4162 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3841 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4165 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4165 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4165 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2676 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10991.778774 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9686.198014 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6109.891448 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2598 97.09% 97.09% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 50 1.87% 98.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 27 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3838 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4162 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4162 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4162 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2674 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12829.655946 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12107.498542 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5222.854689 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2410 90.13% 90.13% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 239 8.94% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 23 0.86% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2676 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 580856500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 580856500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 580856500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2357 88.08% 88.08% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 11.92% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2676 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2674 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2355 88.07% 88.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 319 11.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2674 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4165 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4165 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4162 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4162 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2676 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2676 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71531107 # ITB inst hits -system.cpu0.itb.inst_misses 4165 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6836 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 71465911 # ITB inst hits +system.cpu0.itb.inst_misses 4162 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -517,131 +522,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2451 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2452 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8112 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 8217 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71535272 # ITB inst accesses -system.cpu0.itb.hits 71531107 # DTB hits -system.cpu0.itb.misses 4165 # DTB misses -system.cpu0.itb.accesses 71535272 # DTB accesses -system.cpu0.numCycles 246249018 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71470073 # ITB inst accesses +system.cpu0.itb.hits 71465911 # DTB hits +system.cpu0.itb.misses 4162 # DTB misses +system.cpu0.itb.accesses 71470073 # DTB accesses +system.cpu0.numCycles 248898522 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 113090684 # Number of instructions committed -system.cpu0.committedOps 136745700 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8942808 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1853 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5449882320 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.177447 # CPI: cycles per instruction -system.cpu0.ipc 0.459253 # IPC: instructions per cycle +system.cpu0.committedInsts 112980792 # Number of instructions committed +system.cpu0.committedOps 136605971 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8918624 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1867 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5449022663 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.203016 # CPI: cycles per instruction +system.cpu0.ipc 0.453923 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed -system.cpu0.tickCycles 199226503 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 47022515 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 754267 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.799422 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41868735 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 754779 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.471516 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 600230000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.799422 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968358 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.968358 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1869 # number of quiesce instructions executed +system.cpu0.tickCycles 199912219 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 48986303 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 760179 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.990908 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41826926 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 760691 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 54.985436 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.990908 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972638 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.972638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86874809 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86874809 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23308542 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23308542 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17374131 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17374131 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329905 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329905 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374910 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374910 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371257 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371257 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40682673 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40682673 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 41012578 # number of overall hits -system.cpu0.dcache.overall_hits::total 41012578 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 490349 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 490349 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 600389 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 600389 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141605 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141605 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21484 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21484 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20155 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20155 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1090738 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1090738 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1232343 # number of overall misses -system.cpu0.dcache.overall_misses::total 1232343 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6919620500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6919620500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11358969500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11358969500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328836500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 328836500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472700000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 472700000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 403000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 403000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 18278590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18278590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 18278590000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18278590000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23798891 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23798891 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17974520 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17974520 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471510 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 471510 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396394 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396394 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391412 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391412 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41773411 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41773411 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42244921 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42244921 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020604 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033402 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033402 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300322 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300322 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054199 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054199 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051493 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051493 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026111 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026111 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029171 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029171 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14111.623558 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14111.623558 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18919.349788 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18919.349788 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15306.111525 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15306.111525 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23453.237410 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23453.237410 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 86810511 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 86810511 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23283800 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23283800 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17355484 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17355484 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329213 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 329213 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374953 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374953 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370901 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370901 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40639284 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40639284 # number of demand (read+write) hits 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of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 535273000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 491000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 491000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 19573571500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 19573571500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 19573571500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 19573571500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23778385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23778385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17960378 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17960378 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471203 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 471203 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391410 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391410 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 41738763 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 41738763 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 42209966 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 42209966 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020800 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020800 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033679 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033679 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301335 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301335 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052398 # miss rate for StoreCondReq accesses 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average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17802.587862 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.460137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15766.460137 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -650,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 540480 # number of writebacks -system.cpu0.dcache.writebacks::total 540480 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 76076 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 76076 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 264589 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 264589 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14754 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14754 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 340665 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 340665 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 340665 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 340665 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 414273 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 414273 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335800 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 335800 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107967 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 107967 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6730 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6730 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20155 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20155 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 750073 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 750073 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 858040 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 858040 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32040 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32040 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60762 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60762 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5238286000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5238286000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6456534000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6456534000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810830000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810830000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104761500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104761500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452552000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452552000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 396000 # 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12644.526677 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19227.319833 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19227.319833 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16772.069243 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16772.069243 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15566.344725 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15566.344725 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.584718 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.584718 # average StoreCondReq mshr miss latency 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uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452503000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452503000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12155445500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12155445500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017590 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018846 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230103 # mshr miss rate for SoftPFReq accesses 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12663.883337 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12663.883337 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21036.211674 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21036.211674 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16675.499193 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16675.499193 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15816.919773 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15816.919773 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25099.907358 # average StoreCondReq mshr miss latency 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mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179533.023466 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179533.023466 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189343.323130 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189343.323130 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16408.709792 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16408.709792 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16442.144385 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16442.144385 # average overall mshr miss latency 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142328.863346 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142328.863346 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142328.863346 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142328.863346 # average overall mshr uncacheable latency +system.cpu0.icache.writebacks::writebacks 2044142 # number of writebacks +system.cpu0.icache.writebacks::total 2044142 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2044673 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2044673 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2044673 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2044673 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 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142291.677304 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1923323 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1923513 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 165 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1928199 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1928402 # number of prefetch candidates identified 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-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.074138 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008956 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.020731 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036436 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176690 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.152490 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.152490 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034380 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034380 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188741 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188741 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008051 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019392 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034380 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176207 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072644 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008051 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019392 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034380 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176207 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.159659 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38095.756881 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83864.061723 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35001.012526 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35001.012526 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16525.682006 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16525.682006 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 171249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 171249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57120.246365 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57120.246365 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 55749.536950 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28760.263037 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28760.263037 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43445.423602 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40405.006418 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18752.688172 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 55749.536950 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37067.522566 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83864.061723 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 65095.662608 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190134.581773 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 184058.100403 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172014.205139 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172014.205139 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134328.735632 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181569.138606 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 178709.603105 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38808.422301 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79560.575914 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26906.024521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26906.024521 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17563.487420 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17563.487420 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 404999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 404999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57297.803272 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57297.803272 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58173.070631 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58173.070631 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28950.629460 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28950.629460 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58173.070631 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37433.068707 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44227.440987 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41917.123288 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18725.663717 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58173.070631 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37433.068707 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79560.575914 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63714.398811 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201180.210967 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193894.257508 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182299.321149 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182299.321149 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192255.224789 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188745.234598 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 5752448 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2898331 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 171817 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 171638 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 142841 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2765458 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 746343 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2333999 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 319529 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85747 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112824 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299375 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 296092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2044818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 602268 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3078 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6106044 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739032 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12492 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 185819 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9043387 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 131118848 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 90716354 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 347920 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 222201066 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 910866 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 6693455 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.042507 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.201876 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5764816 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2905184 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45291 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 351229 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 346765 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 143291 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2770361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 748097 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2249647 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 247676 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 331668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114222 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 300767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297392 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2044673 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 607119 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3062 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6104641 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2759378 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13827 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189965 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9067811 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 259587264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104603354 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23308 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362692 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 364576618 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1079592 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4075784 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104187 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 6409112 95.75% 95.75% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 284164 4.25% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3655604 89.69% 89.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 415716 10.20% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4464 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 6693455 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3504755489 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115583734 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4075784 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5775269994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115824460 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3073459276 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3073569625 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1298870694 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1308368315 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8011489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8011477 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 98861455 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 99320942 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3534290 # Number of BP lookups -system.cpu1.branchPred.condPredicted 1990183 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 201553 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2067319 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1417438 # Number of BTB hits +system.cpu1.branchPred.lookups 3602112 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2032281 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 210658 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2218631 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1453392 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 68.564068 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 735878 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 53173 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.508505 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 748126 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55361 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1293,59 +1293,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 21952 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21952 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 17656 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4296 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 21952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 21952 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 21952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1858 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11787.944026 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10957.170839 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8000.267562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1715 92.30% 92.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 133 7.16% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 6 0.32% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 1 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1858 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2099073032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2099073032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2099073032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1319 70.99% 70.99% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 539 29.01% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1858 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 22520 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22520 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18297 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4223 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 22520 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 22520 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 22520 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1840 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11809.782609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11060.962968 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6551.399815 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1685 91.58% 91.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 142 7.72% 99.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.43% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1840 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1331 72.34% 72.34% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 509 27.66% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1840 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22520 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21952 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1858 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1840 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1858 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 23810 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1840 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24360 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3504265 # DTB read hits -system.cpu1.dtb.read_misses 20273 # DTB read misses -system.cpu1.dtb.write_hits 2919622 # DTB write hits -system.cpu1.dtb.write_misses 1679 # DTB write misses +system.cpu1.dtb.read_hits 3580818 # DTB read hits +system.cpu1.dtb.read_misses 20748 # DTB read misses +system.cpu1.dtb.write_hits 2975375 # DTB write hits +system.cpu1.dtb.write_misses 1772 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1723 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1719 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 96 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 254 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3524538 # DTB read accesses -system.cpu1.dtb.write_accesses 2921301 # DTB write accesses +system.cpu1.dtb.read_accesses 3601566 # DTB read accesses +system.cpu1.dtb.write_accesses 2977147 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6423887 # DTB hits -system.cpu1.dtb.misses 21952 # DTB misses -system.cpu1.dtb.accesses 6445839 # DTB accesses +system.cpu1.dtb.hits 6556193 # DTB hits +system.cpu1.dtb.misses 22520 # DTB misses +system.cpu1.dtb.accesses 6578713 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,42 +1373,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1951 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1951 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 155 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1796 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1951 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1951 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1951 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11383.431953 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10916.753394 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4130.106784 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 149 17.63% 17.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 569 67.34% 84.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 12.66% 97.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 9 1.07% 98.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.47% 99.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.47% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 1949 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1949 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 152 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1797 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1949 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1949 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1949 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 843 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11825.029656 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11322.074300 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4470.335302 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 130 15.42% 15.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 558 66.19% 81.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 110 13.05% 94.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 4 0.47% 97.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.19% 98.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 2 0.24% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.71% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2099960532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2099960532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2099960532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 843 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 703 83.39% 83.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 140 16.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 843 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1951 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1951 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1949 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1949 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2796 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6761340 # ITB inst hits -system.cpu1.itb.inst_misses 1951 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 843 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2792 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 6911047 # ITB inst hits +system.cpu1.itb.inst_misses 1949 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1419,130 +1418,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 907 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1031 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6763291 # ITB inst accesses -system.cpu1.itb.hits 6761340 # DTB hits -system.cpu1.itb.misses 1951 # DTB misses -system.cpu1.itb.accesses 6763291 # DTB accesses -system.cpu1.numCycles 39381699 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6912996 # ITB inst accesses +system.cpu1.itb.hits 6911047 # DTB hits +system.cpu1.itb.misses 1949 # DTB misses +system.cpu1.itb.accesses 6912996 # DTB accesses +system.cpu1.numCycles 40490463 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13710475 # Number of instructions committed -system.cpu1.committedOps 16799330 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1340837 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2719 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656091241 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.872380 # CPI: cycles per instruction -system.cpu1.ipc 0.348143 # IPC: instructions per cycle +system.cpu1.committedInsts 14000678 # Number of instructions committed +system.cpu1.committedOps 17158102 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1376852 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5656768220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.892036 # CPI: cycles per instruction +system.cpu1.ipc 0.345777 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2719 # number of quiesce instructions executed -system.cpu1.tickCycles 26653258 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 12728441 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 152894 # number of replacements -system.cpu1.dcache.tags.tagsinuse 470.093140 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6072239 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 153243 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.624903 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 110033723500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.093140 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918151 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.918151 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12903758 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12903758 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3189039 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3189039 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2677291 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2677291 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41980 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41980 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69267 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69267 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60867 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60867 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5866330 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5866330 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5908310 # number of overall hits -system.cpu1.dcache.overall_hits::total 5908310 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 130563 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 130563 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 120040 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 120040 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24252 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24252 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16672 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16672 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23310 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23310 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 250603 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 250603 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 274855 # number of overall misses -system.cpu1.dcache.overall_misses::total 274855 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2128187500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2128187500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4337924000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4337924000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321753000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 321753000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615942500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 615942500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1442500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1442500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6466111500 # number of demand (read+write) miss cycles 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16185.899347 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16185.899347 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36952.537203 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36952.537203 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19279.741795 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19279.741795 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27333.326206 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27333.326206 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25802.211067 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 25802.211067 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23525.537101 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23525.537101 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26046.148306 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26046.148306 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23768.219846 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23768.219846 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1551,149 +1550,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 95329 # number of writebacks -system.cpu1.dcache.writebacks::total 95329 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12149 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 12149 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41106 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 41106 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11576 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11576 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 53255 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 53255 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 53255 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 53255 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118414 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118414 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78934 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 78934 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23724 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23724 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5096 # number of LoadLockedReq MSHR misses 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overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4896262500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 356276500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 356276500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224816500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224816500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 581093000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 581093000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035671 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035671 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028218 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028218 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358195 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358195 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059298 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.059298 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.276916 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.276916 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032263 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032263 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035754 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035754 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15300.082760 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15300.082760 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33592.273292 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33592.273292 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18249.283426 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18249.283426 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18080.455259 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18080.455259 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25424.560275 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25424.560275 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 156173 # number of writebacks +system.cpu1.dcache.writebacks::total 156173 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12677 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 12677 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41645 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 41645 # number of WriteReq MSHR hits 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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 23961 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4877 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4877 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23384 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23384 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 201137 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 201137 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 225098 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 225098 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5287 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5287 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1847735500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1847735500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2733456500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2733456500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 448084000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 448084000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87974000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87974000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 615791500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 615791500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1382500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1382500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4581192000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4581192000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5029276000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5029276000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389353500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389353500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251607000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251607000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 640960500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 640960500 # number of overall MSHR uncacheable cycles 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0.274280 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032215 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032215 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035669 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035669 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15209.326924 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15209.326924 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34318.349027 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34318.349027 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18700.555069 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18700.555069 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18038.548288 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18038.548288 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26333.882142 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26333.882142 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22616.476985 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22616.476985 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22147.818358 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22147.818358 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125228.998243 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125228.998243 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102609.082611 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 102609.082611 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 115387.807784 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 115387.807784 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22776.475735 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22776.475735 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22342.606331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22342.606331 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130831.149194 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130831.149194 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108873.647772 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108873.647772 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121233.308114 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121233.308114 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 837637 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.228366 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5922018 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 838149 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.065591 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72771979500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.228366 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975055 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975055 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 857356 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.135276 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6052000 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 857868 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.054698 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73316283000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135276 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974874 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974874 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14358483 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14358483 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5922018 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5922018 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5922018 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5922018 # number of demand (read+write) hits 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of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7371671000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7371671000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 6760167 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 6760167 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 6760167 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 6760167 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 6760167 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 6760167 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.123983 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.123983 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.123983 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.123983 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.123983 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.123983 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8795.179616 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8795.179616 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8795.179616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8795.179616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8795.179616 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14677604 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14677604 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6052000 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6052000 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6052000 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6052000 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6052000 # number of overall hits +system.cpu1.icache.overall_hits::total 6052000 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 857868 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 857868 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 857868 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 857868 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 857868 # number of overall misses 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number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 6909868 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 6909868 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124151 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.124151 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124151 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.124151 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124151 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.124151 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8849.576508 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8849.576508 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8849.576508 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8849.576508 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8849.576508 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8849.576508 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1702,452 +1701,456 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed 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137058.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119402 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119476 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 119508 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 119564 # number of prefetch candidates identified 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0.000005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.257194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132720 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052299 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.932353 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1099 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13920 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1042 # Occupied blocks per task id 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95329 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1276 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1276 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 784 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 784 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 17759 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 17759 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 825014 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 825014 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 81245 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 81245 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23345 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2401 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UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 27711 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22526 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22526 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32189 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32189 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13135 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13135 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 65988 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 65988 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 724 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 240 # number of demand (read+write) misses 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ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1579312997 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1579312997 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 16832000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4807500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733172000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3265436497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4020247997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 16832000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4807500 # number of overall miss cycles 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0.089933 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.033900 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.955980 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.955980 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966366 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966366 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015656 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.447882 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.447882 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.105420 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.030080 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090875 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015656 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.496366 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.639312 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.639312 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014882 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014882 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.444293 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.444293 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027748 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.089933 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014882 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.493225 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103761 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027748 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.089933 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014882 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.493225 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123009 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16447.614108 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55962.030191 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19994.370467 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19994.370467 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18513.917251 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18513.917251 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45891.797939 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45891.797939 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49821.216278 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.069681 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.069681 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29620.292935 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17248.618785 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14031.250000 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49821.216278 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27041.691328 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55962.030191 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33387.027679 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117221.441125 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117594.183294 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95050.661798 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 95050.661798 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127062.500000 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 107575.655282 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 107999.611500 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122376 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16065.874730 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47856.937268 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.410143 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.410143 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18769.490656 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18769.490656 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1285000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1285000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46666.356011 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46666.356011 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51608.012846 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51608.012846 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17914.886101 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17914.886101 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51608.012846 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27265.642503 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29931.907322 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16734.992679 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14185.185185 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51608.012846 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27265.642503 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47856.937268 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32658.506137 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122808.635753 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123035.297927 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101317.827780 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101317.827780 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113414.790997 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113739.303575 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 2085429 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1050114 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 105283 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 105064 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 32952 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1055933 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2191 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 125445 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 933113 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 22957 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41419 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84915 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 54585 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 838149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 236592 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 39 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2498025 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 734861 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6388 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50317 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3289591 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 53648704 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 21442516 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10564 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 96276 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 75198060 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 344587 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2379730 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.062577 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.242581 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 2131909 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1073389 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18199 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 177399 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1221 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 33577 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1078735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 124920 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 900775 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 97230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 24545 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71695 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41696 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84990 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57514 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55014 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 857868 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234653 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 35 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2557119 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 745420 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6448 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51357 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3360344 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 108744896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394242 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10808 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 98456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 134248402 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 381517 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1451505 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.140526 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.349944 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2231032 93.75% 93.75% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 148479 6.24% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 219 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1248752 86.03% 86.03% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 201532 13.88% 99.92% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1221 0.08% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2379730 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1153078495 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79714518 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1451505 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2095009994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78651519 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1257481819 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1287084271 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 326951344 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 333125737 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3747000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3746000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 26275944 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 26768449 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31009 # Transaction distribution system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2168,11 +2171,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2193,67 +2196,67 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40103000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 51019501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 572500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6101000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 169500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 32834001 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186411762 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186304797 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 14.472862 # Cycle average of tags in use +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.470000 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271656669000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472862 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904554 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904554 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272418338000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.470000 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904375 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904375 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2267,14 +2270,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31866877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31866877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715834885 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715834885 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31866877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31866877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31866877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31866877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31658876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31658876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4735531921 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4735531921 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31658876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31658876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31658876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31658876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2291,24 +2294,24 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 131139.411523 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 131139.411523 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130185.371163 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130185.371163 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 131139.411523 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 131139.411523 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 131139.411523 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130283.440329 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130283.440329 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130729.127678 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130729.127678 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130283.440329 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130283.440329 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130283.440329 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130283.440329 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 628 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 73 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.602740 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2317,14 +2320,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19716877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19716877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904634885 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2904634885 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19716877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19716877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19716877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19716877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19508876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19508876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2924331921 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2924331921 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19508876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19508876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19508876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19508876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2333,580 +2336,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 81139.411523 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81139.411523 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80185.371163 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80185.371163 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 81139.411523 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 81139.411523 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80283.440329 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80283.440329 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80729.127678 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80729.127678 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80283.440329 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80283.440329 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80283.440329 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80283.440329 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 133318 # number of replacements -system.l2c.tags.tagsinuse 64014.997062 # Cycle average of tags in use -system.l2c.tags.total_refs 446453 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 198047 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.254278 # Average number of references to valid blocks. +system.l2c.tags.replacements 131732 # number of replacements +system.l2c.tags.tagsinuse 63242.215263 # Cycle average of tags in use +system.l2c.tags.total_refs 477411 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195803 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.438221 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12007.955719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 82.059666 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9722.429733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3069.037039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34559.641433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.516745 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1816.838650 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 555.114204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2192.374249 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.183227 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001252 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.148353 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.527338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.027723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033453 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976791 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30866 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33781 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 78 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5648 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2821 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30623 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.470978 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001251 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.515457 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5802831 # Number of tag accesses -system.l2c.tags.data_accesses 5802831 # Number of data accesses -system.l2c.Writeback_hits::writebacks 230256 # number of Writeback hits -system.l2c.Writeback_hits::total 230256 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3083 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 464 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3547 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 148 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 197 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4599 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5978 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 467 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 52086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 51828 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 50532 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 70 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 10095 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 4893 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3282 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 173352 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 467 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 52086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 56427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 50532 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 70 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10095 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3282 # number of demand (read+write) hits -system.l2c.demand_hits::total 179330 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 467 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits -system.l2c.overall_hits::cpu0.inst 52086 # number of overall hits -system.l2c.overall_hits::cpu0.data 56427 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 50532 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 70 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10095 # number of overall hits -system.l2c.overall_hits::cpu1.data 6272 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3282 # number of overall hits -system.l2c.overall_hits::total 179330 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9481 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2162 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11643 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 497 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1197 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1694 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11009 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7938 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18947 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 137 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 13388.492550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 80.863480 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9301.116819 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2921.908325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33330.007466 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.315084 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1918.660878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 548.645359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1744.165016 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.204292 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.141924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044585 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.508576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029276 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965000 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29065 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34948 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4807 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 58 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31196 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.443497 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000885 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.533264 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6405394 # Number of tag accesses +system.l2c.tags.data_accesses 6405394 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 267195 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 267195 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 33822 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2200 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 36022 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2272 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 961 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3233 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4378 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1264 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5642 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 435 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 108 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 47657 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 51900 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49884 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 81 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 9621 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5534 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3616 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 168852 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 47657 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 56278 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 49884 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 81 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 9621 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6798 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3616 # number of demand (read+write) hits +system.l2c.demand_hits::total 174494 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 435 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 108 # number of overall hits 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number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22412 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20747 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 133466 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3021 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9531 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5720 # number of demand (read+write) misses -system.l2c.demand_misses::total 195051 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 137 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22638 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 21347 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133540 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3146 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9771 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5301 # number of demand (read+write) misses +system.l2c.demand_misses::total 195896 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 140 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22412 # number of overall misses -system.l2c.overall_misses::cpu0.data 20747 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 133466 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 16 # number of 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+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.009174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.321929 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.275002 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.129032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.245868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.589716 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.594482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.528851 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.243478 # mshr miss rate for overall accesses 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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75191.096178 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75507.917750 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77408.602151 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76636.504254 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76918.507609 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137998.651705 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122013.339860 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 131357.273606 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127225 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127131.303276 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130152.542373 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 138273.544253 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120620.592134 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.600345 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123187.639376 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127372.812500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137420.742603 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127225 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130923.357664 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120620.592134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132916.920410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123187.639376 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122890.952820 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 136811.953365 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127225 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120609.033295 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133524.173335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 141539.933451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124424.378109 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123430.227678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159976.647378 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 137665.594300 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172134.394507 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99366.068286 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160713.619307 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155010.758304 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 78049.520767 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149556.028208 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113328.735632 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164040.107304 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106058.035714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90084.558824 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 155773.635439 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120620.592134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132916.920410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140691.392205 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126166.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123187.639376 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122890.952820 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157896.665158 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 136811.953365 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183179.415161 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104915.405314 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169993.507491 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165294.760661 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84314.798788 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159264.837608 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174725.348868 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95905.563967 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165242.219717 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38908 # Transaction distribution -system.membus.trans_dist::ReadResp 215242 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::Writeback 138211 # Transaction distribution -system.membus.trans_dist::CleanEvict 17281 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73717 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40307 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13440 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 39445 # Transaction distribution -system.membus.trans_dist::ReadExResp 18844 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176334 # Transaction distribution +system.membus.trans_dist::ReadReq 39045 # Transaction distribution +system.membus.trans_dist::ReadResp 215502 # Transaction distribution +system.membus.trans_dist::WriteReq 31036 # Transaction distribution +system.membus.trans_dist::WriteResp 31036 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138282 # Transaction distribution +system.membus.trans_dist::CleanEvict 17700 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74095 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40637 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14846 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40045 # Transaction distribution +system.membus.trans_dist::ReadExResp 19551 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176457 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 674810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 796498 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 905407 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 801187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 910112 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19258908 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19450490 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21767610 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 121785 # Total snoops (count) -system.membus.snoop_fanout::samples 591590 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28452 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19316644 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19509252 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21827396 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120950 # Total snoops (count) +system.membus.snoop_fanout::samples 593773 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 591590 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 593773 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 591590 # Request fanout histogram -system.membus.reqLayer0.occupancy 91392000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 593773 # Request fanout histogram +system.membus.reqLayer0.occupancy 91220498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 24328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11844500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12309500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1004304747 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1009592824 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1168943229 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1175000125 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64602498 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64118281 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2949,52 +2948,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 982687 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 493902 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 158313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 22110 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21385 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 725 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 38912 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 507516 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 368484 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 106099 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77161 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40652 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117813 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51062 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51062 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 468619 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 1045381 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 564426 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 153843 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20977 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 974 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 39048 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 502086 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31036 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31036 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 405496 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110001 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43870 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153871 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51160 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51160 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 463053 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1216476 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 257070 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1473546 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35115318 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4064004 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39179322 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 452154 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1258731 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.293892 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.456806 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1307707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 268101 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1575808 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36951502 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337654 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41289156 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 448414 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 942644 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.339212 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475620 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 889525 70.67% 70.67% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 368481 29.27% 99.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 725 0.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 623862 66.18% 66.18% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 317808 33.71% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 974 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1258731 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 836264644 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 942644 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 904161512 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342619 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 685711951 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 693453750 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 211221475 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 213389277 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 481a34a0c..e97d068c7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858301 # Number of seconds simulated -sim_ticks 2858301146500 # Number of ticks simulated -final_tick 2858301146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858555 # Number of seconds simulated +sim_ticks 2858554679500 # Number of ticks simulated +final_tick 2858554679500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158663 # Simulator instruction rate (inst/s) -host_op_rate 191838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4049033168 # Simulator tick rate (ticks/s) -host_mem_usage 629392 # Number of bytes of host memory used -host_seconds 705.92 # Real time elapsed on the host -sim_insts 112003872 # Number of instructions simulated -sim_ops 135422492 # Number of ops (including micro ops) simulated +host_inst_rate 162796 # Simulator instruction rate (inst/s) +host_op_rate 196833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4157408079 # Simulator tick rate (ticks/s) +host_mem_usage 628580 # Number of bytes of host memory used +host_seconds 687.58 # Real time elapsed on the host +sim_insts 111935485 # Number of instructions simulated +sim_ops 135338943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7616 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1692928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9156716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9149804 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10858604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1692928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1692928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7945984 # Number of bytes written to this memory +system.physmem.bytes_read::total 10866540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7937280 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7963508 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 124 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7954804 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 119 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143487 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170187 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124156 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170311 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124020 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2776 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128401 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2664 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 592285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3203552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3200850 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3798971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 592285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 592285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2779967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6131 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2786098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2779967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3801411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2776676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2782806 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2776676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2664 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 592285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3209683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3206980 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170187 # Number of read requests accepted -system.physmem.writeReqs 128537 # Number of write requests accepted -system.physmem.readBursts 170187 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128537 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10884288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7975936 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10858604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7963508 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6584217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170311 # Number of read requests accepted +system.physmem.writeReqs 128401 # Number of write requests accepted +system.physmem.readBursts 170311 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128401 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10891264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7967296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10866540 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7954804 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40806 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10600 # Per bank write bursts -system.physmem.perBankRdBursts::1 10887 # Per bank write bursts -system.physmem.perBankRdBursts::2 11108 # Per bank write bursts -system.physmem.perBankRdBursts::3 10980 # Per bank write bursts -system.physmem.perBankRdBursts::4 13553 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 10585 # Per bank write bursts -system.physmem.perBankRdBursts::7 10816 # Per bank write bursts -system.physmem.perBankRdBursts::8 10327 # Per bank write bursts -system.physmem.perBankRdBursts::9 10604 # Per bank write bursts -system.physmem.perBankRdBursts::10 9912 # Per bank write bursts -system.physmem.perBankRdBursts::11 9123 # Per bank write bursts -system.physmem.perBankRdBursts::12 10363 # Per bank write bursts -system.physmem.perBankRdBursts::13 10770 # Per bank write bursts -system.physmem.perBankRdBursts::14 10067 # Per bank write bursts -system.physmem.perBankRdBursts::15 9962 # Per bank write bursts -system.physmem.perBankWrBursts::0 7842 # Per bank write bursts -system.physmem.perBankWrBursts::1 8249 # Per bank write bursts -system.physmem.perBankWrBursts::2 8721 # Per bank write bursts -system.physmem.perBankWrBursts::3 8464 # Per bank write bursts -system.physmem.perBankWrBursts::4 7420 # Per bank write bursts -system.physmem.perBankWrBursts::5 7583 # Per bank write bursts -system.physmem.perBankWrBursts::6 7625 # Per bank write bursts -system.physmem.perBankWrBursts::7 7909 # Per bank write bursts -system.physmem.perBankWrBursts::8 7872 # Per bank write bursts -system.physmem.perBankWrBursts::9 8104 # Per bank write bursts -system.physmem.perBankWrBursts::10 7451 # Per bank write bursts -system.physmem.perBankWrBursts::11 6976 # Per bank write bursts -system.physmem.perBankWrBursts::12 7788 # Per bank write bursts -system.physmem.perBankWrBursts::13 7975 # Per bank write bursts -system.physmem.perBankWrBursts::14 7387 # Per bank write bursts -system.physmem.perBankWrBursts::15 7258 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49408 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10771 # Per bank write bursts +system.physmem.perBankRdBursts::1 10784 # Per bank write bursts +system.physmem.perBankRdBursts::2 10887 # Per bank write bursts +system.physmem.perBankRdBursts::3 10717 # Per bank write bursts +system.physmem.perBankRdBursts::4 14062 # Per bank write bursts +system.physmem.perBankRdBursts::5 10208 # Per bank write bursts +system.physmem.perBankRdBursts::6 10996 # Per bank write bursts +system.physmem.perBankRdBursts::7 10949 # Per bank write bursts +system.physmem.perBankRdBursts::8 9936 # Per bank write bursts +system.physmem.perBankRdBursts::9 10239 # Per bank write bursts +system.physmem.perBankRdBursts::10 9937 # Per bank write bursts +system.physmem.perBankRdBursts::11 9167 # Per bank write bursts +system.physmem.perBankRdBursts::12 10278 # Per bank write bursts +system.physmem.perBankRdBursts::13 11186 # Per bank write bursts +system.physmem.perBankRdBursts::14 10249 # Per bank write bursts +system.physmem.perBankRdBursts::15 9810 # Per bank write bursts +system.physmem.perBankWrBursts::0 8068 # Per bank write bursts +system.physmem.perBankWrBursts::1 8140 # Per bank write bursts +system.physmem.perBankWrBursts::2 8529 # Per bank write bursts +system.physmem.perBankWrBursts::3 8260 # Per bank write bursts +system.physmem.perBankWrBursts::4 7653 # Per bank write bursts +system.physmem.perBankWrBursts::5 7417 # Per bank write bursts +system.physmem.perBankWrBursts::6 7934 # Per bank write bursts +system.physmem.perBankWrBursts::7 8022 # Per bank write bursts +system.physmem.perBankWrBursts::8 7566 # Per bank write bursts +system.physmem.perBankWrBursts::9 7724 # Per bank write bursts +system.physmem.perBankWrBursts::10 7504 # Per bank write bursts +system.physmem.perBankWrBursts::11 7051 # Per bank write bursts +system.physmem.perBankWrBursts::12 7682 # Per bank write bursts +system.physmem.perBankWrBursts::13 8291 # Per bank write bursts +system.physmem.perBankWrBursts::14 7536 # Per bank write bursts +system.physmem.perBankWrBursts::15 7112 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 2858300743000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2858554234000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169630 # Read request sizes (log2) +system.physmem.readPktSize::6 169754 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124020 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,159 +159,157 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2399 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 6060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6447 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 42 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.136640 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.409953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.199512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22530 36.57% 36.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14842 24.09% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6878 11.16% 71.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3579 5.81% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2575 4.18% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2036 3.30% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1091 1.77% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1049 1.70% 88.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 11.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61607 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.410058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.248357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6203 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.404893 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.124702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.856556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22378 36.48% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14856 24.22% 60.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6657 10.85% 71.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3691 6.02% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2584 4.21% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1979 3.23% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1099 1.79% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1109 1.81% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6994 11.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.377091 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.055211 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6215 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6204 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.087685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.454852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.723718 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5415 87.28% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 1.32% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 29 0.47% 89.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 170 2.74% 91.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.58% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 140 2.26% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.82% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.15% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.42% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.27% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.58% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.03% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.13% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6204 # Writes before turning the bus around for reads -system.physmem.totQLat 1827154250 # Total ticks spent queuing -system.physmem.totMemAccLat 5015910500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10743.73 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.029123 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.467033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.100027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5396 86.82% 86.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 102 1.64% 88.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.63% 89.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 172 2.77% 91.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 31 0.50% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.45% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.63% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.27% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 24 0.39% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 159 2.56% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.42% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.08% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6215 # Writes before turning the bus around for reads +system.physmem.totQLat 1812035750 # Total ticks spent queuing +system.physmem.totMemAccLat 5002835750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10648.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29493.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29398.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.50 # Average write queue length when enqueuing -system.physmem.readRowHits 139389 # Number of row buffer hits during reads -system.physmem.writeRowHits 93694 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.17 # Row buffer hit rate for writes -system.physmem.avgGap 9568366.60 # Average gap between requests -system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240959880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131476125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 693724200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 413508240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86986692810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638672097500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1913828291955 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.570205 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725916009250 # Time in different power states -system.physmem_0.memoryStateTime::REF 95444700000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.83 # Average write queue length when enqueuing +system.physmem.readRowHits 139556 # Number of row buffer hits during reads +system.physmem.writeRowHits 93759 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.30 # Row buffer hit rate for writes +system.physmem.avgGap 9569599.59 # Average gap between requests +system.physmem.pageHitRate 79.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 241731000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131896875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697117200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 414817200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86828058675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638965418000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913985654630 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.565069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726406946000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95453280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36932994500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36694429000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 224789040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122652750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 632790600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 394055280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186689833200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85302372735 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640149571250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913516064855 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.460970 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728391286000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95444700000 # Time in different power states +system.physmem_1.actEnergy 222037200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121151250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630247800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 391819680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186706615680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85116075930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640467157250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913655104790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.449434 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728919167500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95453280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34465013500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34182085000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -331,15 +329,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31040865 # Number of BP lookups -system.cpu.branchPred.condPredicted 16831531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2506988 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18486474 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13317466 # Number of BTB hits +system.cpu.branchPred.lookups 31017399 # Number of BP lookups +system.cpu.branchPred.condPredicted 16820647 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2503170 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18419836 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13303162 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.038973 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7868005 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1514854 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.221935 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7872052 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1510670 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -370,55 +368,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66489 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66489 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43580 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22909 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66489 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66489 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66489 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7766 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12735.320628 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10552.887084 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8498.851872 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7759 99.91% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7766 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 513949000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 513949000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 513949000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6383 82.19% 82.19% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1383 17.81% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7766 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66489 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 65808 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65808 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 42987 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22821 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65808 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65808 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7823 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12723.315863 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10567.827696 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8328.598591 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7817 99.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7823 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6431 82.21% 82.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1392 17.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7823 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65808 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66489 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7766 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65808 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7823 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7766 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74255 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7823 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73631 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24754555 # DTB read hits -system.cpu.dtb.read_misses 59253 # DTB read misses -system.cpu.dtb.write_hits 19441053 # DTB write hits -system.cpu.dtb.write_misses 7236 # DTB write misses +system.cpu.dtb.read_hits 24739501 # DTB read hits +system.cpu.dtb.read_misses 58797 # DTB read misses +system.cpu.dtb.write_hits 19434146 # DTB write hits +system.cpu.dtb.write_misses 7011 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1795 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1307 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1800 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 764 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24813808 # DTB read accesses -system.cpu.dtb.write_accesses 19448289 # DTB write accesses +system.cpu.dtb.perms_faults 763 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24798298 # DTB read accesses +system.cpu.dtb.write_accesses 19441157 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44195608 # DTB hits -system.cpu.dtb.misses 66489 # DTB misses -system.cpu.dtb.accesses 44262097 # DTB accesses +system.cpu.dtb.hits 44173647 # DTB hits +system.cpu.dtb.misses 65808 # DTB misses +system.cpu.dtb.accesses 44239455 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -448,36 +446,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5448 # Table walker walks requested -system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5128 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3191 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12717.173300 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10597.999219 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7372.723577 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2455 76.94% 76.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 735 23.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5439 # Table walker walks requested +system.cpu.itb.walker.walksShort 5439 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5120 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5439 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5439 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5439 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12910.175879 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10824.296487 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7389.330309 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2456 77.14% 77.14% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 727 22.83% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3191 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 513294500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 513294500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 513294500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2881 90.29% 90.29% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3191 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2874 90.26% 90.26% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5439 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5439 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3191 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3191 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8639 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57598121 # ITB inst hits -system.cpu.itb.inst_misses 5448 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8623 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57560838 # ITB inst hits +system.cpu.itb.inst_misses 5439 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -486,127 +484,127 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2979 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8499 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8472 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57603569 # ITB inst accesses -system.cpu.itb.hits 57598121 # DTB hits -system.cpu.itb.misses 5448 # DTB misses -system.cpu.itb.accesses 57603569 # DTB accesses -system.cpu.numCycles 332010047 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57566277 # ITB inst accesses +system.cpu.itb.hits 57560838 # DTB hits +system.cpu.itb.misses 5439 # DTB misses +system.cpu.itb.accesses 57566277 # DTB accesses +system.cpu.numCycles 333233745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112003872 # Number of instructions committed -system.cpu.committedOps 135422492 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7777324 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5384653012 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.964273 # CPI: cycles per instruction -system.cpu.ipc 0.337351 # IPC: instructions per cycle +system.cpu.committedInsts 111935485 # Number of instructions committed +system.cpu.committedOps 135338943 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7768370 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5383936377 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.977016 # CPI: cycles per instruction +system.cpu.ipc 0.335907 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed -system.cpu.tickCycles 227998615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104011432 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 840949 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.900791 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42597434 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 841461 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.623183 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 590729500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.900791 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999806 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed +system.cpu.tickCycles 228546607 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104687138 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 843126 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899809 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42573204 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843638 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.463829 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899809 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176149332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176149332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23058407 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23058407 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18275243 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18275243 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356879 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356879 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443776 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443776 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460246 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41333650 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41333650 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41690529 # number of overall hits -system.cpu.dcache.overall_hits::total 41690529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 492651 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 492651 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 547770 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 547770 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169693 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169693 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22295 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22295 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176066237 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176066237 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23041742 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23041742 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267850 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356487 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356487 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443903 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443903 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460330 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460330 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41309592 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41309592 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41666079 # number of overall hits +system.cpu.dcache.overall_hits::total 41666079 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 494543 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 494543 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 548727 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 548727 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169803 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169803 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22255 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22255 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1040421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1040421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1210114 # number of overall misses -system.cpu.dcache.overall_misses::total 1210114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8002189000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8002189000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35630203980 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35630203980 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292207000 # number of LoadLockedReq miss cycles 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rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019488 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15607.726806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15607.726806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64384.677363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64384.677363 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14121.169836 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14121.169836 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13929.274517 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13929.274517 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016925 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016925 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15636.527038 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15636.527038 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64181.630599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64181.630599 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.500091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 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Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60487009 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60487009 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54691304 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54691304 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54691304 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54691304 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54691304 # number of overall hits -system.cpu.icache.overall_hits::total 54691304 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897853 # number of demand (read+write) misses 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3490 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3490 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3490 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3490 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37593940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37593940500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37593940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37593940500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37593940500 # number of overall MSHR miss cycles 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mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129192.979943 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129192.979943 # average overall mshr uncacheable latency +system.cpu.icache.writebacks::writebacks 2897280 # number of writebacks +system.cpu.icache.writebacks::total 2897280 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897804 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897804 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897804 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2897804 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2897804 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2897804 # number of overall MSHR misses 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37596628000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050351 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050351 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050351 # mshr miss rate for overall accesses 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of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4767951000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 427218000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656258500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083476500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001575 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982406 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982406 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007928 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007928 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.441961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.441961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007915 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025846 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025846 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044041 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000216 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171957 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044041 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125876 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70744.875549 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70744.875549 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131266.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70755.482456 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70755.482456 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118205.063870 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118205.063870 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120864.906630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120864.906630 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122468.814525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122468.814525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118126.602050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118126.602050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120631.926582 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120631.926582 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122428.263482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122428.263482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125903.225806 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131340.336134 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120864.906630 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118617.575945 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118929.787601 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178237.262272 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 171723.308683 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162059.928217 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162059.928217 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113624.068768 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170636.993068 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167438.087812 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120631.926582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118546.138204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118839.765779 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189152.184388 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180996.919153 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172852.051914 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172852.051914 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181494.336955 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177400.907534 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 7509435 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770131 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58870 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 575 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 575 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 7513660 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772219 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58915 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 134592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3578420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 822692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2989768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 824300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2845639 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 144382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295719 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295719 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 545999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 547664 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2639755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15227 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11465064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185683904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98756893 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288828 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284748229 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192861 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7812074 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.136054 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8648746 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2646408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11470512 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367819456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99009385 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286196 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 467133521 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192542 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4075210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021724 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145782 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7664687 98.11% 98.11% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 147387 1.89% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3986679 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 88531 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7812074 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4533598000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 377377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4075210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7434516500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4352382759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4352877441 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1308632806 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312009118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10576000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10561994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89410974 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88663416 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1213,63 +1218,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46504000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 89000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 569500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6052000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 33698500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186368011 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186339520 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.036757 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036928 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274667845000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036757 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274875272000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036928 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064808 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064808 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1283,14 +1288,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29104877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29104877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697807134 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697807134 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29104877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29104877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29104877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29104877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29051377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29051377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4719366143 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4719366143 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29051377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29051377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29051377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29051377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1307,19 +1312,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124379.816239 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124379.816239 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129687.696941 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129687.696941 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124379.816239 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124379.816239 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124379.816239 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124151.183761 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124151.183761 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130282.855096 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130282.855096 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124151.183761 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124151.183761 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124151.183761 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 731 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 70 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.442857 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1333,14 +1338,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17404877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17404877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886607134 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886607134 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17404877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17404877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17404877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17404877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17351377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17351377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2908166143 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2908166143 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17351377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17351377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17351377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17351377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1349,68 +1354,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74379.816239 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74379.816239 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79687.696941 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79687.696941 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74379.816239 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74379.816239 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74151.183761 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74151.183761 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80282.855096 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80282.855096 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74151.183761 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74151.183761 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34618 # Transaction distribution -system.membus.trans_dist::ReadResp 71995 # Transaction distribution -system.membus.trans_dist::WriteReq 27583 # Transaction distribution -system.membus.trans_dist::WriteResp 27583 # Transaction distribution -system.membus.trans_dist::Writeback 124156 # Transaction distribution -system.membus.trans_dist::CleanEvict 8653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4582 # Transaction distribution +system.membus.trans_dist::ReadReq 34893 # Transaction distribution +system.membus.trans_dist::ReadResp 72333 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124020 # Transaction distribution +system.membus.trans_dist::CleanEvict 8585 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4599 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4584 # Transaction distribution -system.membus.trans_dist::ReadExReq 129275 # Transaction distribution -system.membus.trans_dist::ReadExResp 129275 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37377 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4601 # Transaction distribution +system.membus.trans_dist::ReadExReq 129063 # Transaction distribution +system.membus.trans_dist::ReadExResp 129063 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37440 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562725 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455241 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562809 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668765 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16504224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16668009 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18985885 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18985129 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 402707 # Request fanout histogram +system.membus.snoop_fanout::samples 402632 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402707 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402707 # Request fanout histogram -system.membus.reqLayer0.occupancy 87547000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402632 # Request fanout histogram +system.membus.reqLayer0.occupancy 87539000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 878616291 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 878086902 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 998538415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 999035643 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64594078 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64196432 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 51e8b32a5..ce335443d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832619 # Number of seconds simulated -sim_ticks 2832618668500 # Number of ticks simulated -final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832918 # Number of seconds simulated +sim_ticks 2832917624000 # Number of ticks simulated +final_tick 2832917624000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65632 # Simulator instruction rate (inst/s) -host_op_rate 79607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643300725 # Simulator tick rate (ticks/s) -host_mem_usage 630388 # Number of bytes of host memory used -host_seconds 1723.74 # Real time elapsed on the host -sim_insts 113133035 # Number of instructions simulated -sim_ops 137220830 # Number of ops (including micro ops) simulated +host_inst_rate 67788 # Simulator instruction rate (inst/s) +host_op_rate 82221 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1698232616 # Simulator tick rate (ticks/s) +host_mem_usage 630604 # Number of bytes of host memory used +host_seconds 1668.16 # Real time elapsed on the host +sim_insts 113081477 # Number of instructions simulated +sim_ops 137157144 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9392488 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory +system.physmem.bytes_read::total 10711336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8002368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8019892 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147278 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125037 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129418 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 464550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3315482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3781026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2824780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2830965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2824780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3321668 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170127 # Number of read requests accepted -system.physmem.writeReqs 129798 # Number of write requests accepted -system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6611992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170133 # Number of read requests accepted +system.physmem.writeReqs 129418 # Number of write requests accepted +system.physmem.readBursts 170133 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129418 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10877696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10816 # Total number of bytes read from write queue +system.physmem.bytesWritten 8031936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10711400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8019892 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 169 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11277 # Per bank write bursts -system.physmem.perBankRdBursts::1 10595 # Per bank write bursts -system.physmem.perBankRdBursts::2 11086 # Per bank write bursts -system.physmem.perBankRdBursts::3 11282 # Per bank write bursts -system.physmem.perBankRdBursts::4 12957 # Per bank write bursts -system.physmem.perBankRdBursts::5 9975 # Per bank write bursts -system.physmem.perBankRdBursts::6 10510 # Per bank write bursts -system.physmem.perBankRdBursts::7 10855 # Per bank write bursts -system.physmem.perBankRdBursts::8 10363 # Per bank write bursts -system.physmem.perBankRdBursts::9 10082 # Per bank write bursts -system.physmem.perBankRdBursts::10 10269 # Per bank write bursts -system.physmem.perBankRdBursts::11 9303 # Per bank write bursts -system.physmem.perBankRdBursts::12 9940 # Per bank write bursts -system.physmem.perBankRdBursts::13 11053 # Per bank write bursts -system.physmem.perBankRdBursts::14 10302 # Per bank write bursts -system.physmem.perBankRdBursts::15 10142 # Per bank write bursts -system.physmem.perBankWrBursts::0 8501 # Per bank write bursts -system.physmem.perBankWrBursts::1 7938 # Per bank write bursts -system.physmem.perBankWrBursts::2 8637 # Per bank write bursts -system.physmem.perBankWrBursts::3 8770 # Per bank write bursts -system.physmem.perBankWrBursts::4 7610 # Per bank write bursts -system.physmem.perBankWrBursts::5 7376 # Per bank write bursts -system.physmem.perBankWrBursts::6 7709 # Per bank write bursts -system.physmem.perBankWrBursts::7 8071 # Per bank write bursts -system.physmem.perBankWrBursts::8 7782 # Per bank write bursts -system.physmem.perBankWrBursts::9 7594 # Per bank write bursts -system.physmem.perBankWrBursts::10 7680 # Per bank write bursts -system.physmem.perBankWrBursts::11 6982 # Per bank write bursts -system.physmem.perBankWrBursts::12 7590 # Per bank write bursts -system.physmem.perBankWrBursts::13 8396 # Per bank write bursts -system.physmem.perBankWrBursts::14 7757 # Per bank write bursts -system.physmem.perBankWrBursts::15 7487 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48557 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11298 # Per bank write bursts +system.physmem.perBankRdBursts::1 10506 # Per bank write bursts +system.physmem.perBankRdBursts::2 10925 # Per bank write bursts +system.physmem.perBankRdBursts::3 11199 # Per bank write bursts +system.physmem.perBankRdBursts::4 12883 # Per bank write bursts +system.physmem.perBankRdBursts::5 10202 # Per bank write bursts +system.physmem.perBankRdBursts::6 10845 # Per bank write bursts +system.physmem.perBankRdBursts::7 11219 # Per bank write bursts +system.physmem.perBankRdBursts::8 10577 # Per bank write bursts +system.physmem.perBankRdBursts::9 10527 # Per bank write bursts +system.physmem.perBankRdBursts::10 10037 # Per bank write bursts +system.physmem.perBankRdBursts::11 8948 # Per bank write bursts +system.physmem.perBankRdBursts::12 9970 # Per bank write bursts +system.physmem.perBankRdBursts::13 10631 # Per bank write bursts +system.physmem.perBankRdBursts::14 9988 # Per bank write bursts +system.physmem.perBankRdBursts::15 10209 # Per bank write bursts +system.physmem.perBankWrBursts::0 8496 # Per bank write bursts +system.physmem.perBankWrBursts::1 7860 # Per bank write bursts +system.physmem.perBankWrBursts::2 8364 # Per bank write bursts +system.physmem.perBankWrBursts::3 8532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7663 # Per bank write bursts +system.physmem.perBankWrBursts::5 7568 # Per bank write bursts +system.physmem.perBankWrBursts::6 8029 # Per bank write bursts +system.physmem.perBankWrBursts::7 8274 # Per bank write bursts +system.physmem.perBankWrBursts::8 8070 # Per bank write bursts +system.physmem.perBankWrBursts::9 7909 # Per bank write bursts +system.physmem.perBankWrBursts::10 7508 # Per bank write bursts +system.physmem.perBankWrBursts::11 6646 # Per bank write bursts +system.physmem.perBankWrBursts::12 7551 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7465 # Per bank write bursts +system.physmem.perBankWrBursts::15 7558 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2832618457500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2832917392000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166575 # Read request sizes (log2) +system.physmem.readPktSize::6 166581 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125037 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,155 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.281406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.810971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.663684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23300 37.49% 37.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14989 24.12% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6559 10.55% 72.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3523 5.67% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2511 4.04% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1609 2.59% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.56% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1065 1.71% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6997 11.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62145 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.121768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.971651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6265 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6266 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.028567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.454463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.210745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5460 87.14% 87.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.76% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.48% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.68% 92.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.41% 92.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.19% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.85% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.24% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.18% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.34% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.63% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 23 0.37% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads -system.physmem.totQLat 2109686750 # Total ticks spent queuing -system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.19% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6266 # Writes before turning the bus around for reads +system.physmem.totQLat 2116809750 # Total ticks spent queuing +system.physmem.totMemAccLat 5303634750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12454.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31204.46 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing -system.physmem.readRowHits 139766 # Number of row buffer hits during reads -system.physmem.writeRowHits 93986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes -system.physmem.avgGap 9444422.63 # Average gap between requests -system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.462100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states -system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 139542 # Number of row buffer hits during reads +system.physmem.writeRowHits 93775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 9457212.27 # Average gap between requests +system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246546720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134524500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 694792800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419813280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83588992920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626422631000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896539228820 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.466691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705562728250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32757782250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.364017 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states -system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem_1.actEnergy 223269480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121823625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630918600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 393420240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81878542335 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627923026250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896202928130 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.347979 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2708066096500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30247332250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -327,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46909632 # Number of BP lookups -system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits +system.cpu.branchPred.lookups 46858822 # Number of BP lookups +system.cpu.branchPred.condPredicted 24018425 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233385 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29501817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21322160 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.274057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11724285 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33905 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -366,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9696 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9696 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9696 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9696 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9696 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 9701 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9701 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9701 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9701 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9701 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6227 82.67% 82.67% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1305 17.33% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7532 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9696 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 6238 82.77% 82.77% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1299 17.23% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7537 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9701 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9696 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7532 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9701 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7537 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7532 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17228 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7537 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17238 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24584215 # DTB read hits -system.cpu.checker.dtb.read_misses 8281 # DTB read misses -system.cpu.checker.dtb.write_hits 19636610 # DTB write hits -system.cpu.checker.dtb.write_misses 1415 # DTB write misses +system.cpu.checker.dtb.read_hits 24572028 # DTB read hits +system.cpu.checker.dtb.read_misses 8280 # DTB read misses +system.cpu.checker.dtb.write_hits 19630755 # DTB write hits +system.cpu.checker.dtb.write_misses 1421 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24592496 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19638025 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24580308 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19632176 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44220825 # DTB hits -system.cpu.checker.dtb.misses 9696 # DTB misses -system.cpu.checker.dtb.accesses 44230521 # DTB accesses +system.cpu.checker.dtb.hits 44202783 # DTB hits +system.cpu.checker.dtb.misses 9701 # DTB misses +system.cpu.checker.dtb.accesses 44212484 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -452,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115833137 # ITB inst hits +system.cpu.checker.itb.inst_hits 115778479 # ITB inst hits system.cpu.checker.itb.inst_misses 4825 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -469,11 +470,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115837962 # ITB inst accesses -system.cpu.checker.itb.hits 115833137 # DTB hits +system.cpu.checker.itb.inst_accesses 115783304 # ITB inst accesses +system.cpu.checker.itb.hits 115778479 # DTB hits system.cpu.checker.itb.misses 4825 # DTB misses -system.cpu.checker.itb.accesses 115837962 # DTB accesses -system.cpu.checker.numCycles 139072975 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115783304 # DTB accesses +system.cpu.checker.numCycles 139006189 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -505,79 +506,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 71741 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 71435 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71435 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29241 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22400 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19794 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 426.153638 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2576.445985 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 49864 96.56% 96.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.13% 97.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.02% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 340 0.66% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.43% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9159.086359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8173.463802 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17339 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.616564 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493575 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131327318816 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37570000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7000000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6185500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1198500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6381 82.69% 82.69% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1336 17.31% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7717 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71435 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71435 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7717 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7717 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79152 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25458814 # DTB read hits -system.cpu.dtb.read_misses 61805 # DTB read misses -system.cpu.dtb.write_hits 19912938 # DTB write hits -system.cpu.dtb.write_misses 9936 # DTB write misses +system.cpu.dtb.read_hits 25445516 # DTB read hits +system.cpu.dtb.read_misses 61525 # DTB read misses +system.cpu.dtb.write_hits 19906341 # DTB write hits +system.cpu.dtb.write_misses 9910 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25520619 # DTB read accesses -system.cpu.dtb.write_accesses 19922874 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25507041 # DTB read accesses +system.cpu.dtb.write_accesses 19916251 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45371752 # DTB hits -system.cpu.dtb.misses 71741 # DTB misses -system.cpu.dtb.accesses 45443493 # DTB accesses +system.cpu.dtb.hits 45351857 # DTB hits +system.cpu.dtb.misses 71435 # DTB misses +system.cpu.dtb.accesses 45423292 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -607,54 +613,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11944 # Table walker walks requested -system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated +system.cpu.itb.walker.walks 11899 # Table walker walks requested +system.cpu.itb.walker.walksShort 11899 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3941 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 616.629560 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2880.318774 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11122 95.24% 95.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.25% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 32 0.27% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12870.386024 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8688.844550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.26% 73.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 892 25.13% 98.39% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 55 1.55% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.962955 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.189019 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 889977000 3.71% 3.71% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 23117314916 96.29% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3008 90.38% 90.38% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 320 9.62% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11899 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11899 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66274552 # ITB inst hits -system.cpu.itb.inst_misses 11944 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15227 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66219818 # ITB inst hits +system.cpu.itb.inst_misses 11899 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -663,143 +670,143 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66286496 # ITB inst accesses -system.cpu.itb.hits 66274552 # DTB hits -system.cpu.itb.misses 11944 # DTB misses -system.cpu.itb.accesses 66286496 # DTB accesses -system.cpu.numCycles 277645869 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66231717 # ITB inst accesses +system.cpu.itb.hits 66219818 # DTB hits +system.cpu.itb.misses 11899 # DTB misses +system.cpu.itb.accesses 66231717 # DTB accesses +system.cpu.numCycles 278809396 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104752228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184594753 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46858822 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33046445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161837102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6149420 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189977 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 357687 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 560902 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66220013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1133469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5179 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.831431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.217897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171565839 63.36% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29222654 10.79% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14067780 5.20% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55926286 20.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168068 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77849645 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121907615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64584092 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3844418 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2596789 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423202 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486322 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157325754 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3698413 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2596789 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83693975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11775859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76672657 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62585691 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33457588 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146699029 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 957260 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 452831 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63761 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16550 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30707740 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150373398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678238170 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164317610 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141712294 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8661101 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2840653 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644485 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26394295 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21292545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1689185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2215742 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143439670 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121732 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143229007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8404254 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14686510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125844 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270782559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.528945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865530 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182544969 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45137079 16.67% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32020155 11.83% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10269839 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810484 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270782559 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7336568 32.74% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631848 25.13% 57.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9441706 42.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95930740 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113813 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -823,101 +830,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26175663 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20997878 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued -system.cpu.iq.rate 0.516124 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143229007 # Type of FU issued +system.cpu.iq.rate 0.513717 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22410154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156464 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579885434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153971015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140120635 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165613479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 322744 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1495175 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 703988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2596789 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1243570 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 532137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145762333 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26394295 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21292545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096246 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17995 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 497968 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317449 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788645 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142286885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25773498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 870795 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200573 # number of nop insts executed -system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed -system.cpu.iew.exec_branches 26519669 # Number of branches executed -system.cpu.iew.exec_stores 20875979 # Number of stores executed -system.cpu.iew.exec_rate 0.512728 # Inst execution rate -system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271886 # num instructions producing a value -system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value +system.cpu.iew.exec_nop 200931 # number of nop insts executed +system.cpu.iew.exec_refs 46642508 # number of memory reference insts executed +system.cpu.iew.exec_branches 26501737 # Number of branches executed +system.cpu.iew.exec_stores 20869010 # Number of stores executed +system.cpu.iew.exec_rate 0.510337 # Inst execution rate +system.cpu.iew.wb_sent 141900432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140132002 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63223126 # num instructions producing a value +system.cpu.iew.wb_consumers 95712973 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back +system.cpu.iew.wb_rate 0.502609 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660549 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7603118 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995888 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755464 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267848804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.512648 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.117834 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194453826 72.60% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43232556 16.14% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15468323 5.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4394328 1.64% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6341907 2.37% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1685586 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800919 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412081 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059278 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113287940 # Number of instructions committed -system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267848804 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113236382 # Number of instructions committed +system.cpu.commit.committedOps 137312049 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45505753 # Number of memory references committed -system.cpu.commit.loads 24911268 # Number of loads committed -system.cpu.commit.membars 814898 # Number of memory barriers committed -system.cpu.commit.branches 26034583 # Number of branches committed +system.cpu.commit.refs 45487677 # Number of memory references committed +system.cpu.commit.loads 24899120 # Number of loads committed +system.cpu.commit.membars 814929 # Number of memory barriers committed +system.cpu.commit.branches 26016406 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. -system.cpu.commit.function_calls 4887749 # Number of function calls committed. +system.cpu.commit.int_insts 120142081 # Number of committed integer instructions. +system.cpu.commit.function_calls 4881652 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91703052 66.78% 66.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112745 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -941,501 +948,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24899120 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20588557 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction -system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 388465780 # The number of ROB reads -system.cpu.rob.rob_writes 292930075 # The number of ROB writes -system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113133035 # Number of Instructions Simulated -system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads -system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155797969 # number of integer regfile reads -system.cpu.int_regfile_writes 88612712 # number of integer regfile writes -system.cpu.fp_regfile_reads 9524 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137312049 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059278 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389547304 # The number of ROB reads +system.cpu.rob.rob_writes 292761659 # The number of ROB writes +system.cpu.timesIdled 892855 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8026837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387025853 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113081477 # Number of Instructions Simulated +system.cpu.committedOps 137157144 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.465562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.465562 # CPI: Total CPI of All Threads +system.cpu.ipc 0.405587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.405587 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155726558 # number of integer regfile reads +system.cpu.int_regfile_writes 88564581 # number of integer regfile writes +system.cpu.fp_regfile_reads 9527 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502896978 # number of cc regfile reads -system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes -system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes -system.cpu.dcache.tags.replacements 840044 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 502647576 # number of cc regfile reads +system.cpu.cc_regfile_writes 53157224 # number of cc regfile writes +system.cpu.misc_regfile_reads 348272878 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521665 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837515 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40092431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838027 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.841455 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage 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-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 273000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 273000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26368126969 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26368126969 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019107 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019107 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126808000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126808000 # number of LoadLockedReq MSHR miss cycles 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 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-system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits 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miss cycles -system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66271739 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029898 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029898 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029898 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029898 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029898 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029898 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14197.629415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14197.629415 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4834 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68104377 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68104377 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64237730 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64237730 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64237730 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64237730 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64237730 # number of overall hits +system.cpu.icache.overall_hits::total 64237730 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1979279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1979279 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1979279 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1979279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1979279 # number of overall misses +system.cpu.icache.overall_misses::total 1979279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28148050491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28148050491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28148050491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28148050491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28148050491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28148050491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66217009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66217009 # number of ReadReq accesses(hits+misses) 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+system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.946108 # average number of cycles each access was blocked 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for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987277 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024466 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024466 # mshr miss rate for ReadSharedReq accesses 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ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2710500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1060500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3771000 # number of ReadReq MSHR miss cycles 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miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17919501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20349262000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888077000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6228194000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644958000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10985075000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456330 # mshr miss rate for ReadExReq accesses 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# mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060442 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5484076 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758688 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47112 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 127589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556141 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194580 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 820637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1846839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8416591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239034368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98344937 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 337643277 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 197136 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158851 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2973765 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 79083 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400072997 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834880345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1303595064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19421986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74092896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30172 # Transaction distribution -system.iobus.trans_dist::ReadResp 30172 # Transaction distribution +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1653,9 +1667,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1678,207 +1692,209 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 647500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6192000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 167000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 33054500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186395016 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 1.005392 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 256608771000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005392 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062837 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062837 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328023 # Number of tag accesses -system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses -system.iocache.ReadReq_misses::total 223 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses -system.iocache.demand_misses::total 223 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 223 # number of overall misses -system.iocache.overall_misses::total 223 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31311876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31311876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715518140 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715518140 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31311876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31311876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31311876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31311876 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125750.506024 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 725 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 77 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.415584 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18861876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18861876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18861876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34133 # Transaction distribution -system.membus.trans_dist::ReadResp 67584 # Transaction distribution +system.membus.trans_dist::ReadResp 67565 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::Writeback 125417 # Transaction distribution -system.membus.trans_dist::CleanEvict 7628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.membus.trans_dist::WritebackDirty 125037 # Transaction distribution +system.membus.trans_dist::CleanEvict 7766 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution -system.membus.trans_dist::ReadExReq 133608 # Transaction distribution -system.membus.trans_dist::ReadExResp 133608 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution +system.membus.trans_dist::ReadExReq 133659 # Transaction distribution +system.membus.trans_dist::ReadExResp 133659 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33433 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455099 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671495 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 487 # Total snoops (count) -system.membus.snoop_fanout::samples 402837 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16416028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16579433 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18894633 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 513 # Total snoops (count) +system.membus.snoop_fanout::samples 402650 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402650 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402837 # Request fanout histogram -system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402650 # Request fanout histogram +system.membus.reqLayer0.occupancy 83677500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1748500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 874312374 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988164899 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64093300 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 1b6a9683d..787619867 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627261 # Number of seconds simulated -sim_ticks 2627260787000 # Number of ticks simulated -final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.837504 # Number of seconds simulated +sim_ticks 2837504217500 # Number of ticks simulated +final_tick 2837504217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73269 # Simulator instruction rate (inst/s) -host_op_rate 88893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1598642516 # Simulator tick rate (ticks/s) -host_mem_usage 609448 # Number of bytes of host memory used -host_seconds 1643.43 # Real time elapsed on the host -sim_insts 120413300 # Number of instructions simulated -sim_ops 146090184 # Number of ops (including micro ops) simulated +host_inst_rate 89459 # Simulator instruction rate (inst/s) +host_op_rate 108491 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2108642938 # Simulator tick rate (ticks/s) +host_mem_usage 665360 # Number of bytes of host memory used +host_seconds 1345.65 # Real time elapsed on the host +sim_insts 120381204 # Number of instructions simulated +sim_ops 145991739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1139008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1190376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8167488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1282472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 326368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 665684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 594880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 172400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 575316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 374464 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12087580 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1139008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 326368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1465376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8694784 # Number of bytes written to this memory +system.physmem.bytes_read::total 12134316 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 172400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1470960 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8568768 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8712348 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20044 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 127617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8586332 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5167 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5851 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 191724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135856 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192455 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133887 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140247 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 433534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 453086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3108747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 253376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 226426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4600830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 433534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3309448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6670 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3316134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3309448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 433534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 459756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3108747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 253391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 226426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7916964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 191724 # Number of read requests accepted -system.physmem.writeReqs 140247 # Number of write requests accepted -system.physmem.readBursts 191724 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140247 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12260288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8725248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12087580 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8712348 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 138278 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 457642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 451972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2970114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 202754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4276405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 457642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3019826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3026016 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3019826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 457642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 458148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2970114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 202768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7302420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 192456 # Number of read requests accepted +system.physmem.writeReqs 138278 # Number of write requests accepted +system.physmem.readBursts 192456 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 138278 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12307136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9984 # Total number of bytes read from write queue +system.physmem.bytesWritten 8599232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12134380 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8586332 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 50731 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11367 # Per bank write bursts -system.physmem.perBankRdBursts::1 11306 # Per bank write bursts -system.physmem.perBankRdBursts::2 12534 # Per bank write bursts -system.physmem.perBankRdBursts::3 11925 # Per bank write bursts -system.physmem.perBankRdBursts::4 14392 # Per bank write bursts -system.physmem.perBankRdBursts::5 11995 # Per bank write bursts -system.physmem.perBankRdBursts::6 12528 # Per bank write bursts -system.physmem.perBankRdBursts::7 12413 # Per bank write bursts -system.physmem.perBankRdBursts::8 12465 # Per bank write bursts -system.physmem.perBankRdBursts::9 12343 # Per bank write bursts -system.physmem.perBankRdBursts::10 12048 # Per bank write bursts -system.physmem.perBankRdBursts::11 11291 # Per bank write bursts -system.physmem.perBankRdBursts::12 11598 # Per bank write bursts -system.physmem.perBankRdBursts::13 11714 # Per bank write bursts -system.physmem.perBankRdBursts::14 10851 # Per bank write bursts -system.physmem.perBankRdBursts::15 10797 # Per bank write bursts -system.physmem.perBankWrBursts::0 8020 # Per bank write bursts -system.physmem.perBankWrBursts::1 8176 # Per bank write bursts -system.physmem.perBankWrBursts::2 9316 # Per bank write bursts -system.physmem.perBankWrBursts::3 8567 # Per bank write bursts -system.physmem.perBankWrBursts::4 8317 # Per bank write bursts -system.physmem.perBankWrBursts::5 8617 # Per bank write bursts -system.physmem.perBankWrBursts::6 9080 # Per bank write bursts -system.physmem.perBankWrBursts::7 8981 # Per bank write bursts -system.physmem.perBankWrBursts::8 9059 # Per bank write bursts -system.physmem.perBankWrBursts::9 8883 # Per bank write bursts -system.physmem.perBankWrBursts::10 8732 # Per bank write bursts -system.physmem.perBankWrBursts::11 8494 # Per bank write bursts -system.physmem.perBankWrBursts::12 8573 # Per bank write bursts -system.physmem.perBankWrBursts::13 8275 # Per bank write bursts -system.physmem.perBankWrBursts::14 7766 # Per bank write bursts -system.physmem.perBankWrBursts::15 7476 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 65662 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11960 # Per bank write bursts +system.physmem.perBankRdBursts::1 11050 # Per bank write bursts +system.physmem.perBankRdBursts::2 12052 # Per bank write bursts +system.physmem.perBankRdBursts::3 12058 # Per bank write bursts +system.physmem.perBankRdBursts::4 14137 # Per bank write bursts +system.physmem.perBankRdBursts::5 12072 # Per bank write bursts +system.physmem.perBankRdBursts::6 12490 # Per bank write bursts +system.physmem.perBankRdBursts::7 12293 # Per bank write bursts +system.physmem.perBankRdBursts::8 12129 # Per bank write bursts +system.physmem.perBankRdBursts::9 11971 # Per bank write bursts +system.physmem.perBankRdBursts::10 11835 # Per bank write bursts +system.physmem.perBankRdBursts::11 10924 # Per bank write bursts +system.physmem.perBankRdBursts::12 11792 # Per bank write bursts +system.physmem.perBankRdBursts::13 12532 # Per bank write bursts +system.physmem.perBankRdBursts::14 11740 # Per bank write bursts +system.physmem.perBankRdBursts::15 11264 # Per bank write bursts +system.physmem.perBankWrBursts::0 8435 # Per bank write bursts +system.physmem.perBankWrBursts::1 7998 # Per bank write bursts +system.physmem.perBankWrBursts::2 8830 # Per bank write bursts +system.physmem.perBankWrBursts::3 8684 # Per bank write bursts +system.physmem.perBankWrBursts::4 8112 # Per bank write bursts +system.physmem.perBankWrBursts::5 8575 # Per bank write bursts +system.physmem.perBankWrBursts::6 8926 # Per bank write bursts +system.physmem.perBankWrBursts::7 8709 # Per bank write bursts +system.physmem.perBankWrBursts::8 8491 # Per bank write bursts +system.physmem.perBankWrBursts::9 8366 # Per bank write bursts +system.physmem.perBankWrBursts::10 8474 # Per bank write bursts +system.physmem.perBankWrBursts::11 8070 # Per bank write bursts +system.physmem.perBankWrBursts::12 8488 # Per bank write bursts +system.physmem.perBankWrBursts::13 8576 # Per bank write bursts +system.physmem.perBankWrBursts::14 8125 # Per bank write bursts +system.physmem.perBankWrBursts::15 7504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2627260507500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 2837503950500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3086 # Read request sizes (log2) +system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188059 # Read request sizes (log2) +system.physmem.readPktSize::6 188790 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 135856 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 73227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133887 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 73949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an 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an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.189431 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.582911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.571271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46399 53.55% 53.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16583 19.14% 72.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5986 6.91% 79.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3348 3.86% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2763 3.19% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1550 1.79% 88.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1005 1.16% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 914 1.05% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8101 9.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86649 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6686 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.651211 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 549.102387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6684 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6686 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6686 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.390667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.828394 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.276627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5432 81.24% 81.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 492 7.36% 88.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 97 1.45% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 153 2.29% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 34 0.51% 92.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 125 1.87% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.63% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.30% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.36% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 25 0.37% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 159 2.38% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.09% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.36% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.12% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6686 # Writes before turning the bus around for reads -system.physmem.totQLat 6416960776 # Total ticks spent queuing -system.physmem.totMemAccLat 10008842026 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 957835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33497.21 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52247.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.32 # Average system write bandwidth in MiByte/s +system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 86935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.482751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.610645 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.163398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46710 53.73% 53.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16982 19.53% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5795 6.67% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3191 3.67% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2666 3.07% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1598 1.84% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 941 1.08% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 911 1.05% 90.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8141 9.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86935 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.322812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 574.114177 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6556 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6558 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.488411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.922621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.969935 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5288 80.63% 80.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 495 7.55% 88.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 103 1.57% 89.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 154 2.35% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 30 0.46% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 130 1.98% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 43 0.66% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.29% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 29 0.44% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.30% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.15% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 145 2.21% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.11% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 33 0.50% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.15% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.15% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6558 # Writes before turning the bus around for reads +system.physmem.totQLat 6213827144 # Total ticks spent queuing +system.physmem.totMemAccLat 9819433394 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 961495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32313.19 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51063.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 159898 # Number of row buffer hits during reads -system.physmem.writeRowHits 81351 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.66 # Row buffer hit rate for writes -system.physmem.avgGap 7914126.56 # Average gap between requests -system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 337168440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 183970875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 767988000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 447599520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75926466675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509753884250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1759016918640 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.525234 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2511501025755 # Time in different power states -system.physmem_0.memoryStateTime::REF 87729980000 # Time in different power states +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing +system.physmem.readRowHits 160530 # Number of row buffer hits during reads +system.physmem.writeRowHits 79197 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.93 # Row buffer hit rate for writes +system.physmem.avgGap 8579414.12 # Average gap between requests +system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 765273600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 442383120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80482301685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1631904131250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1899441376155 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.405614 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2714718220190 # Time in different power states +system.physmem_0.memoryStateTime::REF 94750240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28029087995 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28035696060 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 317898000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 173456250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726226800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 435831840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171599840880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 75533290650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1510098775500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1758885319920 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.475144 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2512077352355 # Time in different power states -system.physmem_1.memoryStateTime::REF 87729980000 # Time in different power states +system.physmem_1.actEnergy 323832600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176694375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 734658600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 428289120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80147926575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1632197442750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1899340822020 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.370176 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2715209176165 # Time in different power states +system.physmem_1.memoryStateTime::REF 94750240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27453418145 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27544740085 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -352,30 +351,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 22632354 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14659623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 908184 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13749139 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10145845 # Number of BTB hits +system.cpu0.branchPred.lookups 53984881 # Number of BP lookups +system.cpu0.branchPred.condPredicted 25029279 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1031275 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32703051 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 24288553 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.792584 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3729563 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29268 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.269991 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15579180 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33867 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,78 +405,90 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 62082 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 62082 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23874 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18654 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19554 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 42528 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 489.830229 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2960.338749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 41379 97.30% 97.30% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 822 1.93% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.35% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 139 0.33% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 71885 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 71885 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26706 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21113 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24066 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 47819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 500.773751 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3132.734175 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 46517 97.28% 97.28% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 174 0.36% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.31% 99.91% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 42528 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9846.471248 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8208.075631 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8231.250252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 15054 99.39% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 70 0.46% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.14% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15147 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 97524095656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.460762 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.504971 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 97474132156 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 37222000 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 6333500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3452500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1280500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 673000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 722500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 263000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 97524095656 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5018 79.05% 79.05% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1330 20.95% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6348 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62082 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 47819 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 18759 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.566879 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7711.880133 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 18631 99.32% 99.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 106 0.57% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 16 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 18759 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 84429292764 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.657402 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.487897 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 29095217424 34.46% 34.46% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 55270258340 65.46% 99.92% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2 29607500 0.04% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::3 15656000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4 4826500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::5 2762000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6 4173000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::7 1494500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8 1031000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::9 697500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10 703000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::11 393500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12 1099500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::13 296000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14 143000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::15 934000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 84429292764 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5818 79.12% 79.12% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1535 20.88% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7353 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71885 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62082 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6348 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71885 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7353 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6348 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7353 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 79238 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16776749 # DTB read hits -system.cpu0.dtb.read_misses 53234 # DTB read misses -system.cpu0.dtb.write_hits 13912942 # DTB write hits -system.cpu0.dtb.write_misses 8848 # DTB write misses +system.cpu0.dtb.read_hits 24461690 # DTB read hits +system.cpu0.dtb.read_misses 61076 # DTB read misses +system.cpu0.dtb.write_hits 18142518 # DTB write hits +system.cpu0.dtb.write_misses 10809 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 80 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2058 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 171 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 829 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16829983 # DTB read accesses -system.cpu0.dtb.write_accesses 13921790 # DTB write accesses +system.cpu0.dtb.perms_faults 1016 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24522766 # DTB read accesses +system.cpu0.dtb.write_accesses 18153327 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30689691 # DTB hits -system.cpu0.dtb.misses 62082 # DTB misses -system.cpu0.dtb.accesses 30751773 # DTB accesses +system.cpu0.dtb.hits 42604208 # DTB hits +system.cpu0.dtb.misses 71885 # DTB misses +system.cpu0.dtb.accesses 42676093 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,53 +518,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10470 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10470 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4275 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6082 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 113 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10357 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 430.336970 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2100.288015 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9961 96.18% 96.18% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 126 1.22% 97.39% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 203 1.96% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 38 0.37% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 10 0.10% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10357 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11506.129272 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10069.776184 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6522.127356 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2498 92.79% 92.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 161 5.98% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 32 1.19% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20202424328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.966577 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.179934 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 675884500 3.35% 3.35% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 19525926328 96.65% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 564000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 49500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20202424328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2260 87.63% 87.63% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 12.37% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2579 # Table walker page sizes translated +system.cpu0.itb.walker.walks 10900 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10900 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4234 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6533 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 133 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10767 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 543.187517 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2520.119999 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 10263 95.32% 95.32% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.37% 96.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 248 2.30% 98.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 60 0.56% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.17% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 11 0.10% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10767 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3015 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6103.776811 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2740 90.88% 90.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 236 7.83% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 36 1.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 2 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 3015 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 20004739824 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.958205 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.200359 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 836985000 4.18% 4.18% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 19166939824 95.81% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 745000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 20004739824 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2539 88.10% 88.10% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 343 11.90% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2882 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10470 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10470 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10900 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10900 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2579 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13049 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 35710587 # ITB inst hits -system.cpu0.itb.inst_misses 10470 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2882 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2882 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13782 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74221386 # ITB inst hits +system.cpu0.itb.inst_misses 10900 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -562,1046 +576,1042 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2356 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1940 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35721057 # ITB inst accesses -system.cpu0.itb.hits 35710587 # DTB hits -system.cpu0.itb.misses 10470 # DTB misses -system.cpu0.itb.accesses 35721057 # DTB accesses -system.cpu0.numCycles 126659372 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74232286 # ITB inst accesses +system.cpu0.itb.hits 74221386 # DTB hits +system.cpu0.itb.misses 10900 # DTB misses +system.cpu0.itb.accesses 74232286 # DTB accesses +system.cpu0.numCycles 211089412 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17871987 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106431260 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 22632354 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 13875408 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 101673133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2651880 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 146874 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 68068 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 354842 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 428688 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 93530 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 35711195 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 256145 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4738 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 121963062 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.052824 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.258485 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21154368 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 200477778 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53984881 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39867733 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 180634648 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5887980 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 163875 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 73228 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 386540 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 467083 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 106682 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 74221667 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 284223 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5134 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 205930414 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.189818 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.306225 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62962688 51.62% 51.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 20162814 16.53% 68.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8269817 6.78% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 30567743 25.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98513446 47.84% 47.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 31147875 15.13% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14935472 7.25% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 61333621 29.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 121963062 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.178687 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.840295 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18684987 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58693341 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 38833256 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4747637 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1003841 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2912386 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 326313 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 104496141 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3704345 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1003841 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24126481 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12572099 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 34554184 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 38013567 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11692890 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 99684423 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 977099 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1404281 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 150386 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 54053 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7679999 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 103244507 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 455598825 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 114217475 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9462 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 92488092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10756412 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1189033 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1051673 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11830745 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 17693579 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15395073 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1633265 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2155883 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 96874005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1635627 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 95096979 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 454397 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8909178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20852751 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116081 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 121963062 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.779720 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.027198 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 205930414 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.255744 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.949729 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26441792 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 111116512 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 60639193 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 5147176 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2585741 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3185045 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 362773 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 158832709 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4189276 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2585741 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 35360438 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13326930 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 85149071 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 56726750 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 12781484 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 141877128 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1133387 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1508513 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 170712 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 63171 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8443572 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 146064106 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 654194105 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157626069 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 133804111 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12259992 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2731692 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2584898 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22953113 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 25474104 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19753680 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1758400 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2611655 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 138738893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1764680 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 136614694 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 514032 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11572613 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23827744 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 127449 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205930414 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.663402 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.962674 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 68765776 56.38% 56.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22213388 18.21% 74.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 21122370 17.32% 91.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 8807290 7.22% 99.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1054209 0.86% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 127115623 61.73% 61.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 34474239 16.74% 78.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 32051807 15.56% 94.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 11118185 5.40% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1170514 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 121963062 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205930414 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 8813581 40.35% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 132 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5351630 24.50% 64.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7678552 35.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 11113465 43.69% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 76 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5930869 23.32% 67.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8390890 32.99% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 62602265 65.83% 65.83% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 87841 0.09% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7143 0.01% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.93% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 17444547 18.34% 84.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 14952910 15.72% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 92049537 67.38% 67.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8149 0.01% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 25196866 18.44% 85.91% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 19245098 14.09% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 95096979 # Type of FU issued -system.cpu0.iq.rate 0.750809 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 21843895 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229701 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 334422549 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 107425966 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 93117016 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32763 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11378 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9790 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 116917216 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 346137 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 136614694 # Type of FU issued +system.cpu0.iq.rate 0.647189 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 25435300 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 505071342 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 152083684 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 132900099 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 37792 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 11443 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 162023237 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 24442 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 380983 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1858057 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2517 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18608 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 952368 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2125903 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2726 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20804 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1085884 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 100941 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 343903 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121982 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 393712 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1003841 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1765434 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 210085 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 98680740 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2585741 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1952892 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 140712950 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 17693579 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15395073 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 848677 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 265563 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 639510 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 25474104 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19753680 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 902814 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28763 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 175994 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20804 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 314280 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 420638 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 734918 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 135458636 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 24717807 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1084310 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171108 # number of nop insts executed -system.cpu0.iew.exec_refs 31795600 # number of memory reference insts executed -system.cpu0.iew.exec_branches 15818182 # Number of branches executed -system.cpu0.iew.exec_stores 14774938 # Number of stores executed -system.cpu0.iew.exec_rate 0.742778 # Inst execution rate -system.cpu0.iew.wb_sent 93557624 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 93126806 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 48392376 # num instructions producing a value -system.cpu0.iew.wb_consumers 80015738 # num instructions consuming a value +system.cpu0.iew.exec_nop 209377 # number of nop insts executed +system.cpu0.iew.exec_refs 43763584 # number of memory reference insts executed +system.cpu0.iew.exec_branches 26159060 # Number of branches executed +system.cpu0.iew.exec_stores 19045777 # Number of stores executed +system.cpu0.iew.exec_rate 0.641712 # Inst execution rate +system.cpu0.iew.wb_sent 134853240 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 132911542 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 67798610 # num instructions producing a value +system.cpu0.iew.wb_consumers 109653581 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.735254 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.604786 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.629646 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618298 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7942186 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1519546 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 586085 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 120319586 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.745699 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.465434 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10465758 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1637231 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 673026 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202620964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.637065 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.337510 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78400270 65.16% 65.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 23370127 19.42% 84.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 7855137 6.53% 91.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3041175 2.53% 93.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3186617 2.65% 96.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1413825 1.18% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1097896 0.91% 98.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 521063 0.43% 98.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1433476 1.19% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 140811364 69.49% 69.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 34122035 16.84% 86.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12973971 6.40% 92.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3422170 1.69% 94.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4965504 2.45% 96.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2761485 1.36% 98.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1431161 0.71% 98.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 576287 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1556987 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 120319586 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 74552173 # Number of instructions committed -system.cpu0.commit.committedOps 89722144 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202620964 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 106609467 # Number of instructions committed +system.cpu0.commit.committedOps 129082799 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 30278227 # Number of memory references committed -system.cpu0.commit.loads 15835522 # Number of loads committed -system.cpu0.commit.membars 627502 # Number of memory barriers committed -system.cpu0.commit.branches 15222627 # Number of branches committed -system.cpu0.commit.fp_insts 9772 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 77510355 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1849810 # Number of function calls committed. +system.cpu0.commit.refs 42015997 # Number of memory references committed +system.cpu0.commit.loads 23348201 # Number of loads committed +system.cpu0.commit.membars 664671 # Number of memory barriers committed +system.cpu0.commit.branches 25482813 # Number of branches committed +system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 112616062 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4882659 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 59351234 66.15% 66.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 85540 0.10% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7143 0.01% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 15835522 17.65% 83.90% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14442705 16.10% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 86948458 67.36% 67.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 110195 0.09% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8149 0.01% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 23348201 18.09% 85.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18667796 14.46% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 89722144 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1433476 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 212523033 # The number of ROB reads -system.cpu0.rob.rob_writes 196970686 # The number of ROB writes -system.cpu0.timesIdled 126988 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4696310 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5127862528 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 74430479 # Number of Instructions Simulated -system.cpu0.committedOps 89600450 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.701714 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.701714 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.587643 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.587643 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 104622739 # number of integer regfile reads -system.cpu0.int_regfile_writes 56501496 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8247 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 331476991 # number of cc regfile reads -system.cpu0.cc_regfile_writes 38443016 # number of cc regfile writes -system.cpu0.misc_regfile_reads 169856708 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1190913 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 672498 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.161129 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 27296512 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 673010 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.558851 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 129082799 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1556987 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 317266716 # The number of ROB reads +system.cpu0.rob.rob_writes 282405799 # The number of ROB writes +system.cpu0.timesIdled 139400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5158998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5463919353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 106457624 # Number of Instructions Simulated +system.cpu0.committedOps 128930956 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.982849 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.982849 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.504325 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.504325 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 146869793 # number of integer regfile reads +system.cpu0.int_regfile_writes 83863812 # number of integer regfile writes +system.cpu0.fp_regfile_reads 9544 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes +system.cpu0.cc_regfile_reads 478325864 # number of cc regfile reads +system.cpu0.cc_regfile_writes 51342401 # number of cc regfile writes +system.cpu0.misc_regfile_reads 283146795 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1260752 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 750420 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.151485 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38802198 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 750932 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.672053 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.161129 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947580 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947580 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.151485 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969046 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.969046 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60152551 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60152551 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14711290 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14711290 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11396766 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11396766 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295733 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 295733 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354236 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354236 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350938 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 350938 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26108056 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 26108056 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26403789 # number of overall hits -system.cpu0.dcache.overall_hits::total 26403789 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 611234 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 611234 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1805910 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1805910 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141308 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141308 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24174 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24174 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21176 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21176 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2417144 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2417144 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2558452 # number of overall misses -system.cpu0.dcache.overall_misses::total 2558452 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9073163500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9073163500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32396978375 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32396978375 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 391326000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 391326000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 534289500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 534289500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 728500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 728500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 41470141875 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 41470141875 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 41470141875 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 41470141875 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15322524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15322524 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13202676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13202676 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437041 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437041 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378410 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372114 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28525200 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28525200 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 28962241 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 28962241 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039891 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039891 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136784 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136784 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323329 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323329 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063883 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063883 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056907 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056907 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084737 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084737 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088338 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088338 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14844.009823 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14844.009823 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17939.420223 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17939.420223 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16187.887813 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16187.887813 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25230.898187 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25230.898187 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83743288 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83743288 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22166108 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22166108 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15386838 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15386838 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316240 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 316240 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371193 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 371193 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369806 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 369806 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37552946 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37552946 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 37869186 # number of overall hits +system.cpu0.dcache.overall_hits::total 37869186 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 688329 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 688329 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1970797 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1970797 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153398 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 153398 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26102 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 26102 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2659126 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2659126 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2812524 # number of overall misses +system.cpu0.dcache.overall_misses::total 2812524 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9979901000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 9979901000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36499508368 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36499508368 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 419269000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 419269000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 539016500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 539016500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 316500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 316500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 46479409368 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46479409368 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46479409368 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46479409368 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22854437 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22854437 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17357635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17357635 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469638 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 469638 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397295 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 397295 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390053 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390053 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 40212072 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40212072 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40681710 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40681710 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030118 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030118 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113541 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.113541 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326630 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326630 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065699 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065699 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051908 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051908 # miss rate for StoreCondReq accesses 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-system.cpu0.dcache.blocked::no_mshrs 49 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 192315 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.775510 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 27.169176 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1220 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5610117 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 211671 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.018868 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.503947 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 490431 # number of writebacks -system.cpu0.dcache.writebacks::total 490431 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 244715 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 244715 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493725 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1493725 # number of WriteReq MSHR hits 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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 97992 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6126 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6126 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21176 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21176 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 678704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 678704 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 776696 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 776696 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17958 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17958 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16709 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16709 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34667 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34667 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4650113000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4650113000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6789940400 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6789940400 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1696741500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1696741500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97425500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97425500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513125500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513125500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 716500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 716500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11440053400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11440053400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13136794900 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13136794900 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3760775500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3760775500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2938081500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2938081500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6698857000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6698857000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023920 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023920 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023646 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023646 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224217 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224217 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016189 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056907 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056907 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023793 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023793 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026818 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026818 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12687.235860 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12687.235860 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21749.733011 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21749.733011 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17315.102253 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17315.102253 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15903.607574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15903.607574 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24231.464866 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24231.464866 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 750420 # number of writebacks +system.cpu0.dcache.writebacks::total 750420 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277928 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 277928 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634691 # number of WriteReq MSHR hits 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of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1795459000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1795459000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 518776500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 518776500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 309500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 309500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12810598902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12810598902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14606057902 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14606057902 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629004500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629004500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396257500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396257500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12025262000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12025262000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016990 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016990 # mshr miss rate for LoadLockedReq accesses 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22864.475499 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25622.388502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25622.388502 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 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193234.401592 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193234.401592 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537 # average WriteReq mshr uncacheable latency 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ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34456109 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34456109 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34456109 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34456109 # number of overall hits -system.cpu0.icache.overall_hits::total 34456109 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1251492 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1251492 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1251492 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1251492 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1251492 # number of overall misses -system.cpu0.icache.overall_misses::total 1251492 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13477536890 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13477536890 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13477536890 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13477536890 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13477536890 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13477536890 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35707601 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35707601 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35707601 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35707601 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35707601 # number of overall (read+write) accesses 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overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10769.175424 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10769.175424 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1798735 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 149746644 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 149746644 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 72850689 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 72850689 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 72850689 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 72850689 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 72850689 # number of overall hits +system.cpu0.icache.overall_hits::total 72850689 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1367277 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1367277 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1367277 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1367277 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1367277 # number of overall misses +system.cpu0.icache.overall_misses::total 1367277 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942894261 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14942894261 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14942894261 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14942894261 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14942894261 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14942894261 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74217966 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 74217966 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74217966 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 74217966 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74217966 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 74217966 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018422 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018422 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018422 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018422 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018422 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018422 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10928.944362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10928.944362 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2021185 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 112593 # number of cycles access was blocked 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# number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 56563 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 56563 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 56563 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 56563 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310714 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1310714 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1310714 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1310714 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1310714 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1310714 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12113813705 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12113813705 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12113813705 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12113813705 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12113813705 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12113813705 # number of overall MSHR miss cycles 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-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140025.964714 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140025.964714 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13414113616 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13414113616 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13414113616 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13414113616 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13414113616 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13414113616 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017660 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses 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-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32682.978879 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32682.978879 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18064.019037 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18064.019037 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 625999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 625999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57218.002951 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57218.002951 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60574.842304 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26869.500117 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26869.500117 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 42370.378910 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24360.837438 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20305.031447 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 60574.842304 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35755.485450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89557.677124 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 68405.133252 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201415.469429 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 191543.054098 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168173.586810 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168173.586810 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132525.466045 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185393.355699 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 181177.509543 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207675 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 254999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 254999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3900428 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1972103 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 30395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 166078 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 150 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 98608 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1819240 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 685334 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1450937 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 287419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 90627 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114961 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 22 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 273601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1201355 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 557036 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3216 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3585963 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2443651 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28820 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 110863 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6169297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76933952 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82016191 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 198724 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159198391 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 860528 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4738789 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.052471 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.223116 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 4274202 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 328935 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4545 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 121088 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2005227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 739211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1521984 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 210746 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 317495 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85916 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42642 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113550 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299038 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 295760 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595848 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3361 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3912120 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727113 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130288 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6801615 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166153536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103357964 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245424 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 269816100 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1019832 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3249125 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.119614 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.328792 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4490292 94.76% 94.76% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 248347 5.24% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 150 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2865028 88.18% 88.18% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 379552 11.68% 99.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4545 0.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4738789 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2495889948 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112738429 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3249125 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4275785445 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115025120 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1805438687 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1969663813 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1156413493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1293120190 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16448481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17309980 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 61214934 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 68982399 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 35362528 # Number of BP lookups -system.cpu1.branchPred.condPredicted 12650645 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 376011 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 19640345 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15643376 # Number of BTB hits +system.cpu1.branchPred.lookups 4001540 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2313487 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 245860 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2018567 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1484210 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.649191 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12652559 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10779 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.527904 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 788035 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5731 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1631,90 +1641,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24283 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24283 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11247 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5966 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7070 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17213 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 473.798873 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2831.806000 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16574 96.29% 96.29% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 219 1.27% 97.56% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 229 1.33% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 75 0.44% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 24 0.14% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 7 0.04% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 43 0.25% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 17 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 3 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 15963 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 15963 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8440 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3082 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4441 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 11522 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 609.182434 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3297.605064 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 10996 95.43% 95.43% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 184 1.60% 98.54% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 58 0.50% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 21 0.18% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 47 0.41% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 21 0.18% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17213 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5394 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10976.177234 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9365.976538 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8403.035892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4813 89.23% 89.23% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 520 9.64% 98.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 49 0.91% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 4 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 4 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5394 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 75766592176 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.320474 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.469554 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 51526613188 68.01% 68.01% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 24219637488 31.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 12480500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3766000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1197500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 815500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 985500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 293500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 146000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 224500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 83500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 76500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 137000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 22000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 95500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 75766592176 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 75.85% 75.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 615 24.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2547 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 11522 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 3235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6677.373091 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2744 84.82% 84.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 453 14.00% 98.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 32 0.99% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.15% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 3235 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 75555560672 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.169680 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.377976 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 62765308336 83.07% 83.07% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 12774698836 16.91% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 10450000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 2017500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1080000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 463500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 984500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 133500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 33500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 93000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 88500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 24500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 138000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 75555560672 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1230 72.78% 72.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 460 27.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1690 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15963 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24283 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2547 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15963 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1690 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2547 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1690 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 17653 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11209013 # DTB read hits -system.cpu1.dtb.read_misses 21079 # DTB read misses -system.cpu1.dtb.write_hits 7325054 # DTB write hits -system.cpu1.dtb.write_misses 3204 # DTB write misses +system.cpu1.dtb.read_hits 3544820 # DTB read hits +system.cpu1.dtb.read_misses 14056 # DTB read misses +system.cpu1.dtb.write_hits 3033862 # DTB write hits +system.cpu1.dtb.write_misses 1907 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2001 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 612 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1651 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 51 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 367 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11230092 # DTB read accesses -system.cpu1.dtb.write_accesses 7328258 # DTB write accesses +system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3558876 # DTB read accesses +system.cpu1.dtb.write_accesses 3035769 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18534067 # DTB hits -system.cpu1.dtb.misses 24283 # DTB misses -system.cpu1.dtb.accesses 18558350 # DTB accesses +system.cpu1.dtb.hits 6578682 # DTB hits +system.cpu1.dtb.misses 15963 # DTB misses +system.cpu1.dtb.accesses 6594645 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1744,57 +1751,60 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6861 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6861 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4105 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2676 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 80 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6781 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 216.855921 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1684.274104 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6669 98.35% 98.35% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 39 0.58% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 44 0.65% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 12 0.18% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6781 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1249 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11729.383507 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10507.790303 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6381.189280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 353 28.26% 28.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 814 65.17% 93.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 24 1.92% 95.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 32 2.56% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 17 1.36% 99.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.56% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1249 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 15604919032 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.958751 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.198933 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 643875264 4.13% 4.13% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14960875268 95.87% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 148500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 20000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 15604919032 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 997 85.29% 85.29% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 172 14.71% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1169 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6382 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6382 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2250 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 56 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 181.394246 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1406.259305 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6214 98.23% 98.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.93% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 37 0.58% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 6 0.09% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 4 0.06% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 3 0.05% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5550.111041 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 41 4.59% 4.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 147 16.46% 21.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 548 61.37% 82.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 11.98% 94.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 11 1.23% 95.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 5 0.56% 96.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 19 2.13% 98.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.34% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.11% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.56% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.34% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.22% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 893 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 11098487732 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.931053 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.253398 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 765303264 6.90% 6.90% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 10333090968 93.10% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 93500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 11098487732 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 693 82.80% 82.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 144 17.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6861 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6861 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6382 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6382 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8030 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 45813094 # ITB inst hits -system.cpu1.itb.inst_misses 6861 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7219 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7191521 # ITB inst hits +system.cpu1.itb.inst_misses 6382 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1803,1043 +1813,1040 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 526 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 347 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 45819955 # ITB inst accesses -system.cpu1.itb.hits 45813094 # DTB hits -system.cpu1.itb.misses 6861 # DTB misses -system.cpu1.itb.accesses 45819955 # DTB accesses -system.cpu1.numCycles 115872528 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7197903 # ITB inst accesses +system.cpu1.itb.hits 7191521 # DTB hits +system.cpu1.itb.misses 6382 # DTB misses +system.cpu1.itb.accesses 7197903 # DTB accesses +system.cpu1.numCycles 32425900 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 11244647 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 115696053 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 35362528 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 28295935 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 100513645 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3955668 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 92958 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 43827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 218813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 324785 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 35760 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 45812479 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 133633 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2410 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114452269 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.250587 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.333322 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8095443 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 21322301 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4001540 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2272245 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 22576717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 701366 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 87665 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 29928 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 190452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 273109 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 16492 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7191191 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 105174 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2314 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 31620489 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.824543 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.195918 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 53787165 47.00% 47.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 15397458 13.45% 60.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8067873 7.05% 67.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 37199773 32.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19556210 61.85% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4372737 13.83% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1374906 4.35% 80.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 6316636 19.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114452269 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.305185 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.998477 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 14331089 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 67536075 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 29425449 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1338809 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1820847 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 912295 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 160061 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74627346 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1451044 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1820847 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19084331 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2925531 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 61205079 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 25977648 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3438833 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 61437487 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 313811 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 329328 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 50880 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 21104 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2227690 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 61781071 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 288761968 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 65715217 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 58198437 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3582634 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1923301 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1845273 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13635165 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11552975 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7780383 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 701343 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 925146 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60392573 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 653667 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 59853310 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 146761 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4556505 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7374621 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 54925 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114452269 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.522954 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.862457 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 31620489 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.123406 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.657570 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6635373 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16232056 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 7605382 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 916534 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 231144 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 619166 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 122135 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20047523 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 930312 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 231144 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7872130 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2262020 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11428772 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7266376 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2560047 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19035604 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 152359 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 204838 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 28045 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12601 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1704098 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 18785965 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 89036414 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21967957 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 16823959 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1962006 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 364639 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 299553 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2452699 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3781052 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3343720 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 554765 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 448879 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 18340674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 508914 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 18185979 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 84059 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1788804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4127246 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 41236 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 31620489 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.575133 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.924807 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 77949624 68.11% 68.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 17744881 15.50% 83.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 14511556 12.68% 96.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3899540 3.41% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 346643 0.30% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 25 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 20837444 65.90% 65.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5408008 17.10% 83.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3574976 11.31% 94.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1572233 4.97% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 227820 0.72% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114452269 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 31620489 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3494882 44.84% 44.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 604 0.01% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1953801 25.07% 69.91% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2345303 30.09% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1135208 27.60% 27.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 664 0.02% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1335102 32.46% 60.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1642689 39.93% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 40748712 68.08% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 52853 0.09% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4129 0.01% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11462159 19.15% 87.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7585390 12.67% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 11205359 61.62% 61.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 26215 0.14% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3128 0.02% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3726030 20.49% 82.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3225223 17.73% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 59853310 # Type of FU issued -system.cpu1.iq.rate 0.516544 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7794590 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.130228 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 242094525 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 65611557 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 57714006 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5715 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67644200 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3633 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 110002 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 18185979 # Type of FU issued +system.cpu1.iq.rate 0.560847 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4113663 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226200 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 72190169 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 20646412 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 17793804 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 22299618 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 72560 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 628284 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 842 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10885 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 426405 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 346468 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 605 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8056 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 274891 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 57089 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 100676 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 35566 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 53462 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1820847 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 727831 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 179449 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61101449 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 231144 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 519259 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 154115 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18866238 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11552975 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7780383 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 331927 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 11154 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 159363 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10885 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 82141 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 153260 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 235401 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59500982 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 11329735 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 328066 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 3781052 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3343720 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 266301 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6646 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 141712 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8056 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 30125 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 104168 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 134293 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 17982694 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3650056 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 187326 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55209 # number of nop insts executed -system.cpu1.iew.exec_refs 18836194 # number of memory reference insts executed -system.cpu1.iew.exec_branches 12894851 # Number of branches executed -system.cpu1.iew.exec_stores 7506459 # Number of stores executed -system.cpu1.iew.exec_rate 0.513504 # Inst execution rate -system.cpu1.iew.wb_sent 59314333 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 57715790 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28288530 # num instructions producing a value -system.cpu1.iew.wb_consumers 43462608 # num instructions consuming a value +system.cpu1.iew.exec_nop 16650 # number of nop insts executed +system.cpu1.iew.exec_refs 6820794 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2588349 # Number of branches executed +system.cpu1.iew.exec_stores 3170738 # Number of stores executed +system.cpu1.iew.exec_rate 0.554578 # Inst execution rate +system.cpu1.iew.wb_sent 17880625 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 17793804 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 8844802 # num instructions producing a value +system.cpu1.iew.wb_consumers 13735859 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.498097 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.650871 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.548753 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.643921 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 4228906 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 598742 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 219024 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112407306 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.502841 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.169324 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1618894 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 467678 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 126321 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31256140 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.545936 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.299262 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 84196637 74.90% 74.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 15782926 14.04% 88.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6506905 5.79% 94.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 899885 0.80% 95.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2238894 1.99% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1696394 1.51% 99.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 469505 0.42% 99.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 157300 0.14% 99.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 458860 0.41% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23000082 73.59% 73.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 4925249 15.76% 89.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1442060 4.61% 93.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 538119 1.72% 95.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 452265 1.45% 97.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 297433 0.95% 98.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 181915 0.58% 98.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 99730 0.32% 98.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 319287 1.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112407306 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 46016034 # Number of instructions committed -system.cpu1.commit.committedOps 56522947 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31256140 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13926644 # Number of instructions committed +system.cpu1.commit.committedOps 17063847 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18278669 # Number of memory references committed -system.cpu1.commit.loads 10924691 # Number of loads committed -system.cpu1.commit.membars 232005 # Number of memory barriers committed -system.cpu1.commit.branches 12685356 # Number of branches committed -system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 50487985 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3456157 # Number of function calls committed. +system.cpu1.commit.refs 6503413 # Number of memory references committed +system.cpu1.commit.loads 3434584 # Number of loads committed +system.cpu1.commit.membars 191656 # Number of memory barriers committed +system.cpu1.commit.branches 2466066 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 15229015 # Number of committed integer instructions. +system.cpu1.commit.function_calls 413334 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 38188356 67.56% 67.56% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 51793 0.09% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.65% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4129 0.01% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10924691 19.33% 86.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7353978 13.01% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 10531890 61.72% 61.72% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 25416 0.15% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3128 0.02% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3434584 20.13% 82.02% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3068829 17.98% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 56522947 # Class of committed instruction -system.cpu1.commit.bw_lim_events 458860 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 152481338 # The number of ROB reads -system.cpu1.rob.rob_writes 123545319 # The number of ROB writes -system.cpu1.timesIdled 68699 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1420259 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5138082707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 45982821 # Number of Instructions Simulated -system.cpu1.committedOps 56489734 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.519909 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.519909 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.396840 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.396840 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 62666330 # number of integer regfile reads -system.cpu1.int_regfile_writes 39173045 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads -system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 211754483 # number of cc regfile reads -system.cpu1.cc_regfile_writes 18307351 # number of cc regfile writes -system.cpu1.misc_regfile_reads 158297998 # number of misc regfile reads -system.cpu1.misc_regfile_writes 426234 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 227119 # number of replacements -system.cpu1.dcache.tags.tagsinuse 480.780000 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17377933 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227440 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 76.406670 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89481619000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 480.780000 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.939023 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.939023 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 24 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36531516 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36531516 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10502192 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10502192 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6578620 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6578620 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65191 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65191 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88541 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88541 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80577 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80577 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17080812 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17080812 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17146003 # number of overall hits -system.cpu1.dcache.overall_hits::total 17146003 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 257246 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 257246 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 477990 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 477990 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35676 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35676 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19120 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19120 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23513 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23513 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 735236 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 735236 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 770912 # number of overall misses -system.cpu1.dcache.overall_misses::total 770912 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4397234500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4397234500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13204055417 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 13204055417 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 384125500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 384125500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 615714500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 615714500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2019500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 17601289917 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 17601289917 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 17601289917 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 17601289917 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10759438 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10759438 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7056610 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7056610 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100867 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100867 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107661 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 107661 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104090 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104090 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17816048 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17816048 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17916915 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17916915 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023909 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023909 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067736 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.067736 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.353693 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.353693 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177594 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225891 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225891 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041268 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041268 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043027 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043027 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17093.499996 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17093.499996 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27624.124808 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27624.124808 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20090.245816 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20090.245816 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26186.131076 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26186.131076 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 17063847 # Class of committed instruction +system.cpu1.commit.bw_lim_events 319287 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 48731479 # The number of ROB reads +system.cpu1.rob.rob_writes 37726129 # The number of ROB writes +system.cpu1.timesIdled 54512 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 805411 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5642014046 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13923580 # Number of Instructions Simulated +system.cpu1.committedOps 17060783 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.328848 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.328848 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.429397 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.429397 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20183446 # number of integer regfile reads +system.cpu1.int_regfile_writes 11616875 # number of integer regfile writes +system.cpu1.cc_regfile_reads 64541382 # number of cc regfile reads +system.cpu1.cc_regfile_writes 5516447 # number of cc regfile writes +system.cpu1.misc_regfile_reads 46291245 # number of misc regfile reads +system.cpu1.misc_regfile_writes 345789 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 150536 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.106753 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5837857 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 150895 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.688207 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89621465500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.106753 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933802 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.933802 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12869097 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12869097 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3072993 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3072993 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2528751 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2528751 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42878 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42878 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70516 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70516 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61926 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61926 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5601744 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5601744 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5644622 # number of overall hits +system.cpu1.dcache.overall_hits::total 5644622 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178967 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178967 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 316584 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 316584 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23990 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 23990 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17392 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17392 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23411 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23411 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 495551 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 495551 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 519541 # number of overall misses +system.cpu1.dcache.overall_misses::total 519541 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3311567500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3311567500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11108580447 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11108580447 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357363500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 357363500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 641574000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 641574000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 819500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 819500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 14420147947 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 14420147947 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 14420147947 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 14420147947 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3251960 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3251960 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2845335 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2845335 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66868 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66868 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87908 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87908 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85337 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85337 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6097295 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6097295 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6164163 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6164163 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055034 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.055034 # miss rate for ReadReq accesses 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# miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.084284 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23939.646477 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23939.646477 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22831.775763 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 22831.775763 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1982545 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 49131 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.243243 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 40.352222 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1652938 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 30246 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.625000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 54.649805 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 137800 # number of writebacks -system.cpu1.dcache.writebacks::total 137800 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 93990 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 93990 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 374320 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 374320 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13607 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13607 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 468310 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 468310 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 468310 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 468310 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163256 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163256 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103670 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103670 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32269 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32269 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5513 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23513 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23513 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 266926 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 266926 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 299195 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 299195 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17062 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17062 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31403 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31403 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2326061500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2326061500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3203086933 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3203086933 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 553503000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 553503000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 109001000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 109001000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 592222500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 592222500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1998500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5529148433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5529148433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6082651433 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6082651433 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2940631000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2940631000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2452626000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2452626000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5393257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5393257000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015173 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015173 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014691 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014691 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319916 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319916 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051207 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051207 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225891 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225891 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014982 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014982 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016699 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016699 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14247.938820 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14247.938820 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30896.951220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30896.951220 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17152.778208 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17152.778208 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19771.630691 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19771.630691 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25187.024199 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25187.024199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 150537 # number of writebacks +system.cpu1.dcache.writebacks::total 150537 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62639 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 62639 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238187 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 238187 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12480 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12480 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 300826 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 300826 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 300826 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 300826 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116328 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116328 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78397 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 78397 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23066 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23066 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4912 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4912 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23411 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23411 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 194725 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 194725 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 217791 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 217791 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2412 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5465 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1734233000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1734233000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2786620456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2786620456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 403892500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 403892500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94891500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94891500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 618171000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 618171000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 811500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 811500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4520853456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4520853456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4924745956 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4924745956 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433886500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433886500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300722000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300722000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734608500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035772 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035772 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027553 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.344948 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.344948 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055877 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055877 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274336 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274336 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035332 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035332 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540 # average SoftPFReq mshr miss latency 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average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20330.057097 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172349.724534 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172349.724534 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171021.964995 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171021.964995 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171743.368468 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171743.368468 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23216.605243 # average overall mshr miss latency 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occupancy +system.cpu1.icache.tags.replacements 559207 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.428858 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6611589 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 559719 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.812336 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79408312500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.428858 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975447 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975447 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id 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-system.cpu1.icache.overall_miss_latency::cpu1.inst 6808598319 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6808598319 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 45812155 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 45812155 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 45812155 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 45812155 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 45812155 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 45812155 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015260 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.015260 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015260 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.015260 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015260 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.015260 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9739.021061 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9739.021061 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9739.021061 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9739.021061 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9739.021061 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 778427 # number of cycles access was blocked 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number of overall hits +system.cpu1.icache.overall_hits::total 6611589 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 579409 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 579409 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 579409 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 579409 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 579409 # number of overall misses +system.cpu1.icache.overall_misses::total 579409 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5260271690 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5260271690 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5260271690 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5260271690 # number of demand (read+write) miss cycles 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rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.080574 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080574 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.080574 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9078.684815 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9078.684815 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9078.684815 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9078.684815 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 508858 # number of cycles access was blocked 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-system.cpu1.icache.overall_mshr_hits::cpu1.inst 26283 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 26283 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672822 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 672822 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 672822 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 672822 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 672822 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 672822 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6167077156 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6167077156 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6167077156 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6167077156 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6167077156 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6167077156 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13506000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13506000 # number of ReadReq MSHR uncacheable cycles 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9165.986184 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9165.986184 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132411.764706 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132411.764706 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132411.764706 # average overall mshr uncacheable latency +system.cpu1.icache.writebacks::writebacks 559207 # number of writebacks +system.cpu1.icache.writebacks::total 559207 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19686 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 19686 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 19686 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 19686 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 19686 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 19686 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559723 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 559723 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 559723 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 559723 # number of demand (read+write) MSHR misses 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MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4814325924 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4814325924 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077837 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for demand accesses 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137067.951456 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 262736 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 263407 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 604 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 109440 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 110020 # number of prefetch candidates identified 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32853 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15122.347980 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1241496 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 48030 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 25.848345 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6569.267487 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 14.374590 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.390464 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4943.655897 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2538.739672 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1470.219959 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.400956 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000877 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000024 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301737 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.154952 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.089735 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.948282 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1250 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 33 # Occupied blocks per task id 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-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8543 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4263 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076294 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002014 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.809814 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 30842090 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 30842090 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19102 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7340 # number of ReadReq hits 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-system.cpu1.l2cache.ReadSharedReq_hits::total 128580 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19102 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7340 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 650319 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 165660 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 842421 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19102 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7340 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 650319 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 165660 # number of overall hits -system.cpu1.l2cache.overall_hits::total 842421 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 434 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 283 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29244 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29244 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22424 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22424 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36071 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36071 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22492 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 22492 # number of ReadCleanReq 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3745713491 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 5010755991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10853500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5913500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1248275500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3745713491 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 5010755991 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19536 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7623 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 27159 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 137799 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 137799 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31159 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31159 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23513 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23513 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73151 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 73151 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 672811 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 672811 # number of ReadCleanReq accesses(hits+misses) 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accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 274161 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 974131 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022215 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037124 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.026400 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938541 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938541 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.953685 # miss rate for SCUpgradeReq accesses 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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170100 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17588.904694 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50628.280594 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23586.650185 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23586.650185 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18516.656261 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18516.656261 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46182.211259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46182.211259 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49490.633204 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19284.639756 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19284.639756 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31636.488495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19019.630485 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15294.444444 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 49490.633204 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27969.486924 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50628.280594 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35739.609590 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164333.255187 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164098.986250 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 163506.624224 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163506.624224 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124911.764706 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 163955.752571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163829.344485 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.164464 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15450.140449 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57294.005503 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20607.194467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20607.194467 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18882.401948 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18882.401948 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 187625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 187625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47100.974776 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47100.974776 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53199.903981 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16826.176342 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16826.176342 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29224.667682 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16127.586207 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14386.281588 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53199.903981 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26736.795746 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57294.005503 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33552.662529 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1911239 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 964293 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 15206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 115900 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 115705 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 195 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 49800 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 965132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 177279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 810351 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 43777 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73201 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89676 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 81502 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 78977 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 672822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 286780 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 213 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2005740 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1027154 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42715 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3092689 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43061536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29508655 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30492 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 72678827 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 390895 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2268265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.069071 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.253913 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1523677 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769701 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 171538 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1680 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 26336 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 768409 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 120538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 604293 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 90253 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 23776 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71073 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57287 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 54410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559723 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 223005 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1668415 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 728070 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27246 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2439609 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70944752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24680600 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29208 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 95705128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 366083 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1123000 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.171945 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.381277 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2111789 93.10% 93.10% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 156281 6.89% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 195 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 931586 82.96% 82.96% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 189734 16.90% 99.85% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1680 0.15% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2268265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1127589981 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 88549490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1123000 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1483438992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80062850 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1009459749 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 839820234 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 464204253 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 323064197 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9470972 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8585980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23200956 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 14617972 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31010 # Transaction distribution -system.iobus.trans_dist::ReadResp 31010 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31018 # Transaction distribution +system.iobus.trans_dist::ReadResp 31018 # Transaction distribution +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2855,16 +2862,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2880,67 +2887,67 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40405000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 581000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6141000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 169500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 34081000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186507978 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186321543 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.440882 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.554671 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256003407000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.440882 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902555 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902555 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256310853000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.554671 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909667 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909667 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2954,14 +2961,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32773877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32773877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715888101 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715888101 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32773877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32773877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32773877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32773877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32664376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32664376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4736716167 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4736716167 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32664376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32664376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32664376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32664376 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2978,19 +2985,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130055.067460 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130055.067460 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130186.840244 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130186.840244 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130055.067460 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130055.067460 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130055.067460 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129620.539683 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129620.539683 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129620.539683 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 734 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.200000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.065934 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -3004,14 +3011,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20173877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20173877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904688101 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2904688101 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20173877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20173877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20173877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20173877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20064376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20064376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2925516167 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2925516167 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20064376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20064376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20064376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20064376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3020,603 +3027,602 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80055.067460 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80055.067460 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80186.840244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80186.840244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80055.067460 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80055.067460 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 129384 # number of replacements -system.l2c.tags.tagsinuse 63948.068698 # Cycle average of tags in use -system.l2c.tags.total_refs 411864 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 193785 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.125366 # Average number of references to valid blocks. +system.l2c.tags.replacements 124125 # number of replacements +system.l2c.tags.tagsinuse 63228.123175 # Cycle average of tags in use +system.l2c.tags.total_refs 440353 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 188206 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.339739 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12531.983329 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.494639 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6442.782513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2029.980541 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34279.633489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.674973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.902888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3492.124605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1459.870620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3683.572737 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.191223 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.098309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.030975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.523066 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13402.508661 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.314049 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063314 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8220.125540 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2863.958869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.597372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1640.209162 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 501.782314 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1607.058034 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.204506 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.125429 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043701 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533548 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.053286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.056207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975770 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30986 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24764 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.472809 # 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+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.549735 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.549735 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128226.416128 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129307.957682 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144712.780285 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130717.030114 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143383.206188 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122503.372493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136456.122612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 148098.213322 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126892.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 137428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 119333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122524.560018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135629.795112 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 146825.506022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125166.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125223.852669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124880.767758 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166785.010005 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 143636.137449 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183415.330215 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146359.370420 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161200.679380 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151171.017895 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146506.380448 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149016.571337 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114525.299601 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167874.031154 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106887.254902 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 146426.512803 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 155731.543232 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 38123 # Transaction distribution -system.membus.trans_dist::ReadResp 207766 # Transaction distribution -system.membus.trans_dist::WriteReq 31050 # Transaction distribution -system.membus.trans_dist::WriteResp 31050 # Transaction distribution -system.membus.trans_dist::Writeback 135856 # Transaction distribution -system.membus.trans_dist::CleanEvict 15674 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78082 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41568 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14509 # Transaction distribution +system.membus.trans_dist::ReadReq 37995 # Transaction distribution +system.membus.trans_dist::ReadResp 208280 # Transaction distribution +system.membus.trans_dist::WriteReq 30910 # Transaction distribution +system.membus.trans_dist::WriteResp 30910 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133887 # Transaction distribution +system.membus.trans_dist::CleanEvict 14956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74359 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40536 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14484 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38794 # Transaction distribution -system.membus.trans_dist::ReadExResp 18985 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169644 # Transaction distribution +system.membus.trans_dist::ReadExReq 38707 # Transaction distribution +system.membus.trans_dist::ReadExResp 19074 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170286 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 784044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13724 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 777327 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 886261 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18481720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18673398 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18402504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18593084 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20991542 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125523 # Total snoops (count) -system.membus.snoop_fanout::samples 585264 # Request fanout histogram +system.membus.pkt_size::total 20911228 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120617 # Total snoops (count) +system.membus.snoop_fanout::samples 578108 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 585264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 578108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 585264 # Request fanout histogram -system.membus.reqLayer0.occupancy 81621000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 578108 # Request fanout histogram +system.membus.reqLayer0.occupancy 81934000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11798981 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11360491 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 986725496 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 977870256 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1119474906 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1121733386 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64610767 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64044757 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3659,56 +3665,56 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 957960 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 483276 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 165836 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 22284 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21444 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 38126 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 494242 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31050 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31050 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 364748 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 86802 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 81249 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41933 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123182 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 33 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50538 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50538 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 456132 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 989446 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 534228 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 146104 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20085 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 878 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 37998 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 475278 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30910 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30910 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 393382 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 89983 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 108688 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43642 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152330 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50244 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50244 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 437296 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1043214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 384499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1427713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31299443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6394691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37694134 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 458404 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1229453 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.314167 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.465653 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240411 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1496522 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34963008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3945788 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38908796 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 440874 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 905624 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.341764 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.476341 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 844039 68.65% 68.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 384574 31.28% 99.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 840 0.07% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 596992 65.92% 65.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 307754 33.98% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 878 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1229453 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 827244513 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 905624 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 871666747 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 355623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 356120 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 603608816 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 657174901 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 273833055 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 205942747 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2086 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2747 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 886ff6be1..d68f4bed9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832619 # Number of seconds simulated -sim_ticks 2832618668500 # Number of ticks simulated -final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832918 # Number of seconds simulated +sim_ticks 2832917624000 # Number of ticks simulated +final_tick 2832917624000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90415 # Simulator instruction rate (inst/s) -host_op_rate 109666 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2263800643 # Simulator tick rate (ticks/s) -host_mem_usage 628336 # Number of bytes of host memory used -host_seconds 1251.27 # Real time elapsed on the host -sim_insts 113133035 # Number of instructions simulated -sim_ops 137220830 # Number of ops (including micro ops) simulated +host_inst_rate 90340 # Simulator instruction rate (inst/s) +host_op_rate 109574 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2263201768 # Simulator tick rate (ticks/s) +host_mem_usage 628644 # Number of bytes of host memory used +host_seconds 1251.73 # Real time elapsed on the host +sim_insts 113081477 # Number of instructions simulated +sim_ops 137157144 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1316032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9392488 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory +system.physmem.bytes_read::total 10711336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1316032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8002368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8019892 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22810 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147278 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170132 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 125037 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129418 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 464550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3315482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3781026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2824780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2830965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2824780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3321668 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170127 # Number of read requests accepted -system.physmem.writeReqs 129798 # Number of write requests accepted -system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6611992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170133 # Number of read requests accepted +system.physmem.writeReqs 129418 # Number of write requests accepted +system.physmem.readBursts 170133 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129418 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10877696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10816 # Total number of bytes read from write queue +system.physmem.bytesWritten 8031936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10711400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8019892 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 169 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11277 # Per bank write bursts -system.physmem.perBankRdBursts::1 10595 # Per bank write bursts -system.physmem.perBankRdBursts::2 11086 # Per bank write bursts -system.physmem.perBankRdBursts::3 11282 # Per bank write bursts -system.physmem.perBankRdBursts::4 12957 # Per bank write bursts -system.physmem.perBankRdBursts::5 9975 # Per bank write bursts -system.physmem.perBankRdBursts::6 10510 # Per bank write bursts -system.physmem.perBankRdBursts::7 10855 # Per bank write bursts -system.physmem.perBankRdBursts::8 10363 # Per bank write bursts -system.physmem.perBankRdBursts::9 10082 # Per bank write bursts -system.physmem.perBankRdBursts::10 10269 # Per bank write bursts -system.physmem.perBankRdBursts::11 9303 # Per bank write bursts -system.physmem.perBankRdBursts::12 9940 # Per bank write bursts -system.physmem.perBankRdBursts::13 11053 # Per bank write bursts -system.physmem.perBankRdBursts::14 10302 # Per bank write bursts -system.physmem.perBankRdBursts::15 10142 # Per bank write bursts -system.physmem.perBankWrBursts::0 8501 # Per bank write bursts -system.physmem.perBankWrBursts::1 7938 # Per bank write bursts -system.physmem.perBankWrBursts::2 8637 # Per bank write bursts -system.physmem.perBankWrBursts::3 8770 # Per bank write bursts -system.physmem.perBankWrBursts::4 7610 # Per bank write bursts -system.physmem.perBankWrBursts::5 7376 # Per bank write bursts -system.physmem.perBankWrBursts::6 7709 # Per bank write bursts -system.physmem.perBankWrBursts::7 8071 # Per bank write bursts -system.physmem.perBankWrBursts::8 7782 # Per bank write bursts -system.physmem.perBankWrBursts::9 7594 # Per bank write bursts -system.physmem.perBankWrBursts::10 7680 # Per bank write bursts -system.physmem.perBankWrBursts::11 6982 # Per bank write bursts -system.physmem.perBankWrBursts::12 7590 # Per bank write bursts -system.physmem.perBankWrBursts::13 8396 # Per bank write bursts -system.physmem.perBankWrBursts::14 7757 # Per bank write bursts -system.physmem.perBankWrBursts::15 7487 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48557 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11298 # Per bank write bursts +system.physmem.perBankRdBursts::1 10506 # Per bank write bursts +system.physmem.perBankRdBursts::2 10925 # Per bank write bursts +system.physmem.perBankRdBursts::3 11199 # Per bank write bursts +system.physmem.perBankRdBursts::4 12883 # Per bank write bursts +system.physmem.perBankRdBursts::5 10202 # Per bank write bursts +system.physmem.perBankRdBursts::6 10845 # Per bank write bursts +system.physmem.perBankRdBursts::7 11219 # Per bank write bursts +system.physmem.perBankRdBursts::8 10577 # Per bank write bursts +system.physmem.perBankRdBursts::9 10527 # Per bank write bursts +system.physmem.perBankRdBursts::10 10037 # Per bank write bursts +system.physmem.perBankRdBursts::11 8948 # Per bank write bursts +system.physmem.perBankRdBursts::12 9970 # Per bank write bursts +system.physmem.perBankRdBursts::13 10631 # Per bank write bursts +system.physmem.perBankRdBursts::14 9988 # Per bank write bursts +system.physmem.perBankRdBursts::15 10209 # Per bank write bursts +system.physmem.perBankWrBursts::0 8496 # Per bank write bursts +system.physmem.perBankWrBursts::1 7860 # Per bank write bursts +system.physmem.perBankWrBursts::2 8364 # Per bank write bursts +system.physmem.perBankWrBursts::3 8532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7663 # Per bank write bursts +system.physmem.perBankWrBursts::5 7568 # Per bank write bursts +system.physmem.perBankWrBursts::6 8029 # Per bank write bursts +system.physmem.perBankWrBursts::7 8274 # Per bank write bursts +system.physmem.perBankWrBursts::8 8070 # Per bank write bursts +system.physmem.perBankWrBursts::9 7909 # Per bank write bursts +system.physmem.perBankWrBursts::10 7508 # Per bank write bursts +system.physmem.perBankWrBursts::11 6646 # Per bank write bursts +system.physmem.perBankWrBursts::12 7551 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7465 # Per bank write bursts +system.physmem.perBankWrBursts::15 7558 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2832618457500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 2832917392000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166575 # Read request sizes (log2) +system.physmem.readPktSize::6 166581 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125037 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,155 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.281406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.810971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.663684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23300 37.49% 37.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14989 24.12% 61.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6559 10.55% 72.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3523 5.67% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2511 4.04% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1609 2.59% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.56% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1065 1.71% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6997 11.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62145 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6266 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.121768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 563.971651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6265 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6266 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.028567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.454463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.210745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5460 87.14% 87.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.76% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.48% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.68% 92.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.41% 92.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.19% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.85% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.24% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.18% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 21 0.34% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.63% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 23 0.37% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.66% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads -system.physmem.totQLat 2109686750 # Total ticks spent queuing -system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.19% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6266 # Writes before turning the bus around for reads +system.physmem.totQLat 2116809750 # Total ticks spent queuing +system.physmem.totMemAccLat 5303634750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12454.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31204.46 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing -system.physmem.readRowHits 139766 # Number of row buffer hits during reads -system.physmem.writeRowHits 93986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes -system.physmem.avgGap 9444422.63 # Average gap between requests -system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.462100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states -system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 139542 # Number of row buffer hits during reads +system.physmem.writeRowHits 93775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 9457212.27 # Average gap between requests +system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246546720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134524500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 694792800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419813280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83588992920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626422631000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896539228820 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.466691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705562728250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32757782250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.364017 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states -system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states +system.physmem_1.actEnergy 223269480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121823625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630918600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 393420240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81878542335 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627923026250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896202928130 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.347979 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2708066096500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30247332250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -327,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46909632 # Number of BP lookups -system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits +system.cpu.branchPred.lookups 46858822 # Number of BP lookups +system.cpu.branchPred.condPredicted 24018425 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233385 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29501817 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21322160 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.274057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11724285 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33905 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -366,79 +367,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 71741 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 71435 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71435 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29241 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22400 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19794 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 426.153638 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2576.445985 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 49864 96.56% 96.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.13% 97.69% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.02% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 340 0.66% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.43% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 51641 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9159.086359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8173.463802 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17339 98.96% 98.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17522 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.616564 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493575 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131327318816 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37570000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7000000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6185500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1198500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131382086816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6381 82.69% 82.69% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1336 17.31% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7717 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71435 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71435 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7717 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7717 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79152 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25458814 # DTB read hits -system.cpu.dtb.read_misses 61805 # DTB read misses -system.cpu.dtb.write_hits 19912938 # DTB write hits -system.cpu.dtb.write_misses 9936 # DTB write misses +system.cpu.dtb.read_hits 25445516 # DTB read hits +system.cpu.dtb.read_misses 61525 # DTB read misses +system.cpu.dtb.write_hits 19906341 # DTB write hits +system.cpu.dtb.write_misses 9910 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25520619 # DTB read accesses -system.cpu.dtb.write_accesses 19922874 # DTB write accesses +system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25507041 # DTB read accesses +system.cpu.dtb.write_accesses 19916251 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45371752 # DTB hits -system.cpu.dtb.misses 71741 # DTB misses -system.cpu.dtb.accesses 45443493 # DTB accesses +system.cpu.dtb.hits 45351857 # DTB hits +system.cpu.dtb.misses 71435 # DTB misses +system.cpu.dtb.accesses 45423292 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,54 +474,55 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11944 # Table walker walks requested -system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated +system.cpu.itb.walker.walks 11899 # Table walker walks requested +system.cpu.itb.walker.walksShort 11899 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3941 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 616.629560 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2880.318774 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11122 95.24% 95.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.25% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::20480-24575 32 0.27% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11678 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12870.386024 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8688.844550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.26% 73.26% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 892 25.13% 98.39% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-49151 55 1.55% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3549 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.962955 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.189019 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 889977000 3.71% 3.71% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 23117314916 96.29% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 24007842416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3008 90.38% 90.38% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 320 9.62% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11899 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11899 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66274552 # ITB inst hits -system.cpu.itb.inst_misses 11944 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15227 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66219818 # ITB inst hits +system.cpu.itb.inst_misses 11899 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -524,143 +531,143 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66286496 # ITB inst accesses -system.cpu.itb.hits 66274552 # DTB hits -system.cpu.itb.misses 11944 # DTB misses -system.cpu.itb.accesses 66286496 # DTB accesses -system.cpu.numCycles 277645869 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66231717 # ITB inst accesses +system.cpu.itb.hits 66219818 # DTB hits +system.cpu.itb.misses 11899 # DTB misses +system.cpu.itb.accesses 66231717 # DTB accesses +system.cpu.numCycles 278809396 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104752228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184594753 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46858822 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33046445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161837102 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6149420 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189977 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 9772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 357687 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 560902 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66220013 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1133469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5179 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.831431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.217897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171565839 63.36% 63.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29222654 10.79% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14067780 5.20% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55926286 20.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 270782559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168068 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77849645 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121907615 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64584092 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3844418 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2596789 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423202 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486322 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157325754 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3698413 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2596789 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83693975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11775859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76672657 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62585691 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33457588 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146699029 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 957260 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 452831 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63761 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16550 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30707740 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150373398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678238170 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164317610 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141712294 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8661101 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2840653 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644485 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26394295 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21292545 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1689185 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2215742 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143439670 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121732 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143229007 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270292 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8404254 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14686510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125844 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270782559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.528945 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865530 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182544969 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45137079 16.67% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32020155 11.83% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10269839 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810484 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270782559 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7336568 32.74% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631848 25.13% 57.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9441706 42.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95930740 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113813 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -684,101 +691,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26175663 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20997878 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued -system.cpu.iq.rate 0.516124 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143229007 # Type of FU issued +system.cpu.iq.rate 0.513717 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22410154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156464 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579885434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153971015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140120635 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165613479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 322744 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1495175 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 703988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87827 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2596789 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1243570 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 532137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145762333 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26394295 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21292545 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096246 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17995 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 497968 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317449 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788645 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142286885 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25773498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 870795 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200573 # number of nop insts executed -system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed -system.cpu.iew.exec_branches 26519669 # Number of branches executed -system.cpu.iew.exec_stores 20875979 # Number of stores executed -system.cpu.iew.exec_rate 0.512728 # Inst execution rate -system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271886 # num instructions producing a value -system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value +system.cpu.iew.exec_nop 200931 # number of nop insts executed +system.cpu.iew.exec_refs 46642508 # number of memory reference insts executed +system.cpu.iew.exec_branches 26501737 # Number of branches executed +system.cpu.iew.exec_stores 20869010 # Number of stores executed +system.cpu.iew.exec_rate 0.510337 # Inst execution rate +system.cpu.iew.wb_sent 141900432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140132002 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63223126 # num instructions producing a value +system.cpu.iew.wb_consumers 95712973 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back +system.cpu.iew.wb_rate 0.502609 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660549 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7603118 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995888 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755464 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267848804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.512648 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.117834 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194453826 72.60% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43232556 16.14% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15468323 5.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4394328 1.64% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6341907 2.37% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1685586 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800919 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412081 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059278 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113287940 # Number of instructions committed -system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267848804 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113236382 # Number of instructions committed +system.cpu.commit.committedOps 137312049 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45505753 # Number of memory references committed -system.cpu.commit.loads 24911268 # Number of loads committed -system.cpu.commit.membars 814898 # Number of memory barriers committed -system.cpu.commit.branches 26034583 # Number of branches committed +system.cpu.commit.refs 45487677 # Number of memory references committed +system.cpu.commit.loads 24899120 # Number of loads committed +system.cpu.commit.membars 814929 # Number of memory barriers committed +system.cpu.commit.branches 26016406 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120199859 # Number of committed integer instructions. -system.cpu.commit.function_calls 4887749 # Number of function calls committed. +system.cpu.commit.int_insts 120142081 # Number of committed integer instructions. +system.cpu.commit.function_calls 4881652 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91703052 66.78% 66.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112745 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -802,501 +809,507 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24899120 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20588557 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction -system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 388465780 # The number of ROB reads -system.cpu.rob.rob_writes 292930075 # The number of ROB writes -system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113133035 # Number of Instructions Simulated -system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads -system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155797969 # number of integer regfile reads -system.cpu.int_regfile_writes 88612711 # number of integer regfile writes -system.cpu.fp_regfile_reads 9524 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137312049 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059278 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389547304 # The number of ROB reads +system.cpu.rob.rob_writes 292761659 # The number of ROB writes +system.cpu.timesIdled 892855 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8026837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387025853 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113081477 # Number of Instructions Simulated +system.cpu.committedOps 137157144 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.465562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.465562 # CPI: Total CPI of All Threads +system.cpu.ipc 0.405587 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.405587 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155726558 # number of integer regfile reads +system.cpu.int_regfile_writes 88564579 # number of integer regfile writes +system.cpu.fp_regfile_reads 9527 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502896975 # number of cc regfile reads -system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes -system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes -system.cpu.dcache.tags.replacements 840044 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks. +system.cpu.cc_regfile_reads 502647570 # number of cc regfile reads +system.cpu.cc_regfile_writes 53157224 # number of cc regfile writes +system.cpu.misc_regfile_reads 348272878 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521665 # number of misc regfile writes +system.cpu.dcache.tags.replacements 837515 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40092431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838027 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.841455 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179336842 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179336842 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23308523 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23308523 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15546666 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15546666 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346021 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346021 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441431 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441431 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460353 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460353 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38855189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38855189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39201210 # number of overall hits -system.cpu.dcache.overall_hits::total 39201210 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 708825 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 708825 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3606988 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3606988 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177865 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177865 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27388 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27388 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4315813 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4315813 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4493678 # number of overall misses -system.cpu.dcache.overall_misses::total 4493678 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11757743000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11757743000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 232345213174 # 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ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6403711500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19964415469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19964415469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 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overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 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LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19975151483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701142500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126808000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126808000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26362087983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26362087983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28063230483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28063230483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277199000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277199000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075698951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075698951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352897951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352897951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017210 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017210 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015648 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015648 # mshr miss rate for WriteReq accesses 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rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067 # average WriteReq mshr uncacheable latency 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511.157898 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998355 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998355 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1886833 # number of replacements +system.cpu.icache.tags.tagsinuse 511.154154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64237730 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1887345 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.036029 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64290369 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64290369 # number of overall hits -system.cpu.icache.overall_hits::total 64290369 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981370 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981370 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981370 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981370 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981370 # number of overall misses -system.cpu.icache.overall_misses::total 1981370 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28130756994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28130756994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28130756994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14197.629415 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4834 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68104377 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68104377 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64237730 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64237730 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64237730 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64237730 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64237730 # number of overall hits +system.cpu.icache.overall_hits::total 64237730 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1979279 # number of ReadReq misses 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accesses +system.cpu.icache.overall_miss_rate::total 0.029891 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14221.365705 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4340 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.946108 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91786 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91786 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91786 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91786 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889584 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1889584 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1889584 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1889584 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1889584 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1889584 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1886833 # number of writebacks +system.cpu.icache.writebacks::total 1886833 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91909 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91909 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91909 # number of 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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16238965500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2439385500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2439385500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658508500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658508500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3235500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 858500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2439385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17897474000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20340953500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3235500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 858500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2439385500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17897474000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20340953500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340103000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5546780500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5886883500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4471146500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4471146500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340103000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10017927000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10358030000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000465 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987277 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987277 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024466 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024466 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060271 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2710500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1060500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3771000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192695000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192695000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16252241500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16252241500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425990000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425990000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1667259500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1667259500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2710500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425990000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17919501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20349262000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2710500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425990000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17919501000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20349262000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888077000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6228194000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756881000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644958000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10985075000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988026 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024652 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024652 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060442 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060442 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5484076 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758688 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47112 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 127589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556141 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194580 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 820637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1846839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541297 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8416591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239034368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98344937 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 337643277 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 197136 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158851 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2973765 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 79083 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5400072997 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834880345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1303595064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19421986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74092896 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30172 # Transaction distribution -system.iobus.trans_dist::ReadResp 30172 # Transaction distribution +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1514,9 +1528,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1539,207 +1553,209 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 647500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6192000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 167000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 33054500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186395016 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 1.005392 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 256608771000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005392 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062837 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062837 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328023 # Number of tag accesses -system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses -system.iocache.ReadReq_misses::total 223 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses -system.iocache.demand_misses::total 223 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 223 # number of overall misses -system.iocache.overall_misses::total 223 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits +system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses +system.iocache.ReadReq_misses::total 249 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses +system.iocache.demand_misses::total 249 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 249 # number of overall misses +system.iocache.overall_misses::total 249 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31311876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31311876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715518140 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715518140 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31311876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31311876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31311876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31311876 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125750.506024 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125750.506024 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 725 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 77 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.415584 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18861876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2905768140 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18861876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18861876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18861876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34133 # Transaction distribution -system.membus.trans_dist::ReadResp 67584 # Transaction distribution +system.membus.trans_dist::ReadResp 67565 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::Writeback 125417 # Transaction distribution -system.membus.trans_dist::CleanEvict 7628 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.membus.trans_dist::WritebackDirty 125037 # Transaction distribution +system.membus.trans_dist::CleanEvict 7766 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution -system.membus.trans_dist::ReadExReq 133608 # Transaction distribution -system.membus.trans_dist::ReadExResp 133608 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution +system.membus.trans_dist::ReadExReq 133659 # Transaction distribution +system.membus.trans_dist::ReadExResp 133659 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33433 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455099 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 671495 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 487 # Total snoops (count) -system.membus.snoop_fanout::samples 402837 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16416028 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16579433 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18894633 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 513 # Total snoops (count) +system.membus.snoop_fanout::samples 402650 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402650 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402837 # Request fanout histogram -system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402650 # Request fanout histogram +system.membus.reqLayer0.occupancy 83677500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1748500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 874312374 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 988164899 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64093300 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d7415aa23..8c271cc38 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824718 # Number of seconds simulated -sim_ticks 2824717821500 # Number of ticks simulated -final_tick 2824717821500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824799 # Number of seconds simulated +sim_ticks 2824799320500 # Number of ticks simulated +final_tick 2824799320500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249146 # Simulator instruction rate (inst/s) -host_op_rate 302232 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5724351305 # Simulator tick rate (ticks/s) -host_mem_usage 631692 # Number of bytes of host memory used -host_seconds 493.46 # Real time elapsed on the host -sim_insts 122942928 # Number of instructions simulated -sim_ops 149138280 # Number of ops (including micro ops) simulated +host_inst_rate 251577 # Simulator instruction rate (inst/s) +host_op_rate 305184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5777436345 # Simulator tick rate (ticks/s) +host_mem_usage 631984 # Number of bytes of host memory used +host_seconds 488.94 # Real time elapsed on the host +sim_insts 123005008 # Number of instructions simulated +sim_ops 149215388 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 536420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4179876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 910464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 318592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1655680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 408768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3010752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 540900 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4166756 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 103808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 328256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1677824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 415296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3014912 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11149640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 536420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 318592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 408768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1385572 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8394624 # Number of bytes written to this memory +system.physmem.bytes_read::total 11180680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 540900 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 103808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 328256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 415296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1388260 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8418624 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8412148 # Number of bytes written to this memory +system.physmem.bytes_written::total 8436148 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16835 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65830 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1903 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14226 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 25870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 63 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 47043 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 26216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6489 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 47108 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131166 # Number of write requests responded to by this memory +system.physmem.num_reads::total 183671 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131541 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135547 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135922 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1479750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 322320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 112787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 586140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 144711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1065859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1475063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 36749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 327613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 116205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 593962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 147018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1067301 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3947169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 112787 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 144711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490517 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2971845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3958044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191483 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 36749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 116205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 147018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491454 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2980256 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2978049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2971845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2986459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2980256 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1485954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 322320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 112787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 586140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 144711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1065859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1481266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 36749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 327613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 116205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 593962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 147018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1067301 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6925218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 100502 # Number of read requests accepted -system.physmem.writeReqs 68912 # Number of write requests accepted -system.physmem.readBursts 100502 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68912 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6426176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 4409728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6432128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4410368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6944503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 101122 # Number of read requests accepted +system.physmem.writeReqs 69399 # Number of write requests accepted +system.physmem.readBursts 101122 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69399 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6464000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 4440192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6471808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4441536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17980 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6920 # Per bank write bursts -system.physmem.perBankRdBursts::1 6286 # Per bank write bursts -system.physmem.perBankRdBursts::2 6764 # Per bank write bursts -system.physmem.perBankRdBursts::3 6403 # Per bank write bursts -system.physmem.perBankRdBursts::4 6105 # Per bank write bursts -system.physmem.perBankRdBursts::5 5950 # Per bank write bursts -system.physmem.perBankRdBursts::6 6704 # Per bank write bursts -system.physmem.perBankRdBursts::7 6701 # Per bank write bursts -system.physmem.perBankRdBursts::8 6487 # Per bank write bursts -system.physmem.perBankRdBursts::9 6589 # Per bank write bursts -system.physmem.perBankRdBursts::10 6182 # Per bank write bursts -system.physmem.perBankRdBursts::11 5526 # Per bank write bursts -system.physmem.perBankRdBursts::12 5641 # Per bank write bursts -system.physmem.perBankRdBursts::13 6650 # Per bank write bursts -system.physmem.perBankRdBursts::14 6151 # Per bank write bursts -system.physmem.perBankRdBursts::15 5350 # Per bank write bursts -system.physmem.perBankWrBursts::0 4550 # Per bank write bursts -system.physmem.perBankWrBursts::1 4246 # Per bank write bursts -system.physmem.perBankWrBursts::2 4783 # Per bank write bursts -system.physmem.perBankWrBursts::3 4329 # Per bank write bursts -system.physmem.perBankWrBursts::4 4133 # Per bank write bursts -system.physmem.perBankWrBursts::5 4124 # Per bank write bursts -system.physmem.perBankWrBursts::6 4743 # Per bank write bursts -system.physmem.perBankWrBursts::7 4271 # Per bank write bursts -system.physmem.perBankWrBursts::8 4451 # Per bank write bursts -system.physmem.perBankWrBursts::9 4796 # Per bank write bursts -system.physmem.perBankWrBursts::10 4218 # Per bank write bursts -system.physmem.perBankWrBursts::11 3947 # Per bank write bursts -system.physmem.perBankWrBursts::12 3851 # Per bank write bursts -system.physmem.perBankWrBursts::13 4779 # Per bank write bursts -system.physmem.perBankWrBursts::14 4130 # Per bank write bursts -system.physmem.perBankWrBursts::15 3551 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 22992 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 7206 # Per bank write bursts +system.physmem.perBankRdBursts::1 6389 # Per bank write bursts +system.physmem.perBankRdBursts::2 6982 # Per bank write bursts +system.physmem.perBankRdBursts::3 6703 # Per bank write bursts +system.physmem.perBankRdBursts::4 6109 # Per bank write bursts +system.physmem.perBankRdBursts::5 6146 # Per bank write bursts +system.physmem.perBankRdBursts::6 6610 # Per bank write bursts +system.physmem.perBankRdBursts::7 6743 # Per bank write bursts +system.physmem.perBankRdBursts::8 6516 # Per bank write bursts +system.physmem.perBankRdBursts::9 6576 # Per bank write bursts +system.physmem.perBankRdBursts::10 6052 # Per bank write bursts +system.physmem.perBankRdBursts::11 5500 # Per bank write bursts +system.physmem.perBankRdBursts::12 5540 # Per bank write bursts +system.physmem.perBankRdBursts::13 6495 # Per bank write bursts +system.physmem.perBankRdBursts::14 6075 # Per bank write bursts +system.physmem.perBankRdBursts::15 5358 # Per bank write bursts +system.physmem.perBankWrBursts::0 4814 # Per bank write bursts +system.physmem.perBankWrBursts::1 4268 # Per bank write bursts +system.physmem.perBankWrBursts::2 4976 # Per bank write bursts +system.physmem.perBankWrBursts::3 4599 # Per bank write bursts +system.physmem.perBankWrBursts::4 4151 # Per bank write bursts +system.physmem.perBankWrBursts::5 4285 # Per bank write bursts +system.physmem.perBankWrBursts::6 4619 # Per bank write bursts +system.physmem.perBankWrBursts::7 4309 # Per bank write bursts +system.physmem.perBankWrBursts::8 4473 # Per bank write bursts +system.physmem.perBankWrBursts::9 4780 # Per bank write bursts +system.physmem.perBankWrBursts::10 4110 # Per bank write bursts +system.physmem.perBankWrBursts::11 3894 # Per bank write bursts +system.physmem.perBankWrBursts::12 3790 # Per bank write bursts +system.physmem.perBankWrBursts::13 4672 # Per bank write bursts +system.physmem.perBankWrBursts::14 4032 # Per bank write bursts +system.physmem.perBankWrBursts::15 3606 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2823151552500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2823233051500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 100502 # Read request sizes (log2) +system.physmem.readPktSize::6 101122 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68912 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 76732 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69399 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 77320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,170 +182,170 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.584628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.263333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.433492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16168 41.12% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9688 24.64% 65.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3830 9.74% 75.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2076 5.28% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1590 4.04% 84.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 981 2.49% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 594 1.51% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 552 1.40% 90.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3840 9.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3599 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.894137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 471.050714 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3597 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39537 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 275.792296 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.681718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.680924 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16252 41.11% 41.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9627 24.35% 65.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3980 10.07% 75.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2061 5.21% 80.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1623 4.11% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1029 2.60% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 580 1.47% 88.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 548 1.39% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3837 9.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39537 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.947135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 470.013093 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3611 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3599 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3599 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.144762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.954400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.164866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 6 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.14% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3182 88.41% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 82 2.28% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 48 1.33% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 63 1.75% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 10 0.28% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 1.50% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 28 0.78% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.14% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.25% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.47% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.11% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 52 1.44% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.14% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 13 0.36% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.08% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3599 # Writes before turning the bus around for reads -system.physmem.totQLat 1312823000 # Total ticks spent queuing -system.physmem.totMemAccLat 3195491750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 502045000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13074.75 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3613 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3613 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.202325 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.997759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.552053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 4 0.11% 0.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.14% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3178 87.96% 88.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 101 2.80% 91.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 1.19% 92.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 66 1.83% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 15 0.42% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 55 1.52% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 32 0.89% 96.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.17% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 5 0.14% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.33% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.06% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.08% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 56 1.55% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.30% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.22% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3613 # Writes before turning the bus around for reads +system.physmem.totQLat 1315778000 # Total ticks spent queuing +system.physmem.totMemAccLat 3209528000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 505000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13027.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31824.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31777.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.91 # Average write queue length when enqueuing -system.physmem.readRowHits 80981 # Number of row buffer hits during reads -system.physmem.writeRowHits 49010 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.12 # Row buffer hit rate for writes -system.physmem.avgGap 16664216.37 # Average gap between requests -system.physmem.pageHitRate 76.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85152375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 404274000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 227959920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73215548100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1622782125750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876644765225 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.446746 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640312790250 # Time in different power states -system.physmem_0.memoryStateTime::REF 91908700000 # Time in different power states +system.physmem.avgWrQLen 30.16 # Average write queue length when enqueuing +system.physmem.readRowHits 81477 # Number of row buffer hits during reads +system.physmem.writeRowHits 49363 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.13 # Row buffer hit rate for writes +system.physmem.avgGap 16556512.40 # Average gap between requests +system.physmem.pageHitRate 76.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 159508440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86917875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 412503000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 233416080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73304297100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624538062500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1878513716355 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.386003 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640260933000 # Time in different power states +system.physmem_0.memoryStateTime::REF 91911560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20242228250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20369491500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140963760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76741500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 378892800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 218525040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72451612440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1618075692000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1871115844740 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.608024 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641479820250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91908700000 # Time in different power states +system.physmem_1.actEnergy 139391280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75900000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 375273600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 216153360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72455887440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616321661750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1869363278790 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.677649 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641542244250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91911560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19062807500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19077733750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -399,47 +395,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 4993 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4993 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4993 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4993 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4993 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.255415 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -14647046374 -25.54% -25.54% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993140750 125.54% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 57346094376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2743 66.90% 66.90% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.10% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4100 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4993 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4963 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4963 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.356118 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -18905470420 -35.61% -35.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993161750 135.61% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 53087691330 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2701 66.40% 66.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1367 33.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4068 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4963 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4993 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4100 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4963 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4068 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4100 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9093 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4068 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9031 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12030030 # DTB read hits -system.cpu0.dtb.read_misses 4190 # DTB read misses -system.cpu0.dtb.write_hits 9398007 # DTB write hits -system.cpu0.dtb.write_misses 803 # DTB write misses +system.cpu0.dtb.read_hits 11938297 # DTB read hits +system.cpu0.dtb.read_misses 4171 # DTB read misses +system.cpu0.dtb.write_hits 9295240 # DTB write hits +system.cpu0.dtb.write_misses 792 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2915 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2875 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 721 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 692 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12034220 # DTB read accesses -system.cpu0.dtb.write_accesses 9398810 # DTB write accesses +system.cpu0.dtb.perms_faults 167 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 11942468 # DTB read accesses +system.cpu0.dtb.write_accesses 9296032 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21428037 # DTB hits -system.cpu0.dtb.misses 4993 # DTB misses -system.cpu0.dtb.accesses 21433030 # DTB accesses +system.cpu0.dtb.hits 21233537 # DTB hits +system.cpu0.dtb.misses 4963 # DTB misses +system.cpu0.dtb.accesses 21238500 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -469,648 +465,650 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2307 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2307 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2307 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2307 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2307 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.255417 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -14647174874 -25.54% -25.54% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993269250 125.54% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 57346094376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1275 74.08% 74.08% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 446 25.92% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1721 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2305 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.356120 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -18905570920 -35.61% -35.61% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993262250 135.61% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 53087691330 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1266 73.91% 73.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 447 26.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1713 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2307 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2307 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1721 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1721 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4028 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57257258 # ITB inst hits -system.cpu0.itb.inst_misses 2307 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1713 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1713 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4018 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57022290 # ITB inst hits +system.cpu0.itb.inst_misses 2305 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1727 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1719 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57259565 # ITB inst accesses -system.cpu0.itb.hits 57257258 # DTB hits -system.cpu0.itb.misses 2307 # DTB misses -system.cpu0.itb.accesses 57259565 # DTB accesses -system.cpu0.numCycles 69320920 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57024595 # ITB inst accesses +system.cpu0.itb.hits 57022290 # DTB hits +system.cpu0.itb.misses 2305 # DTB misses +system.cpu0.itb.accesses 57024595 # DTB accesses +system.cpu0.numCycles 68977361 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55846469 # Number of instructions committed -system.cpu0.committedOps 67799019 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59476753 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4636 # Number of float alu accesses -system.cpu0.num_func_calls 5739649 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7404981 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59476753 # number of integer instructions -system.cpu0.num_fp_insts 4636 # number of float instructions -system.cpu0.num_int_register_reads 109855675 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41239490 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3530 # number of times the floating registers were read +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed +system.cpu0.committedInsts 55612915 # Number of instructions committed +system.cpu0.committedOps 67456889 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59167201 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4525 # Number of float alu accesses +system.cpu0.num_func_calls 5730859 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7383240 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59167201 # number of integer instructions +system.cpu0.num_fp_insts 4525 # number of float instructions +system.cpu0.num_int_register_reads 109233677 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41018104 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3419 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 206363052 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25211275 # number of times the CC registers were written -system.cpu0.num_mem_refs 21994746 # number of memory refs -system.cpu0.num_load_insts 12174830 # Number of load instructions -system.cpu0.num_store_insts 9819916 # Number of store instructions -system.cpu0.num_idle_cycles 65448484.972740 # Number of idle cycles -system.cpu0.num_busy_cycles 3872435.027260 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055862 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944138 # Percentage of idle cycles -system.cpu0.Branches 13529823 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2175 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46835768 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 49875 0.07% 68.07% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3855 0.01% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::MemRead 12174830 17.67% 85.74% # Class of executed instruction -system.cpu0.op_class::MemWrite 9819916 14.26% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 205348706 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25186036 # number of times the CC registers were written +system.cpu0.num_mem_refs 21795373 # number of memory refs +system.cpu0.num_load_insts 12079832 # Number of load instructions +system.cpu0.num_store_insts 9715541 # Number of store instructions +system.cpu0.num_idle_cycles 65194671.854537 # Number of idle cycles +system.cpu0.num_busy_cycles 3782689.145463 # Number of busy cycles +system.cpu0.not_idle_fraction 0.054840 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.945160 # Percentage of idle cycles +system.cpu0.Branches 13504260 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2176 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46697221 68.12% 68.13% # Class of executed instruction +system.cpu0.op_class::IntMult 49891 0.07% 68.20% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3798 0.01% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction +system.cpu0.op_class::MemRead 12079832 17.62% 85.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 9715541 14.17% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68886419 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833472 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996601 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46054787 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833984 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.222627 # Average number of references to valid blocks. +system.cpu0.op_class::total 68548459 # Class of executed instruction +system.cpu0.dcache.tags.replacements 833427 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996688 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 46067752 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833939 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.241153 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.685791 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.479753 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.026378 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.804679 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936886 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022421 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011770 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028915 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 476.386497 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.984373 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.249015 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.376803 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.930442 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023407 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012205 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.033939 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193142781 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193142781 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11422254 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3666502 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4281798 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6456449 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25827003 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9049094 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2626435 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3309918 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 3942780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18928227 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 169795 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 55205 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74478 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86629 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 386107 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210372 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75336 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 77039 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 87626 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450373 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 211678 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 77328 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 79652 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 91425 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 193252454 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193252454 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11340872 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3665086 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4347150 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6492094 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25845202 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8951769 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2627923 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3357260 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 3986228 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18923180 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 168663 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54737 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74832 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87703 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 385935 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 206642 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75155 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 78814 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 89773 # number of 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+system.cpu0.dcache.overall_accesses::total 47176100 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013905 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015363 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021566 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031088 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019768 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013996 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011560 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027952 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.217410 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.067131 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.225752 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.248283 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.301060 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.309610 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.264544 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016154 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.034742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.046263 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.082817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038485 # miss rate for LoadLockedReq accesses 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accesses +system.cpu0.dcache.overall_miss_rate::total 0.042856 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18050.895324 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14935.440105 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17988.879021 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11915.149236 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60770.735041 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67858.390273 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 70735.642702 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63706.476050 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14240.850277 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14246.926498 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14550.703183 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11701.087258 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 38224.137931 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 38224.137931 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32984.059191 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41496.236169 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62384.871917 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 49370.165942 # average overall miss latency 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number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 692075 # number of writebacks -system.cpu0.dcache.writebacks::total 692075 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 65 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15172 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 93547 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 108784 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 43736 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1006705 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1050441 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1618 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2327 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5382 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9327 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 65 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 58908 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 1100252 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1159225 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 65 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 58908 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 1100252 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1159225 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 56510 # 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of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1022 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1248 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2430 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4700 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 23 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 23 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 86929 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 131660 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 199261 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 417850 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 104296 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 153657 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 227501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 485454 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3591 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5668 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8430 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17689 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2928 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4375 # number of WriteReq MSHR uncacheable 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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3850166500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810886000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3506727500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6410528421 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11728141921 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 228034000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 306929500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 499195000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1034158500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 15604000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 21310500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39501500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2777126500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4660825500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8140356421 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15578308421 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3005160500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4967755000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8639551421 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16612466921 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 597998000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1071505000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1718751500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3388254500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 486771500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 812532000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1333957452 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2633260952 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1084769500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1884037000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3052708952 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6021515452 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015178 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018153 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016680 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009377 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011449 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015330 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017500 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008422 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238417 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.207372 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225980 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.128883 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013107 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015481 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.025462 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000252 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013625 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016918 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017033 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.008962 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016163 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019479 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019241 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010296 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17098.575473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14526.640402 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15569.448445 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15583.869975 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59531.411289 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67161.961580 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72717.179816 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68670.358870 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13130.304601 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13953.243624 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17676.876771 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15297.297497 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15268.101761 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17075.721154 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16255.761317 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16258.723404 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 33739.130435 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33739.130435 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31947.065996 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35400.467112 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40852.732953 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37282.059162 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28813.765629 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32330.157429 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37975.883275 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34220.475928 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166526.872737 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 189044.636556 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203885.112693 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191545.847702 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166247.096995 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185721.600000 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200083.613619 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188493.983679 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166401.211842 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187597.032759 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 202206.329204 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190199.167756 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 692230 # number of writebacks +system.cpu0.dcache.writebacks::total 692230 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 73 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15389 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 95422 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 110884 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 43862 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1018548 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1062410 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1613 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2364 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5475 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9452 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 59251 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1113970 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1173294 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 59251 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1113970 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1173294 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 57113 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 80429 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112878 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 250420 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 30733 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52678 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 88857 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 172268 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 17812 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 22623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 28947 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 69382 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1092 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1459 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2631 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5182 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 29 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 87846 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 133107 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 201735 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 422688 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 105658 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 155730 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 230682 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 492070 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3488 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5443 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8526 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17457 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2835 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4201 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6746 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13782 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6323 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9644 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 15272 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31239 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 973626500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1170429000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1752405000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3896460500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1836934000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3551134500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6426494942 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11814563442 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 237039500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 314888500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 508808000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1060736000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 18701500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 25087500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 42425000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86214000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 1079500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1079500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2810560500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4721563500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8178899942 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15711023942 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3047600000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 5036452000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8687707942 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16771759942 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 617743500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1078938000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1840814500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3537496000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506139500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 824481000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1437530452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2768150952 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1123883000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1903419000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3278344952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6305646952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015344 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018103 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016846 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011560 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015252 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017445 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008492 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.211302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.227868 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132218 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.014025 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017656 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.026880 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011063 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000309 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013767 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016856 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017105 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009061 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016372 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019457 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019351 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010430 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17047.371001 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14552.325654 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15524.770106 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15559.701701 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59770.735041 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67412.098030 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72324.014338 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68582.461293 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13307.854256 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13918.954162 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17577.227347 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15288.345680 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17125.915751 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17194.996573 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16125.047510 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16637.205712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 37224.137931 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37224.137931 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31994.177310 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35471.939868 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40542.790998 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37169.316238 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28844.006133 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32340.923393 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37660.970262 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.093609 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177105.361239 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198224.875988 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215905.993432 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202640.545340 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178532.451499 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196258.271840 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213093.752149 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200852.630387 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 177745.215879 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197368.208212 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214663.760608 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201851.754282 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1975887 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.441259 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 94009429 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1976399 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.566017 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12738207000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.789749 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.948279 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.353975 # 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-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2681572500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6562452000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7336863488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16580887988 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012951 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012951 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012951 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13331.913902 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 1980846 # number of writebacks +system.cpu0.icache.writebacks::total 1980846 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43949 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43949 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 43949 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43949 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 43949 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43949 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 203984 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 502026 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 553639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1259649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 203984 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 502026 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 553639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1259649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 203984 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 502026 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 553639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1259649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2649785000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6659762500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7509042490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16818589990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2649785000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6659762500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7509042490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16818589990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2649785000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6659762500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7509042490 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16818589990 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013139 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013139 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013139 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13351.806726 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13351.806726 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13351.806726 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1141,55 +1139,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1988 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1988 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 507 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1481 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1988 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1988 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1988 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1694 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13442.148760 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11640.659125 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7340.460279 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1298 76.62% 76.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 23.32% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1694 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1928 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1928 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 500 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1428 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1928 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1928 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1928 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1628 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13253.992629 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11553.834233 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6560.213470 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 361 22.17% 22.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 74 4.55% 26.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 476 29.24% 55.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 145 8.91% 64.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 172 10.57% 75.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 41 2.52% 77.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 347 21.31% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 12 0.74% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1628 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1189 70.19% 70.19% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 505 29.81% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1694 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1988 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1130 69.41% 69.41% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 498 30.59% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1628 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1928 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1988 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1694 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1928 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1628 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1694 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3682 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1628 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3556 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3877487 # DTB read hits -system.cpu1.dtb.read_misses 1782 # DTB read misses -system.cpu1.dtb.write_hits 2737174 # DTB write hits -system.cpu1.dtb.write_misses 206 # DTB write misses -system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3876436 # DTB read hits +system.cpu1.dtb.read_misses 1705 # DTB read misses +system.cpu1.dtb.write_hits 2738772 # DTB write hits +system.cpu1.dtb.write_misses 223 # DTB write misses +system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1170 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1110 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 242 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 221 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3879269 # DTB read accesses -system.cpu1.dtb.write_accesses 2737380 # DTB write accesses +system.cpu1.dtb.read_accesses 3878141 # DTB read accesses +system.cpu1.dtb.write_accesses 2738995 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6614661 # DTB hits -system.cpu1.dtb.misses 1988 # DTB misses -system.cpu1.dtb.accesses 6616649 # DTB accesses +system.cpu1.dtb.hits 6615208 # DTB hits +system.cpu1.dtb.misses 1928 # DTB misses +system.cpu1.dtb.accesses 6617136 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1219,130 +1222,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1030 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1030 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 846 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1030 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1030 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1030 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 746 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12997.319035 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11244.232149 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6525.015841 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 210 28.15% 28.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.13% 28.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 183 24.53% 52.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 68 9.12% 61.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 130 17.43% 79.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 152 20.38% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 2 0.27% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 746 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 970 # Table walker walks requested +system.cpu1.itb.walker.walksShort 970 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 790 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 970 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 970 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 970 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 698 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12663.323782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10953.370627 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6428.547911 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 206 29.51% 29.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.14% 29.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 176 25.21% 54.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 64 9.17% 64.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 123 17.62% 81.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 124 17.77% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.57% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 698 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 562 75.34% 75.34% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 184 24.66% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 746 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 518 74.21% 74.21% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 180 25.79% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 698 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1030 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1030 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 970 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 970 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1776 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18130522 # ITB inst hits -system.cpu1.itb.inst_misses 1030 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 698 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 698 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1668 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 18090241 # ITB inst hits +system.cpu1.itb.inst_misses 970 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 779 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 729 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18131552 # ITB inst accesses -system.cpu1.itb.hits 18130522 # DTB hits -system.cpu1.itb.misses 1030 # DTB misses -system.cpu1.itb.accesses 18131552 # DTB accesses -system.cpu1.numCycles 144010279 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 18091211 # ITB inst accesses +system.cpu1.itb.hits 18090241 # DTB hits +system.cpu1.itb.misses 970 # DTB misses +system.cpu1.itb.accesses 18091211 # DTB accesses +system.cpu1.numCycles 144011692 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 17464166 # Number of instructions committed -system.cpu1.committedOps 20951836 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18623353 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1244 # Number of float alu accesses -system.cpu1.num_func_calls 2002453 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2238605 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18623353 # number of integer instructions -system.cpu1.num_fp_insts 1244 # number of float instructions -system.cpu1.num_int_register_reads 34462753 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13064497 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 984 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76266638 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7592351 # number of times the CC registers were written -system.cpu1.num_mem_refs 6809095 # number of memory refs -system.cpu1.num_load_insts 3920028 # Number of load instructions -system.cpu1.num_store_insts 2889067 # Number of store instructions -system.cpu1.num_idle_cycles 136641410.332873 # Number of idle cycles -system.cpu1.num_busy_cycles 7368868.667127 # Number of busy cycles -system.cpu1.not_idle_fraction 0.051169 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.948831 # Percentage of idle cycles -system.cpu1.Branches 4354761 # Number of branches fetched -system.cpu1.op_class::No_OpClass 27 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14731476 68.33% 68.33% # Class of executed instruction -system.cpu1.op_class::IntMult 16530 0.08% 68.41% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 936 0.00% 68.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.42% # Class of executed instruction -system.cpu1.op_class::MemRead 3920028 18.18% 86.60% # Class of executed instruction -system.cpu1.op_class::MemWrite 2889067 13.40% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21558064 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5764695 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2966106 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 506808 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3301109 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2388086 # Number of BTB hits +system.cpu1.committedInsts 17421387 # Number of instructions committed +system.cpu1.committedOps 20908811 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18586966 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1243 # Number of float alu accesses +system.cpu1.num_func_calls 1994388 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2228706 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18586966 # number of integer instructions +system.cpu1.num_fp_insts 1243 # number of float instructions +system.cpu1.num_int_register_reads 34395717 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13039867 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1047 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 196 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 76120282 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7571334 # number of times the CC registers were written +system.cpu1.num_mem_refs 6808450 # number of memory refs +system.cpu1.num_load_insts 3918979 # Number of load instructions +system.cpu1.num_store_insts 2889471 # Number of store instructions +system.cpu1.num_idle_cycles 136781206.784887 # Number of idle cycles +system.cpu1.num_busy_cycles 7230485.215113 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050208 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949792 # Percentage of idle cycles +system.cpu1.Branches 4335876 # Number of branches fetched +system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14685914 68.27% 68.27% # Class of executed instruction +system.cpu1.op_class::IntMult 16370 0.08% 68.35% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 946 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.35% # Class of executed instruction +system.cpu1.op_class::MemRead 3918979 18.22% 86.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 2889471 13.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 21511704 # Class of executed instruction +system.cpu2.branchPred.lookups 5805237 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2994100 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 512421 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3358874 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2415611 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 72.341931 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1613052 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 330539 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.917285 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1615920 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 333124 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1372,60 +1375,55 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12898 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12898 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8122 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4776 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12898 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12898 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12898 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2175 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12233.103448 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10576.406558 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6350.387588 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::2048-4095 16 0.74% 0.74% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::4096-6143 627 28.83% 29.56% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::6144-8191 3 0.14% 29.70% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::10240-12287 777 35.72% 65.43% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::12288-14335 187 8.60% 74.02% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::14336-16383 174 8.00% 82.02% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::22528-24575 386 17.75% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-26623 5 0.23% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2175 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 12664 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12664 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8020 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4644 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12664 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12664 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12664 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2157 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12096.893834 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10423.094509 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6904.169413 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-16383 1795 83.22% 83.22% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-32767 361 16.74% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2157 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1361 62.57% 62.57% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 814 37.43% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2175 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12898 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1306 60.55% 60.55% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 851 39.45% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2157 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12664 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12898 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2175 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12664 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2157 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2175 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 15073 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2157 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14821 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4607133 # DTB read hits -system.cpu2.dtb.read_misses 11539 # DTB read misses -system.cpu2.dtb.write_hits 3514721 # DTB write hits -system.cpu2.dtb.write_misses 1359 # DTB write misses -system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4677262 # DTB read hits +system.cpu2.dtb.read_misses 11320 # DTB read misses +system.cpu2.dtb.write_hits 3564595 # DTB write hits +system.cpu2.dtb.write_misses 1344 # DTB write misses +system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1512 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1473 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 212 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 332 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 112 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4618672 # DTB read accesses -system.cpu2.dtb.write_accesses 3516080 # DTB write accesses +system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4688582 # DTB read accesses +system.cpu2.dtb.write_accesses 3565939 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 8121854 # DTB hits -system.cpu2.dtb.misses 12898 # DTB misses -system.cpu2.dtb.accesses 8134752 # DTB accesses +system.cpu2.dtb.hits 8241857 # DTB hits +system.cpu2.dtb.misses 12664 # DTB misses +system.cpu2.dtb.accesses 8254521 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1455,81 +1453,81 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1355 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1355 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1103 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1355 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1355 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1355 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 885 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12701.694915 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10970.308006 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6476.484391 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 261 29.49% 29.49% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 244 27.57% 57.06% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 68 7.68% 64.75% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 134 15.14% 79.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 177 20.00% 99.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 885 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 1329 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1329 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 263 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1066 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1329 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1329 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1329 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 852 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12299.295775 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10742.634902 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6145.721581 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 262 30.75% 30.75% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 255 29.93% 60.68% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 38 4.46% 65.14% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 163 19.13% 84.27% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 131 15.38% 99.65% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.35% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 852 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 640 72.32% 72.32% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 245 27.68% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 885 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 589 69.13% 69.13% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 263 30.87% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 852 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1355 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1355 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1329 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1329 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 885 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 885 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2240 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10827992 # ITB inst hits -system.cpu2.itb.inst_misses 1355 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 852 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 852 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10929097 # ITB inst hits +system.cpu2.itb.inst_misses 1329 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 895 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 862 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1816 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1732 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10829347 # ITB inst accesses -system.cpu2.itb.hits 10827992 # DTB hits -system.cpu2.itb.misses 1355 # DTB misses -system.cpu2.itb.accesses 10829347 # DTB accesses -system.cpu2.numCycles 1394813628 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10930426 # ITB inst accesses +system.cpu2.itb.hits 10929097 # DTB hits +system.cpu2.itb.misses 1329 # DTB misses +system.cpu2.itb.accesses 10930426 # DTB accesses +system.cpu2.numCycles 1393382531 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 20299204 # Number of instructions committed -system.cpu2.committedOps 24561296 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1454329 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 560 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4254632682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 68.712725 # CPI: cycles per instruction -system.cpu2.ipc 0.014553 # IPC: instructions per cycle +system.cpu2.committedInsts 20580093 # Number of instructions committed +system.cpu2.committedOps 24901206 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1467300 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 567 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4256226860 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 67.705356 # CPI: cycles per instruction +system.cpu2.ipc 0.014770 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42192180 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1352621448 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13267477 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7218148 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 306932 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 7331192 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6244117 # Number of BTB hits +system.cpu2.tickCycles 42624758 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1350757773 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13301320 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7249235 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 312069 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8284814 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6256612 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 85.171920 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3106613 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16022 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.519040 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3109270 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16225 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1559,89 +1557,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 32594 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 32594 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11131 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7720 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 13743 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 18851 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 550.607395 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 4115.669871 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 18669 99.03% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 132 0.70% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 28 0.15% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 10 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 5 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 33037 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33037 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11464 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7705 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 13868 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19169 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 496.400438 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3535.731274 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 19002 99.13% 99.13% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 134 0.70% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 21 0.11% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-65535 6 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 18851 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6073 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 12561.337066 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10324.019552 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7892.573788 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-16383 4743 78.10% 78.10% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1245 20.50% 98.60% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-49151 80 1.32% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkWaitTime::total 19169 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6102 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 13023.926581 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10629.521640 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 8508.049417 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-16383 4638 76.01% 76.01% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1335 21.88% 97.89% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-49151 115 1.88% 99.77% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.15% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6073 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8078927064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.145347 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.140537 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8125083564 100.57% 100.57% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32811500 -0.41% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7062500 -0.09% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2662500 -0.03% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1263000 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 812000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 353000 -0.00% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 734000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 142000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 166000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 33500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 14500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 66000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 5000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walkCompletionTime::total 6102 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8042044064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.800774 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.238438 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8088297564 100.58% 100.58% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 32871500 -0.41% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7478500 -0.09% 100.07% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2286500 -0.03% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1244500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 730000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 408500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 765000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 196000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 177000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 43000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 11000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 27500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8078927064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1773 69.37% 69.37% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 783 30.63% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2556 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32594 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walksPending::30-31 23500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8042044064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1824 68.91% 68.91% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 823 31.09% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33037 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32594 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2556 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33037 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2556 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 35150 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35684 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7207975 # DTB read hits -system.cpu3.dtb.read_misses 28184 # DTB read misses -system.cpu3.dtb.write_hits 5370312 # DTB write hits -system.cpu3.dtb.write_misses 4410 # DTB write misses +system.cpu3.dtb.read_hits 7253561 # DTB read hits +system.cpu3.dtb.read_misses 28594 # DTB read misses +system.cpu3.dtb.write_hits 5432397 # DTB write hits +system.cpu3.dtb.write_misses 4443 # DTB write misses system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1876 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 480 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 811 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1945 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 458 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 789 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 348 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7236159 # DTB read accesses -system.cpu3.dtb.write_accesses 5374722 # DTB write accesses +system.cpu3.dtb.perms_faults 336 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7282155 # DTB read accesses +system.cpu3.dtb.write_accesses 5436840 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12578287 # DTB hits -system.cpu3.dtb.misses 32594 # DTB misses -system.cpu3.dtb.accesses 12610881 # DTB accesses +system.cpu3.dtb.hits 12685958 # DTB hits +system.cpu3.dtb.misses 33037 # DTB misses +system.cpu3.dtb.accesses 12718995 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1671,67 +1668,69 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4409 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4409 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1513 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2804 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 92 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4317 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1474.635163 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 6438.514221 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 4058 94.00% 94.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.59% 96.59% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 78 1.81% 98.40% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 36 0.83% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.28% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.14% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 4 0.09% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.09% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4317 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1329 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13040.632054 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 10790.250081 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7776.712895 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.81% 1.81% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 30.32% 32.13% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 359 27.01% 59.14% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 209 15.73% 74.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 19 1.43% 76.30% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 282 21.22% 97.52% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 11 0.83% 98.34% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 1 0.08% 98.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 9 0.68% 99.17% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 7 0.53% 99.70% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.23% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1329 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8082078064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 1.066049 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 536728704 -6.64% -6.64% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -8620989268 106.67% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1669000 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 344000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 120000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 49500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8082078064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 894 72.27% 72.27% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 343 27.73% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1237 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4585 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4585 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1570 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2921 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 94 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4491 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1433.533734 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 6108.583355 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 4220 93.97% 93.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 132 2.94% 96.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 81 1.80% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 7 0.16% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 7 0.16% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.04% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::90112-98303 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4491 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1402 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13658.345221 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11345.191727 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7983.067706 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 20 1.43% 1.43% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 28.74% 30.17% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 331 23.61% 53.78% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 266 18.97% 72.75% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 21 1.50% 74.25% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 301 21.47% 95.72% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 32 2.28% 98.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 5 0.36% 98.36% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.57% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.36% 98.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 11 0.78% 99.71% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.14% 99.86% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1402 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8073456064 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.704569 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.455286 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2382514092 29.51% 29.51% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -5692999972 70.52% 100.03% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1707500 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 179000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 115500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 56000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8073456064 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 964 73.70% 73.70% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 344 26.30% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1308 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4409 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4409 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4585 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4585 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1237 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1237 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5646 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9814748 # ITB inst hits -system.cpu3.itb.inst_misses 4409 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1308 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1308 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5893 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9829313 # ITB inst hits +system.cpu3.itb.inst_misses 4585 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits @@ -1740,318 +1739,318 @@ system.cpu3.itb.flush_tlb 161 # Nu system.cpu3.itb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1248 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1305 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 724 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 736 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9819157 # ITB inst accesses -system.cpu3.itb.hits 9814748 # DTB hits -system.cpu3.itb.misses 4409 # DTB misses -system.cpu3.itb.accesses 9819157 # DTB accesses -system.cpu3.numCycles 57366661 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9833898 # ITB inst accesses +system.cpu3.itb.hits 9829313 # DTB hits +system.cpu3.itb.misses 4585 # DTB misses +system.cpu3.itb.accesses 9833898 # DTB accesses +system.cpu3.numCycles 58255672 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20761268 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52178877 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13267477 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9350730 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 33698249 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1591212 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 69410 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 1107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 256 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 135306 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 74302 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 555 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9813722 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 210476 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2135 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 55536037 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.135538 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.278414 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20975785 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52339111 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13301320 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9365882 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 34230578 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1600984 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 75110 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 679 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 249 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 165248 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 76892 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9828258 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 213311 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2192 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 56325440 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.124081 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.271401 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 41384973 74.52% 74.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1837710 3.31% 77.83% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1169547 2.11% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3702482 6.67% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 911101 1.64% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 554699 1.00% 89.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2918405 5.25% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 606250 1.09% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2450870 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 42135738 74.81% 74.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1842427 3.27% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1174880 2.09% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3692209 6.56% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 916764 1.63% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 558692 0.99% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2925255 5.19% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 602319 1.07% 95.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2477156 4.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 55536037 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.231275 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.909568 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14514304 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 31619877 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7786036 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 908366 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 707244 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 976635 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 89470 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 44785495 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 293014 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 707244 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15002070 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3712166 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21623767 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8198323 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6292235 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 42920389 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 988 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 999285 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 100726 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4827959 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44612381 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 197148279 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 47945794 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3725 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37230904 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7381477 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 716136 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 666620 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5136604 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7692057 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 5940620 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1092936 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1536247 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41290259 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 501894 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39299013 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 52056 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 5966024 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13660779 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 53087 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 55536037 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.707631 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.411142 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 56325440 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.228327 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.898438 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14665639 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32213939 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7840695 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 894660 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 710284 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 980840 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 91372 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 45017968 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 299154 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 710284 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15152191 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3825257 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 22150592 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8241060 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6245828 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 43133854 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 881 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 923199 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 93585 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4851932 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44760576 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 198184537 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 48159961 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3993 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 37280661 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7479915 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 724518 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 673070 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5055817 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7747142 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6009339 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1097938 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1536830 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41471519 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 515844 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39457989 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 52603 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6038881 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13851448 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54585 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 56325440 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.700536 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.407802 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 39933168 71.90% 71.90% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5154759 9.28% 81.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3998218 7.20% 88.39% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3241689 5.84% 94.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1260306 2.27% 96.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 769738 1.39% 97.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 826217 1.49% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 240001 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 111941 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 40673603 72.21% 72.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5189038 9.21% 81.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3994905 7.09% 88.52% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3229029 5.73% 94.25% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1266179 2.25% 96.50% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 777932 1.38% 97.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 838695 1.49% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 242964 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 113095 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 55536037 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 56325440 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 56634 9.59% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 279182 47.28% 56.87% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 254722 43.13% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 56406 9.38% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 283401 47.13% 56.51% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 261530 43.49% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 79 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26205156 66.68% 66.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 29936 0.08% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2339 0.01% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7421328 18.88% 85.65% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5640175 14.35% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 83 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26250639 66.53% 66.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 29940 0.08% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2415 0.01% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7470638 18.93% 85.54% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5704269 14.46% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39299013 # Type of FU issued -system.cpu3.iq.rate 0.685050 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 590538 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015027 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 134768668 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 47782568 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 38141743 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 7989 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4328 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3477 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 39885201 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4271 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 170012 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 39457989 # Type of FU issued +system.cpu3.iq.rate 0.677324 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 601337 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015240 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 135886575 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 48050717 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 38292520 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8783 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3829 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 40054524 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4719 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 171660 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1165546 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1325 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29357 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 600603 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1179297 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1335 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29850 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 609995 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 108801 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 44606 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 109451 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43922 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 707244 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3069413 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 520763 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 41839488 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 76423 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7692057 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 5940620 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 259410 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22603 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 492210 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29357 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 139025 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 123161 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 262186 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 38971879 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7290710 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 294612 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 710284 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3184032 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 520990 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 42035728 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 77277 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7747142 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6009339 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 266862 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22482 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 492410 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29850 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 141082 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 125238 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 266320 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 39125976 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7338106 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 299066 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 47335 # number of nop insts executed -system.cpu3.iew.exec_refs 12872001 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7242885 # Number of branches executed -system.cpu3.iew.exec_stores 5581291 # Number of stores executed -system.cpu3.iew.exec_rate 0.679347 # Inst execution rate -system.cpu3.iew.wb_sent 38686705 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 38145220 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 19984457 # num instructions producing a value -system.cpu3.iew.wb_consumers 34832102 # num instructions consuming a value +system.cpu3.iew.exec_nop 48365 # number of nop insts executed +system.cpu3.iew.exec_refs 12982427 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7264644 # Number of branches executed +system.cpu3.iew.exec_stores 5644321 # Number of stores executed +system.cpu3.iew.exec_rate 0.671625 # Inst execution rate +system.cpu3.iew.wb_sent 38838436 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 38296349 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 20014644 # num instructions producing a value +system.cpu3.iew.wb_consumers 34860024 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.664937 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.573737 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.657384 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.574143 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 5981270 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 448807 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 218548 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 54250638 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.660854 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.552983 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 6055415 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 461259 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 221839 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 55029535 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.653724 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.548863 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 40430906 74.53% 74.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6113695 11.27% 85.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3127574 5.77% 91.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1326177 2.44% 94.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 716812 1.32% 95.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 505346 0.93% 96.26% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 950559 1.75% 98.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 229517 0.42% 98.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 850052 1.57% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 41164710 74.80% 74.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6174910 11.22% 86.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3105944 5.64% 91.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1319292 2.40% 94.07% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 711711 1.29% 95.36% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 496248 0.90% 96.26% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 960829 1.75% 98.01% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 230731 0.42% 98.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 865160 1.57% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 54250638 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29358701 # Number of instructions committed -system.cpu3.commit.committedOps 35851741 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 55029535 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29416260 # Number of instructions committed +system.cpu3.commit.committedOps 35974129 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11866528 # Number of memory references committed -system.cpu3.commit.loads 6526511 # Number of loads committed -system.cpu3.commit.membars 173804 # Number of memory barriers committed -system.cpu3.commit.branches 6837387 # Number of branches committed -system.cpu3.commit.fp_insts 3456 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31324780 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1241793 # Number of function calls committed. +system.cpu3.commit.refs 11967189 # Number of memory references committed +system.cpu3.commit.loads 6567845 # Number of loads committed +system.cpu3.commit.membars 179077 # Number of memory barriers committed +system.cpu3.commit.branches 6853829 # Number of branches committed +system.cpu3.commit.fp_insts 3808 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 31432423 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1245286 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23953965 66.81% 66.81% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 28909 0.08% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2339 0.01% 66.90% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.90% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.90% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.90% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6526511 18.20% 85.11% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5340017 14.89% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23975618 66.65% 66.65% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 28907 0.08% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2415 0.01% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6567845 18.26% 84.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5399344 15.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35851741 # Class of committed instruction -system.cpu3.commit.bw_lim_events 850052 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 89574127 # The number of ROB reads -system.cpu3.rob.rob_writes 84953819 # The number of ROB writes -system.cpu3.timesIdled 222816 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1830624 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161214707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29333089 # Number of Instructions Simulated -system.cpu3.committedOps 35826129 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.955698 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.955698 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.511326 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.511326 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42472744 # number of integer regfile reads -system.cpu3.int_regfile_writes 24152717 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14290 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12064 # number of floating regfile writes -system.cpu3.cc_regfile_reads 137731283 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14845540 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75477983 # number of misc regfile reads -system.cpu3.misc_regfile_writes 336291 # number of misc regfile writes +system.cpu3.commit.op_class_0::total 35974129 # Class of committed instruction +system.cpu3.commit.bw_lim_events 865160 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90545687 # The number of ROB reads +system.cpu3.rob.rob_writes 85357421 # The number of ROB writes +system.cpu3.timesIdled 228818 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1930232 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5160394940 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 29390613 # Number of Instructions Simulated +system.cpu3.committedOps 35948482 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.982118 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.982118 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.504511 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.504511 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42625892 # number of integer regfile reads +system.cpu3.int_regfile_writes 24241203 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14445 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12329 # number of floating regfile writes +system.cpu3.cc_regfile_reads 138329125 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14829178 # number of cc regfile writes +system.cpu3.misc_regfile_reads 76422783 # number of misc regfile reads +system.cpu3.misc_regfile_writes 345191 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30181 # Transaction distribution system.iobus.trans_dist::ReadResp 30181 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2106,45 +2105,45 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 22360000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 27670500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 32000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3278000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3858000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 19060000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 22212000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 114500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 78461015 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 78391042 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 48730000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 48071000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005075 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.005312 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 249186259009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005075 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062817 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062817 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 249222416009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005312 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062832 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062832 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2160,14 +2159,14 @@ system.iocache.demand_misses::realview.ide 249 # system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 17563919 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17563919 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1966288096 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1966288096 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 17563919 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17563919 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 17563919 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17563919 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1978574123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1978574123 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 17512919 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 17512919 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 17512919 # number of overall miss cycles +system.iocache.overall_miss_latency::total 17512919 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2184,19 +2183,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 70537.827309 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 70537.827309 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54324.854151 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 54324.854151 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 70537.827309 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 70537.827309 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54664.294046 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 54664.294046 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 70333.008032 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 70333.008032 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.217391 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2210,14 +2209,14 @@ system.iocache.demand_mshr_misses::realview.ide 148 system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 10163919 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10163919 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1206938096 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1206938096 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 10163919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10163919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 10163919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10163919 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1219224123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1219224123 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 10112919 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10112919 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 10112919 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10112919 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses @@ -2226,392 +2225,382 @@ system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68675.128378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68675.128378 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79471.791401 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79471.791401 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68330.533784 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68330.533784 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.774544 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.774544 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68330.533784 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68330.533784 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 103711 # number of replacements -system.l2c.tags.tagsinuse 65095.024716 # Cycle average of tags in use -system.l2c.tags.total_refs 5145934 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168963 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.455981 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 80077044000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48951.707616 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971864 # Average occupied blocks per requestor +system.l2c.tags.replacements 104195 # number of replacements +system.l2c.tags.tagsinuse 65091.017513 # Cycle average of tags in use +system.l2c.tags.total_refs 5155167 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169447 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.423478 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 80140567000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48843.546061 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971843 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4249.334624 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2262.984305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 905.000363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 870.835112 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.993332 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2120.702185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 746.628994 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 47.189745 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 3231.570243 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1686.139222 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.746944 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4254.039308 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2206.437116 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 715.458752 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 853.835982 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.288260 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2257.166509 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 817.070736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 50.645979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3368.546938 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1701.009935 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.745293 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 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ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.138598 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002148 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010225 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.170083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003337 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.204986 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035752 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.138598 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002148 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010225 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.170083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003337 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.204986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035752 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 126673.469388 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70765.984655 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70745.437956 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70789.726027 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70769.622528 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 72150 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72150 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 119075.992096 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117432.381378 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122617.089410 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120488.624032 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120435.265105 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122009.935710 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123076.128679 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122339.474404 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121897.687861 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122035.079051 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127029.798217 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124391.904065 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120435.265105 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119572.722339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122009.935710 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117782.075826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123076.128679 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123011.621809 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121072.495888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120435.265105 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119572.722339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123034.482759 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122009.935710 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117782.075826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128202.898551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123076.128679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123011.621809 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121072.495888 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164599.770642 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185723.773654 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203404.879193 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190138.540414 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167025.925926 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184757.557724 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201583.012155 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189345.813380 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 165687.569192 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185302.882621 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202600.117863 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 189788.805660 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 76298 # Transaction distribution +system.membus.trans_dist::ReadResp 76341 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::Writeback 131166 # Transaction distribution -system.membus.trans_dist::CleanEvict 8718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4555 # Transaction distribution -system.membus.trans_dist::ReadExReq 137947 # Transaction distribution -system.membus.trans_dist::ReadExResp 137947 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36184 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131541 # Transaction distribution +system.membus.trans_dist::CleanEvict 8827 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4560 # Transaction distribution +system.membus.trans_dist::ReadExReq 138388 # Transaction distribution +system.membus.trans_dist::ReadExResp 138388 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36227 # Transaction distribution system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 488332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 595784 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 489795 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 597247 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108913 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 704697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 706160 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17254780 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17417905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17309820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17472945 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19738609 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 305 # Total snoops (count) -system.membus.snoop_fanout::samples 422679 # Request fanout histogram +system.membus.pkt_size::total 19793649 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 304 # Total snoops (count) +system.membus.snoop_fanout::samples 423653 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 422679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 423653 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 422679 # Request fanout histogram -system.membus.reqLayer0.occupancy 54961500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423653 # Request fanout histogram +system.membus.reqLayer0.occupancy 54148500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 673000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 680000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 481696064 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 485362066 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 584907455 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 587517958 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 27319765 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 27144297 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2936,59 +2913,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5650262 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2839838 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 45471 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 619 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 619 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5660019 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2844678 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 45590 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 617 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 617 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 112063 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2626235 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 111923 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2630935 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 760987 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2076983 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2848 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 23 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 761630 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1942576 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 139089 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2870 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296422 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296422 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1976439 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537735 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296497 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296497 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1981401 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537613 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5908570 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617393 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26301 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8653114 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126520888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861689 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 178096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224603385 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 193657 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5938870 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.020066 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.140226 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5923303 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26505 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100543 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8667634 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 251163000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97868601 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 349252557 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 193970 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4194071 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021768 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145924 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5819701 97.99% 97.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 119169 2.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4102776 97.82% 97.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 91295 2.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5938870 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2186534999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4194071 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3475552499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1866037017 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1890152632 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 758288292 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 768668207 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11457495 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11579475 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47843740 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47680705 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index b05a1c47b..d53614d95 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823216 # Number of seconds simulated -sim_ticks 2823215630500 # Number of ticks simulated -final_tick 2823215630500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823500 # Number of seconds simulated +sim_ticks 2823500156000 # Number of ticks simulated +final_tick 2823500156000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103983 # Simulator instruction rate (inst/s) -host_op_rate 126208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2510129357 # Simulator tick rate (ticks/s) -host_mem_usage 634500 # Number of bytes of host memory used -host_seconds 1124.73 # Real time elapsed on the host -sim_insts 116952239 # Number of instructions simulated -sim_ops 141949733 # Number of ops (including micro ops) simulated +host_inst_rate 104004 # Simulator instruction rate (inst/s) +host_op_rate 126232 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2512003120 # Simulator tick rate (ticks/s) +host_mem_usage 633188 # Number of bytes of host memory used +host_seconds 1124.00 # Real time elapsed on the host +sim_insts 116900784 # Number of instructions simulated +sim_ops 141885276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 3840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 675712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5138656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 695680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4658888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 658624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5296736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 714240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4509448 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11177960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 675712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 695680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1371392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8449664 # Number of bytes written to this memory +system.physmem.bytes_read::total 11188968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 658624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 714240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1372864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8441728 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8467188 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 60 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8459252 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 61 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 65 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10870 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 72797 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 83280 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 78 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70462 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175176 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132026 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175348 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131902 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136407 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1360 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136283 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1383 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 239341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1820143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 246414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1650206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 233265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1875947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 252963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1597113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3959301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 239341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 246414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 485755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2992922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3962801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 233265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 252963 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 486228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2989810 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2999129 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2992922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2996016 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2989810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1383 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 239341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1826347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 246414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1650209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 233265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1882150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 252963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1597116 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6958430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175177 # Number of read requests accepted -system.physmem.writeReqs 136407 # Number of write requests accepted -system.physmem.readBursts 175177 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136407 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11201984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8480320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11178024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8467188 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6958817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175349 # Number of read requests accepted +system.physmem.writeReqs 136283 # Number of write requests accepted +system.physmem.readBursts 175349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136283 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11214592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 8471552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11189032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8459252 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40863 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11773 # Per bank write bursts -system.physmem.perBankRdBursts::1 10998 # Per bank write bursts -system.physmem.perBankRdBursts::2 11169 # Per bank write bursts -system.physmem.perBankRdBursts::3 10855 # Per bank write bursts -system.physmem.perBankRdBursts::4 11706 # Per bank write bursts -system.physmem.perBankRdBursts::5 11087 # Per bank write bursts -system.physmem.perBankRdBursts::6 11923 # Per bank write bursts -system.physmem.perBankRdBursts::7 11611 # Per bank write bursts -system.physmem.perBankRdBursts::8 10970 # Per bank write bursts -system.physmem.perBankRdBursts::9 11831 # Per bank write bursts -system.physmem.perBankRdBursts::10 10190 # Per bank write bursts -system.physmem.perBankRdBursts::11 9677 # Per bank write bursts -system.physmem.perBankRdBursts::12 10224 # Per bank write bursts -system.physmem.perBankRdBursts::13 10941 # Per bank write bursts -system.physmem.perBankRdBursts::14 10213 # Per bank write bursts -system.physmem.perBankRdBursts::15 9863 # Per bank write bursts -system.physmem.perBankWrBursts::0 8674 # Per bank write bursts -system.physmem.perBankWrBursts::1 8377 # Per bank write bursts -system.physmem.perBankWrBursts::2 8725 # Per bank write bursts -system.physmem.perBankWrBursts::3 8463 # Per bank write bursts -system.physmem.perBankWrBursts::4 8546 # Per bank write bursts -system.physmem.perBankWrBursts::5 8273 # Per bank write bursts -system.physmem.perBankWrBursts::6 8696 # Per bank write bursts -system.physmem.perBankWrBursts::7 8627 # Per bank write bursts -system.physmem.perBankWrBursts::8 8420 # Per bank write bursts -system.physmem.perBankWrBursts::9 9181 # Per bank write bursts -system.physmem.perBankWrBursts::10 7887 # Per bank write bursts -system.physmem.perBankWrBursts::11 7530 # Per bank write bursts -system.physmem.perBankWrBursts::12 7884 # Per bank write bursts -system.physmem.perBankWrBursts::13 8402 # Per bank write bursts -system.physmem.perBankWrBursts::14 7675 # Per bank write bursts -system.physmem.perBankWrBursts::15 7145 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 49584 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11393 # Per bank write bursts +system.physmem.perBankRdBursts::1 10987 # Per bank write bursts +system.physmem.perBankRdBursts::2 11434 # Per bank write bursts +system.physmem.perBankRdBursts::3 11274 # Per bank write bursts +system.physmem.perBankRdBursts::4 11014 # Per bank write bursts +system.physmem.perBankRdBursts::5 10539 # Per bank write bursts +system.physmem.perBankRdBursts::6 11403 # Per bank write bursts +system.physmem.perBankRdBursts::7 11330 # Per bank write bursts +system.physmem.perBankRdBursts::8 11251 # Per bank write bursts +system.physmem.perBankRdBursts::9 11289 # Per bank write bursts +system.physmem.perBankRdBursts::10 10499 # Per bank write bursts +system.physmem.perBankRdBursts::11 10072 # Per bank write bursts +system.physmem.perBankRdBursts::12 10665 # Per bank write bursts +system.physmem.perBankRdBursts::13 11522 # Per bank write bursts +system.physmem.perBankRdBursts::14 10554 # Per bank write bursts +system.physmem.perBankRdBursts::15 10002 # Per bank write bursts +system.physmem.perBankWrBursts::0 8625 # Per bank write bursts +system.physmem.perBankWrBursts::1 8280 # Per bank write bursts +system.physmem.perBankWrBursts::2 8885 # Per bank write bursts +system.physmem.perBankWrBursts::3 8791 # Per bank write bursts +system.physmem.perBankWrBursts::4 7852 # Per bank write bursts +system.physmem.perBankWrBursts::5 7876 # Per bank write bursts +system.physmem.perBankWrBursts::6 8450 # Per bank write bursts +system.physmem.perBankWrBursts::7 8527 # Per bank write bursts +system.physmem.perBankWrBursts::8 8486 # Per bank write bursts +system.physmem.perBankWrBursts::9 8687 # Per bank write bursts +system.physmem.perBankWrBursts::10 7873 # Per bank write bursts +system.physmem.perBankWrBursts::11 7718 # Per bank write bursts +system.physmem.perBankWrBursts::12 8233 # Per bank write bursts +system.physmem.perBankWrBursts::13 8873 # Per bank write bursts +system.physmem.perBankWrBursts::14 7886 # Per bank write bursts +system.physmem.perBankWrBursts::15 7326 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2823215466500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2823499978000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174621 # Read request sizes (log2) +system.physmem.readPktSize::6 174793 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 132026 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131902 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 107531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1718 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -161,133 +161,132 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 91 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 88 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7756 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::35 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 23 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.586729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.315744 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.746281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25059 38.02% 38.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16073 24.38% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6703 10.17% 72.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3821 5.80% 78.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2972 4.51% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1599 2.43% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1035 1.57% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1073 1.63% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7583 11.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65918 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.191410 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 482.907115 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6680 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6682 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.830141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.245831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.832578 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.873263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.206399 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.323909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24801 37.78% 37.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16133 24.58% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6704 10.21% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3735 5.69% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2850 4.34% 82.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1672 2.55% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1116 1.70% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1095 1.67% 88.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7542 11.49% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65648 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6665 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.286122 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 483.294559 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6663 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6665 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6665 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.860165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.266089 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.031195 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 5 0.07% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 6 0.09% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5722 85.63% 86.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 190 2.84% 89.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 49 0.73% 89.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 177 2.65% 92.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 24 0.36% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 142 2.13% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 60 0.90% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.12% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.28% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 22 0.33% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 156 2.33% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.30% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6682 # Writes before turning the bus around for reads -system.physmem.totQLat 2754544250 # Total ticks spent queuing -system.physmem.totMemAccLat 6036375500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 875155000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15737.47 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::4-7 4 0.06% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 5 0.08% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.15% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5719 85.81% 86.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 154 2.31% 88.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 55 0.83% 89.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 202 3.03% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 36 0.54% 93.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 143 2.15% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 0.68% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.14% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.23% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.35% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.43% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 18 0.27% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.26% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6665 # Writes before turning the bus around for reads +system.physmem.totQLat 2742857501 # Total ticks spent queuing +system.physmem.totMemAccLat 6028382501 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 876140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15653.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34487.47 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34403.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s @@ -296,41 +295,41 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.48 # Average write queue length when enqueuing -system.physmem.readRowHits 143966 # Number of row buffer hits during reads -system.physmem.writeRowHits 97651 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.69 # Row buffer hit rate for writes -system.physmem.avgGap 9060848.65 # Average gap between requests -system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 261734760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 142811625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 710751600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 443108880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184398261840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80170181370 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1623600588000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1889727438075 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.354462 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2700891551000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94273140000 # Time in different power states +system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.09 # Average write queue length when enqueuing +system.physmem.readRowHits 144250 # Number of row buffer hits during reads +system.physmem.writeRowHits 97697 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes +system.physmem.avgGap 9060366.00 # Average gap between requests +system.physmem.pageHitRate 78.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 255936240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139647750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697117200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 436013280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80003561535 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1623919600500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1889868955065 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.336286 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2701419954000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94282760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28044170250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27794238500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236605320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129100125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654482400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 415523520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184398261840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79085731860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1624551859500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1889471564565 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.263829 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2702486818500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94273140000 # Time in different power states +system.physmem_1.actEnergy 240362640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131150250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 669653400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421731360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79168489875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1624652119500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1889700585585 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.276655 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2702647601500 # Time in different power states +system.physmem_1.memoryStateTime::REF 94282760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26455661500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26569784000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory @@ -350,15 +349,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26494710 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13632658 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 507079 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 16292260 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12421928 # Number of BTB hits +system.cpu0.branchPred.lookups 26581187 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13736110 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 501433 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16012084 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12431439 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 76.244352 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6636932 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 27006 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.637858 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6636300 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 27516 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -389,92 +388,88 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 55575 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 55575 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17227 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13739 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24609 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 30966 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 596.880450 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3694.116884 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 30106 97.22% 97.22% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 526 1.70% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 216 0.70% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 59 0.19% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.06% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 8 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::73728-81919 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::90112-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 30966 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 13159 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13974.808116 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11468.359848 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 9225.442290 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 9399 71.43% 71.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3482 26.46% 97.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 252 1.92% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 15 0.11% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 56625 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 56625 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17270 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13837 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25518 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 31107 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 865.432218 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 5323.916597 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 30633 98.48% 98.48% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 331 1.06% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 76 0.24% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 30 0.10% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 18 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 31107 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12481 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13577.197340 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10994.614021 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9335.319316 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9132 73.17% 73.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3098 24.82% 97.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 222 1.78% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-81919 4 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 14 0.11% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 13159 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 78337685356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.743824 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.461899 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 78259560856 99.90% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 54393500 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 11721500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4062000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2302000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1574000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 883500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 2122500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 542000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 148500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 83000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 91000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 86000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 78500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 78337685356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3804 69.37% 69.37% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1680 30.63% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5484 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 55575 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 12481 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 91900460244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.603534 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.511861 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 91817471744 99.91% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 56263000 0.06% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12793000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5164500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2519500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1396500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1020000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 2514500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 435000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 355500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 97000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 171000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 161000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 91900460244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3454 69.05% 69.05% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1548 30.95% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5002 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56625 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 55575 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56625 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5002 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5484 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 61059 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5002 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 61627 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13854800 # DTB read hits -system.cpu0.dtb.read_misses 47874 # DTB read misses -system.cpu0.dtb.write_hits 10355704 # DTB write hits -system.cpu0.dtb.write_misses 7701 # DTB write misses -system.cpu0.dtb.flush_tlb 184 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 458 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 13967095 # DTB read hits +system.cpu0.dtb.read_misses 47255 # DTB read misses +system.cpu0.dtb.write_hits 10501947 # DTB write hits +system.cpu0.dtb.write_misses 9370 # DTB write misses +system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3595 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 904 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1404 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3287 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 776 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1257 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 604 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13902674 # DTB read accesses -system.cpu0.dtb.write_accesses 10363405 # DTB write accesses +system.cpu0.dtb.perms_faults 595 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14014350 # DTB read accesses +system.cpu0.dtb.write_accesses 10511317 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24210504 # DTB hits -system.cpu0.dtb.misses 55575 # DTB misses -system.cpu0.dtb.accesses 24266079 # DTB accesses +system.cpu0.dtb.hits 24469042 # DTB hits +system.cpu0.dtb.misses 56625 # DTB misses +system.cpu0.dtb.accesses 24525667 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,802 +499,805 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 7385 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7385 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2112 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5086 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 187 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 7198 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1405.946096 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 5932.758848 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6773 94.10% 94.10% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 190 2.64% 96.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 140 1.94% 98.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 47 0.65% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 11 0.15% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 16 0.22% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 7 0.10% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 4 0.06% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 7198 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 14423.425123 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12051.974959 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 8640.644527 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 1863 70.28% 70.28% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 733 27.65% 97.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 46 1.74% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 4 0.15% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-81919 4 0.15% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 7362 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7362 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2261 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4952 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 149 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 7213 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1612.505199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6472.144246 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6729 93.29% 93.29% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 210 2.91% 96.20% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 172 2.38% 98.59% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 48 0.67% 99.25% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 20 0.28% 99.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 11 0.15% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 8 0.11% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 4 0.06% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::90112-98303 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::106496-114687 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 7213 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2374 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13966.512216 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11737.528521 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 8158.100835 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1734 73.04% 73.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 597 25.15% 98.19% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 40 1.68% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 35368734396 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.609046 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.488267 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 13831462500 39.11% 39.11% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 21534286896 60.89% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2356000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 358500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 226000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 35368734396 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1897 76.99% 76.99% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 567 23.01% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2464 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2374 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 23180714008 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.929856 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.256422 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1630643500 7.03% 7.03% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 21546495508 92.95% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2812000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 517500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 174500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 71000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 23180714008 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1663 74.74% 74.74% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 562 25.26% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2225 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7385 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7385 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7362 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7362 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2464 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2464 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 9849 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20114587 # ITB inst hits -system.cpu0.itb.inst_misses 7385 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2225 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2225 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 9587 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20128372 # ITB inst hits +system.cpu0.itb.inst_misses 7362 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 184 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 458 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2409 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2149 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1237 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20121972 # ITB inst accesses -system.cpu0.itb.hits 20114587 # DTB hits -system.cpu0.itb.misses 7385 # DTB misses -system.cpu0.itb.accesses 20121972 # DTB accesses -system.cpu0.numCycles 110325192 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20135734 # ITB inst accesses +system.cpu0.itb.hits 20128372 # DTB hits +system.cpu0.itb.misses 7362 # DTB misses +system.cpu0.itb.accesses 20135734 # DTB accesses +system.cpu0.numCycles 111789846 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39212585 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 103212139 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26494710 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19058860 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 65985336 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3113233 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 120421 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 6405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 451 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 171105 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 126190 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 599 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20113194 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 349758 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3372 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 107179671 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.158056 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.272689 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39393717 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103942274 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26581187 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19067739 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 67197572 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3104883 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 120313 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4808 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 429 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 187538 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 119721 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 669 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20127335 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 349524 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3480 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 108577171 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.150570 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.270138 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 78729483 73.46% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3807123 3.55% 77.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2383498 2.22% 79.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8002443 7.47% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1574194 1.47% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1068807 1.00% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 5993116 5.59% 94.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1028903 0.96% 95.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4592104 4.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80014629 73.69% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3810733 3.51% 77.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2393612 2.20% 79.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7999548 7.37% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1536045 1.41% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1088578 1.00% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6047569 5.57% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1035127 0.95% 95.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4651330 4.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 107179671 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.240151 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.935526 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26754853 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 62165032 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15379945 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1465673 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1413940 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1877729 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 144724 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 85569568 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 471665 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1413940 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27587165 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6832428 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44962784 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16009333 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10373762 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 81846595 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 4353 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1036687 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 217532 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8369836 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 84011397 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 377628674 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 91338127 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6488 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 71240050 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12771347 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1555221 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1457428 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8538957 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14623040 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11507305 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1985956 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2777400 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 78787811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1106001 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 75754836 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10581035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23286965 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 104667 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 107179671 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.706802 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.408587 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 108577171 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.237778 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.929801 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26873328 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 63362554 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15407826 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1524257 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1408897 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1872466 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 145547 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86353471 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 470061 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1408897 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27727925 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6705409 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 45853663 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16073761 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10807193 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82639232 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2272 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1128991 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 256935 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8662593 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84875469 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 381763695 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 92641306 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5587 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72346979 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12528482 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1562352 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1465023 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8851459 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14739399 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11667463 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 2112364 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2804310 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79594677 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1116242 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 76600031 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88073 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10385869 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23123923 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 102217 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 108577171 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.705489 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.406693 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 76952421 71.80% 71.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10093269 9.42% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7647177 7.13% 88.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6479607 6.05% 94.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2319282 2.16% 96.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1495618 1.40% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1437164 1.34% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 490874 0.46% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 264259 0.25% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 77873399 71.72% 71.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10449451 9.62% 81.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7708887 7.10% 88.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6446636 5.94% 94.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2344597 2.16% 96.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1520287 1.40% 97.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1484500 1.37% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 489237 0.45% 99.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 260177 0.24% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 107179671 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 108577171 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 115831 10.14% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.14% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 518494 45.41% 55.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 507518 44.45% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112335 9.77% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 528670 45.98% 55.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 508787 44.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 661 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50460858 66.61% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56393 0.07% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4124 0.01% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14247837 18.81% 85.50% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10984955 14.50% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 225 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51038212 66.63% 66.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57114 0.07% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4060 0.01% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14356873 18.74% 85.45% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 11143544 14.55% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 75754836 # Type of FU issued -system.cpu0.iq.rate 0.686650 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1141845 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.015073 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 259903837 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 90518348 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 73472782 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14532 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7678 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6317 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 76888224 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7796 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 347025 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 76600031 # Type of FU issued +system.cpu0.iq.rate 0.685215 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1149793 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.015010 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 263002604 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91143035 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74349830 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12495 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6612 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5504 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 77742883 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6716 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 356237 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2039138 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2398 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52342 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1081901 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1997626 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2287 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54048 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1072719 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 214750 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 120180 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 202075 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 121659 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1413940 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5391499 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1208860 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80024251 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 117807 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14623040 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11507305 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 566411 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44037 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1152589 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52342 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 226715 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 204902 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 431617 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75186689 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14022863 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 512703 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1408897 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5279939 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1209588 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80840958 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 118727 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14739399 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11667463 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 570481 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 45640 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1151814 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54048 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 221570 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 202811 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 424381 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76042804 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14136234 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 500738 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 130439 # number of nop insts executed -system.cpu0.iew.exec_refs 24907066 # number of memory reference insts executed -system.cpu0.iew.exec_branches 13969302 # Number of branches executed -system.cpu0.iew.exec_stores 10884203 # Number of stores executed -system.cpu0.iew.exec_rate 0.681501 # Inst execution rate -system.cpu0.iew.wb_sent 74615293 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 73479099 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38405173 # num instructions producing a value -system.cpu0.iew.wb_consumers 66942375 # num instructions consuming a value +system.cpu0.iew.exec_nop 130039 # number of nop insts executed +system.cpu0.iew.exec_refs 25177582 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14081958 # Number of branches executed +system.cpu0.iew.exec_stores 11041348 # Number of stores executed +system.cpu0.iew.exec_rate 0.680230 # Inst execution rate +system.cpu0.iew.wb_sent 75486871 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74355334 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38977390 # num instructions producing a value +system.cpu0.iew.wb_consumers 68370260 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.666023 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.573705 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.665135 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.570093 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10599640 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1001334 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 364365 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 104754954 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.662419 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.562446 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10422774 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1014025 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 357851 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 106178823 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.663049 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560671 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 77896212 74.36% 74.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12060503 11.51% 85.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6064743 5.79% 91.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2632493 2.51% 94.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1283946 1.23% 95.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 809122 0.77% 96.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1758606 1.68% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 423456 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1825873 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 78820889 74.23% 74.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12387005 11.67% 85.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6099262 5.74% 91.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2661518 2.51% 94.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1365099 1.29% 95.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 835592 0.79% 96.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1729906 1.63% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 422537 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1857015 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 104754954 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57128680 # Number of instructions committed -system.cpu0.commit.committedOps 69391674 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 106178823 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 58051307 # Number of instructions committed +system.cpu0.commit.committedOps 70401754 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23009306 # Number of memory references committed -system.cpu0.commit.loads 12583902 # Number of loads committed -system.cpu0.commit.membars 411216 # Number of memory barriers committed -system.cpu0.commit.branches 13247589 # Number of branches committed -system.cpu0.commit.fp_insts 6270 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 60931939 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2625183 # Number of function calls committed. +system.cpu0.commit.refs 23336517 # Number of memory references committed +system.cpu0.commit.loads 12741773 # Number of loads committed +system.cpu0.commit.membars 415885 # Number of memory barriers committed +system.cpu0.commit.branches 13388774 # Number of branches committed +system.cpu0.commit.fp_insts 5482 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61799925 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2627242 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46323475 66.76% 66.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54770 0.08% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4123 0.01% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12583902 18.13% 84.98% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10425404 15.02% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 47005628 66.77% 66.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55549 0.08% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4060 0.01% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12741773 18.10% 84.95% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10594744 15.05% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 69391674 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1825873 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 170570043 # The number of ROB reads -system.cpu0.rob.rob_writes 162411378 # The number of ROB writes -system.cpu0.timesIdled 376879 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3145521 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3401736013 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57049783 # Number of Instructions Simulated -system.cpu0.committedOps 69312777 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.933841 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.933841 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.517106 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.517106 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 81821198 # number of integer regfile reads -system.cpu0.int_regfile_writes 46866866 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17105 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13418 # number of floating regfile writes -system.cpu0.cc_regfile_reads 265587152 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27327021 # number of cc regfile writes -system.cpu0.misc_regfile_reads 147986326 # number of misc regfile reads -system.cpu0.misc_regfile_writes 766351 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 853611 # number of replacements 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# number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 219266 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446082 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 233369 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225947 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459316 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19991940 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21105795 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41097735 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20172402 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21289582 # number of overall hits -system.cpu0.dcache.overall_hits::total 41461984 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 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average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 115.912576 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189272310 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189272310 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12310382 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12874546 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25184928 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7941393 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 7958196 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15899589 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 183968 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180294 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 364262 # number of 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miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 14266388354 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29619595783 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2817683000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3126439500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5944122500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2431141924 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2360887452 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4792029376 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5248824924 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5487326952 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10736151876 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016568 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016156 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016356 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015513 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015031 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015268 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.249738 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.193578 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224012 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.020303 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018860 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019593 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000094 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000164 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000128 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016111 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015677 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015889 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019183 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017572 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018360 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.134584 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15352.821210 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15729.332202 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 72640.013933 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 68115.819328 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70382.194493 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14648.484032 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15885.591477 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15138.194637 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19716.932842 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13401.726880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16723.586430 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 28204.545455 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 31527.027027 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30288.135593 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 39701.845171 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36908.899169 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38293.293987 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35413.425756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34441.074085 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34938.327211 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189334.968418 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192431.802794 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190951.283369 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160694.158504 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189492.531664 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173699.774395 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174896.702009 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191156.098098 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182845.715483 # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3330300500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3396411500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6726712000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11231056881 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9824685455 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21055742336 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1111837000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 752623000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1864460000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96489000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61648000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 158137000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 910000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1457500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2367500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14561357381 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13221096955 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27782454336 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15673194381 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 13973719955 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29646914336 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2960669500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3341308500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301978000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2589197924 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2495038452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084236376 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5549867424 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5836346952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11386214376 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016390 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016417 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016404 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015455 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015120 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015288 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.245887 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.196848 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223791 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019573 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019837 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019701 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000170 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000155 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015983 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015867 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015925 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019013 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017787 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018394 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15941.011612 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.011706 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15756.154462 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73997.581179 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66464.743502 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70280.921300 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15005.560429 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15471.426222 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15190.197245 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 20236.786913 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13492.667980 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16936.596337 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27575.757576 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 38355.263158 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33345.070423 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40370.837509 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36140.002064 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38240.453581 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36048.148811 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33714.183584 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34909.073107 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200805.039338 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203924.839792 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.171448 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170207.594268 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201602.977699 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184291.589677 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185267.306182 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202925.731094 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193916.827767 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1936695 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.472430 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38860636 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1937207 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.060136 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11042568500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 296.854540 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 214.617890 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.579794 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.419176 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998970 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1936787 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.471074 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38830098 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1937299 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.043420 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 11154875500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 205.082456 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 306.388618 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.400552 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.598415 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998967 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42883011 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42883011 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19112796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19747840 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38860636 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19112796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19747840 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38860636 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19112796 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19747840 # number of overall hits -system.cpu0.icache.overall_hits::total 38860636 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 999725 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1085355 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2085080 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 999725 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1085355 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2085080 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 999725 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1085355 # number of overall misses -system.cpu0.icache.overall_misses::total 2085080 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14134312480 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 15390349487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29524661967 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14134312480 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 15390349487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29524661967 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14134312480 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 15390349487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29524661967 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20112521 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20833195 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40945716 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20112521 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20833195 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40945716 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20112521 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20833195 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40945716 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049707 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.052097 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050923 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049707 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.052097 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050923 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049707 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.052097 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050923 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14138.200485 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14180.014361 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14159.966029 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14138.200485 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14180.014361 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14159.966029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14138.200485 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14180.014361 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14159.966029 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 20835 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42853283 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42853283 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19119269 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19710829 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38830098 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19119269 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19710829 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38830098 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19119269 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19710829 # number of overall hits +system.cpu0.icache.overall_hits::total 38830098 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1007396 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1078417 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2085813 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1007396 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1078417 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2085813 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1007396 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1078417 # number of overall misses +system.cpu0.icache.overall_misses::total 2085813 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14294314981 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 15434234486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 29728549467 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14294314981 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 15434234486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 29728549467 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14294314981 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 15434234486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29728549467 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20126665 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20789246 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40915911 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20126665 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20789246 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40915911 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20126665 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20789246 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40915911 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050053 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.051874 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050978 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050053 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.051874 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050978 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050053 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.051874 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050978 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14189.370398 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14311.935444 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14252.739563 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14189.370398 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14311.935444 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14252.739563 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14189.370398 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14311.935444 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14252.739563 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 19244 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 782 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 808 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.643223 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.816832 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 70586 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 77198 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147784 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 70586 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 77198 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147784 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 70586 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 77198 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147784 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 929139 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1008157 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1937296 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 929139 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 1008157 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1937296 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 929139 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 1008157 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1937296 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1936787 # number of writebacks +system.cpu0.icache.writebacks::total 1936787 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71558 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76882 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 148440 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 71558 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 76882 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 148440 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 71558 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 76882 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 148440 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 935838 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1001535 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1937373 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 935838 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1001535 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1937373 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 935838 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1001535 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1937373 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 668 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 668 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 668 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 668 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12404793984 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13457356489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 25862150473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12404793984 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13457356489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 25862150473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12404793984 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13457356489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 25862150473 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86442500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86442500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86442500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 86442500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047314 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047314 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046197 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048392 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047314 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13349.612281 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13349.612281 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13350.848456 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13348.472995 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13349.612281 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129404.940120 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129404.940120 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129404.940120 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12537948486 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13509677989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 26047626475 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12537948486 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13509677989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 26047626475 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12537948486 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13509677989 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 26047626475 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86506500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86506500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86506500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 86506500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046497 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048176 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047350 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046497 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048176 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047350 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046497 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048176 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047350 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13397.562918 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13488.972416 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.817531 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13397.562918 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13488.972416 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.817531 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13397.562918 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13488.972416 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.817531 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27956882 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14656819 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 538960 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17404345 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 13151851 # Number of BTB hits +system.cpu1.branchPred.lookups 27828831 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14541667 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 548498 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17325081 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13118302 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.566481 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6863409 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29253 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.718561 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6848129 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29493 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1329,82 +1327,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 58688 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58688 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18912 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13793 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25983 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32705 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 608.026296 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3710.555117 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 32390 99.04% 99.04% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 251 0.77% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 38 0.12% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 12 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32705 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12474 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12069.344236 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9799.859677 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7714.985856 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4605 36.92% 36.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5236 41.98% 78.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2264 18.15% 97.04% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 177 1.42% 98.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 81 0.65% 99.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 107 0.86% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12474 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 91615628244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.688499 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.485401 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 91592721244 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 15376000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 3652500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 2610000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 561000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 145500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 138500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 418000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 91615628244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3400 68.01% 68.01% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1599 31.99% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 4999 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58688 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 57586 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 57586 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19035 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13643 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 24908 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 32678 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 702.995899 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 4885.704946 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32257 98.71% 98.71% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 309 0.95% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 56 0.17% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 25 0.08% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 12 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 32678 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 13208 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 14797.811932 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12463.368567 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8508.122633 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 12903 97.69% 97.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 300 2.27% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 13208 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 91471142744 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.733221 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.463957 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 91384673244 99.91% 99.91% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 60550000 0.07% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 13658500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 4816000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2368000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1256000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 753000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 2182000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 292000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 158000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 50500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 28500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 277000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 61500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 91471142744 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3746 68.55% 68.55% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1719 31.45% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5465 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 57586 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58688 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4999 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 57586 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5465 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4999 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 63687 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5465 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63051 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14526505 # DTB read hits -system.cpu1.dtb.read_misses 49054 # DTB read misses -system.cpu1.dtb.write_hits 10631798 # DTB write hits -system.cpu1.dtb.write_misses 9634 # DTB write misses -system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 459 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14412138 # DTB read hits +system.cpu1.dtb.read_misses 49815 # DTB read misses +system.cpu1.dtb.write_hits 10474078 # DTB write hits +system.cpu1.dtb.write_misses 7771 # DTB write misses +system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3274 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1336 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3611 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 776 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1282 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14575559 # DTB read accesses -system.cpu1.dtb.write_accesses 10641432 # DTB write accesses +system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14461953 # DTB read accesses +system.cpu1.dtb.write_accesses 10481849 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25158303 # DTB hits -system.cpu1.dtb.misses 58688 # DTB misses -system.cpu1.dtb.accesses 25216991 # DTB accesses +system.cpu1.dtb.hits 24886216 # DTB hits +system.cpu1.dtb.misses 57586 # DTB misses +system.cpu1.dtb.accesses 24943802 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1434,382 +1436,386 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7824 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7824 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2815 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4844 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 165 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1312.247030 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 5391.308444 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7206 94.09% 94.09% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 209 2.73% 96.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 155 2.02% 98.84% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 49 0.64% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 13 0.17% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 13 0.17% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 4 0.05% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2378 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12869.007569 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10590.567886 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8075.239006 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 829 34.86% 34.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 979 41.17% 76.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 513 21.57% 97.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 16 0.67% 98.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 11 0.46% 98.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 27 1.14% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2378 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 31482348100 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.924096 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.265389 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2393427520 7.60% 7.60% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 29085771080 92.39% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2580000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 481500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 88000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 31482348100 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1649 74.51% 74.51% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 564 25.49% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2213 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7940 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7940 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2768 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4984 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 188 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7752 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1436.661507 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6120.056353 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7301 94.18% 94.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 193 2.49% 96.67% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 153 1.97% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 37 0.48% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 27 0.35% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 16 0.21% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 11 0.14% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 4 0.05% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 5 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::90112-98303 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7752 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 14933.282501 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12692.719494 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8120.359954 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 585 22.30% 22.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1248 47.58% 69.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 629 23.98% 93.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 104 3.96% 97.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 23 0.88% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 26 0.99% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.15% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.11% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2623 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 31327211100 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.898331 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.302824 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 3189472000 10.18% 10.18% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 28134324100 89.81% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2583000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 637000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 160000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 31327211100 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1850 75.98% 75.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 585 24.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2435 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7940 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7940 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2213 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2213 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10037 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20834938 # ITB inst hits -system.cpu1.itb.inst_misses 7824 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2435 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2435 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10375 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20791300 # ITB inst hits +system.cpu1.itb.inst_misses 7940 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 459 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2128 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2403 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1257 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20842762 # ITB inst accesses -system.cpu1.itb.hits 20834938 # DTB hits -system.cpu1.itb.misses 7824 # DTB misses -system.cpu1.itb.accesses 20842762 # DTB accesses -system.cpu1.numCycles 114249199 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20799240 # ITB inst accesses +system.cpu1.itb.hits 20791300 # DTB hits +system.cpu1.itb.misses 7940 # DTB misses +system.cpu1.itb.accesses 20799240 # DTB accesses +system.cpu1.numCycles 114309908 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 41440028 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108062066 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27956882 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 20015260 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 67364504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3251122 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 125092 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 348 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 238931 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 130362 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20833198 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 375306 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3528 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 110929848 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.171009 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.281658 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 41263279 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 107226594 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27828831 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19966431 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 67413560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3261213 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 132884 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 6791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 371 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 251452 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 126014 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 455 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20789251 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 378310 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3605 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 110825375 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.163723 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.274017 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 81198239 73.20% 73.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3985157 3.59% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2477511 2.23% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8258795 7.45% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1633809 1.47% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1136557 1.02% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6389922 5.76% 94.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1173130 1.06% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4676728 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81246984 73.31% 73.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3970774 3.58% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2468449 2.23% 79.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8233318 7.43% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1681631 1.52% 88.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1117562 1.01% 89.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6321498 5.70% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1162226 1.05% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4622933 4.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 110929848 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244701 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.945845 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 28438107 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 63381229 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15870082 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1769017 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1471120 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1958077 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 156563 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89815738 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 503200 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1471120 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 29385148 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6578856 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46582606 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16681881 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10229932 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85972606 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3235 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1759145 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 332326 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 7382577 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89179456 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 395930491 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95980229 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5368 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 75492279 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13687169 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1580321 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1483697 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10084798 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15398688 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11726928 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2180756 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2876636 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82789954 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1104868 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79357586 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91701 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 11257862 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24898946 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 112169 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 110929848 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.715385 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.405643 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 110825375 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.243451 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.938034 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 28317279 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 63485741 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15848519 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1697419 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1476110 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1966949 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 156570 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 88997857 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 507653 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1476110 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 29247785 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 7012026 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46712417 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16603449 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 9773269 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85151296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3883 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1655595 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 301575 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 7069337 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88292342 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 391615779 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 94636441 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6205 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74317970 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13974372 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1570590 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1473246 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9761371 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15285949 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11554817 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2153118 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2760852 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 81958519 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1096065 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78473689 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91016 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 11494354 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25135429 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 116024 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 110825375 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.708084 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.398689 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 79077492 71.29% 71.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10621201 9.57% 80.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8213587 7.40% 88.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6738763 6.07% 94.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2479052 2.23% 96.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1519430 1.37% 97.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1589812 1.43% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 483396 0.44% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 207115 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 79269169 71.53% 71.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10544902 9.51% 81.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8143493 7.35% 88.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6684211 6.03% 94.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2457263 2.22% 96.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1495236 1.35% 97.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1542850 1.39% 99.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 479172 0.43% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 209079 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 110929848 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 110825375 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 95512 8.42% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 536739 47.33% 55.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 501765 44.25% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 101177 9.01% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 523345 46.61% 55.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 498385 44.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 1676 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53175622 67.01% 67.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 60064 0.08% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4456 0.01% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14922442 18.80% 85.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11193322 14.10% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2112 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52572793 66.99% 67.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59372 0.08% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4520 0.01% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14812673 18.88% 85.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11022213 14.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79357586 # Type of FU issued -system.cpu1.iq.rate 0.694601 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1134021 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014290 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 270859048 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95198962 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77052102 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11694 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6328 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5212 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 80483666 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6265 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368068 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78473689 # Type of FU issued +system.cpu1.iq.rate 0.686499 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1122913 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014309 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 268972635 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94593002 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76135780 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14047 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7316 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6000 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79586882 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7608 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 356462 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2171413 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2447 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 53780 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1110791 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2228793 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2378 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 52565 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1113544 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 197752 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 83861 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 209799 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 80325 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1471120 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5242635 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1056196 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84025940 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 131684 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15398688 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11726928 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 568087 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44365 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 998937 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 53780 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 246243 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 216797 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 463040 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78768106 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14688147 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 530926 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1476110 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5644573 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1066657 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83187752 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132087 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15285949 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11554817 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 564046 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44633 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1008979 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 52565 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 252953 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 220957 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 473910 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 77870409 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14572543 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 545823 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 131118 # number of nop insts executed -system.cpu1.iew.exec_refs 25774139 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14898432 # Number of branches executed -system.cpu1.iew.exec_stores 11085992 # Number of stores executed -system.cpu1.iew.exec_rate 0.689441 # Inst execution rate -system.cpu1.iew.wb_sent 78239059 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77057314 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40452895 # num instructions producing a value -system.cpu1.iew.wb_consumers 70755105 # num instructions consuming a value +system.cpu1.iew.exec_nop 133168 # number of nop insts executed +system.cpu1.iew.exec_refs 25490059 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14772585 # Number of branches executed +system.cpu1.iew.exec_stores 10917516 # Number of stores executed +system.cpu1.iew.exec_rate 0.681222 # Inst execution rate +system.cpu1.iew.wb_sent 77325591 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76141780 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39859971 # num instructions producing a value +system.cpu1.iew.wb_consumers 69277952 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.674467 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.571731 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.666100 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575363 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11247994 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 992699 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 384482 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 108382892 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.670890 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.556432 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11469730 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 980041 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 393964 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 108246213 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.661810 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.544617 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80053687 73.86% 73.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12617943 11.64% 85.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6573081 6.06% 91.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2685794 2.48% 94.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1383289 1.28% 95.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 946585 0.87% 96.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1968943 1.82% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 416822 0.38% 98.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1736748 1.60% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80231551 74.12% 74.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12503324 11.55% 85.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6520168 6.02% 91.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2652912 2.45% 94.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1399925 1.29% 95.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 915869 0.85% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1908410 1.76% 98.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 405906 0.37% 98.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1708148 1.58% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 108382892 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59978464 # Number of instructions committed -system.cpu1.commit.committedOps 72712964 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 108246213 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59004382 # Number of instructions committed +system.cpu1.commit.committedOps 71638427 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23843412 # Number of memory references committed -system.cpu1.commit.loads 13227275 # Number of loads committed -system.cpu1.commit.membars 402801 # Number of memory barriers committed -system.cpu1.commit.branches 14144728 # Number of branches committed -system.cpu1.commit.fp_insts 5158 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63547368 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2716364 # Number of function calls committed. +system.cpu1.commit.refs 23498429 # Number of memory references committed +system.cpu1.commit.loads 13057156 # Number of loads committed +system.cpu1.commit.membars 398159 # Number of memory barriers committed +system.cpu1.commit.branches 13983983 # Number of branches committed +system.cpu1.commit.fp_insts 5946 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 62620951 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2707521 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48806787 67.12% 67.12% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 58309 0.08% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.20% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4456 0.01% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13227275 18.19% 85.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10616137 14.60% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48077932 67.11% 67.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57547 0.08% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.19% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4519 0.01% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13057156 18.23% 85.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10441273 14.57% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 72712964 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1736748 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 177811075 # The number of ROB reads -system.cpu1.rob.rob_writes 170472987 # The number of ROB writes -system.cpu1.timesIdled 411472 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3319351 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2020087270 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59902456 # Number of Instructions Simulated -system.cpu1.committedOps 72636956 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.907254 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.907254 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.524314 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.524314 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 85743042 # number of integer regfile reads -system.cpu1.int_regfile_writes 48986759 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16090 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13161 # number of floating regfile writes -system.cpu1.cc_regfile_reads 278464634 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29701060 # number of cc regfile writes -system.cpu1.misc_regfile_reads 152671939 # number of misc regfile reads -system.cpu1.misc_regfile_writes 753578 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.cpu1.commit.op_class_0::total 71638427 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1708148 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 176890222 # The number of ROB reads +system.cpu1.rob.rob_writes 168799668 # The number of ROB writes +system.cpu1.timesIdled 412724 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 3484533 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3325413921 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 58926185 # Number of Instructions Simulated +system.cpu1.committedOps 71560230 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.939883 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.939883 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.515495 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.515495 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84497448 # number of integer regfile reads +system.cpu1.int_regfile_writes 48483083 # number of integer regfile writes +system.cpu1.fp_regfile_reads 17003 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13376 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275324862 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29228214 # number of cc regfile writes +system.cpu1.misc_regfile_reads 152523655 # number of misc regfile reads +system.cpu1.misc_regfile_writes 741987 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30172 # Transaction distribution +system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1834,9 +1840,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -1859,95 +1865,95 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 49500500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 613500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6444000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 38204000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 128000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186358814 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186303033 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.069707 # Cycle average of tags in use +system.iocache.tags.replacements 36413 # number of replacements +system.iocache.tags.tagsinuse 1.069629 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 236268040000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.069707 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.066857 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.066857 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 236545551000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.069629 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.066852 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.066852 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses +system.iocache.tags.tag_accesses 328023 # Number of tag accesses +system.iocache.tags.data_accesses 328023 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses +system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses -system.iocache.demand_misses::total 233 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 233 # number of overall misses -system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28976877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28976877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697901937 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697901937 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28976877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28976877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28976877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28976877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses +system.iocache.demand_misses::total 223 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 223 # number of overall misses +system.iocache.overall_misses::total 223 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28112876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28112876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4718729157 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4718729157 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28112876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28112876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28112876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28112876 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1956,40 +1962,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124364.278970 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124364.278970 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129690.314074 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129690.314074 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124364.278970 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124364.278970 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124364.278970 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124364.278970 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 126066.708520 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126066.708520 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130265.270456 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130265.270456 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126066.708520 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126066.708520 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126066.708520 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126066.708520 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 790 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 84 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.404762 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks 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ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1998,270 +2004,274 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74364.278970 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74364.278970 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79690.314074 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79690.314074 # average WriteLineReq mshr miss latency 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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 125700 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70801.959412 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70787.077982 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70794.847643 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71142.857143 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70857.142857 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70952.380952 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123570.232343 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123537.033309 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 123554.931055 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123843.000934 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122785.887007 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123275.736837 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125187.249057 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128821.830084 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126862.455726 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123884.203616 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123746.096439 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122373.769889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124320.527414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 123910.475487 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123843.000934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123728.914440 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122785.887007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124055.667281 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 123809.733679 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126131.147541 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123884.203616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123746.096439 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123407.692308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122373.769889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.527414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 123910.475487 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176834.901223 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179931.587370 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 177090.590213 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149054.497984 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177987.198009 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162120.777149 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113688.618263 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162830.378861 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179087.682018 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 170136.187539 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123843.000934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123728.914440 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125403.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122785.887007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124055.667281 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 123809.733679 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188303.818502 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191423.314007 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188345.771519 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158568.564291 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190096.477052 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172712.012469 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173203.915743 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190852.369528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 181082.924931 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 31797 # Transaction distribution -system.membus.trans_dist::ReadResp 68067 # Transaction distribution +system.membus.trans_dist::ReadResp 68202 # Transaction distribution system.membus.trans_dist::WriteReq 27588 # Transaction distribution system.membus.trans_dist::WriteResp 27588 # Transaction distribution -system.membus.trans_dist::Writeback 132026 # Transaction distribution -system.membus.trans_dist::CleanEvict 8663 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131902 # Transaction distribution +system.membus.trans_dist::CleanEvict 8715 # Transaction distribution system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4641 # Transaction distribution -system.membus.trans_dist::ReadExReq 138194 # Transaction distribution -system.membus.trans_dist::ReadExResp 138194 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36271 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution +system.membus.trans_dist::ReadExReq 138223 # Transaction distribution +system.membus.trans_dist::ReadExResp 138223 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36406 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 580716 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 689615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473420 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 581002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 689891 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17328028 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17492021 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17495093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19809141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 503 # Total snoops (count) -system.membus.snoop_fanout::samples 415635 # Request fanout histogram +system.membus.pkt_size::total 19812213 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 495 # Total snoops (count) +system.membus.snoop_fanout::samples 415719 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 415635 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 415719 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 415635 # Request fanout histogram -system.membus.reqLayer0.occupancy 95974000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 415719 # Request fanout histogram +system.membus.reqLayer0.occupancy 95454500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1718000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1728500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 923083346 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 923427409 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1016456858 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1018310336 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64493372 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64109029 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2557,59 +2567,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5623278 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2831878 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 48082 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 557 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5625045 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2831932 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 48184 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 147787 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2643011 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 147963 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2644441 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 836563 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2046694 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2917 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 59 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2976 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296419 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296419 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1937296 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 557950 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 836893 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1896241 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 151625 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 71 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2903 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296799 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296799 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1937373 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 559190 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5772132 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2677725 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 39632 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 158982 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8648471 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124011712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99951221 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 59380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 271116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224293429 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 211232 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5937467 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.022790 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.149234 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5772018 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2682598 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162458 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8657634 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 245374528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100080181 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62636 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284772 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 345802117 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 207035 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3148875 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027211 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.162698 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5802151 97.72% 97.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 135316 2.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 3063191 97.28% 97.28% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85684 2.72% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5937467 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3598371995 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3148875 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5537375493 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 269876 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2908371640 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2909027051 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1327935857 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1330509019 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24806959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24943913 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 91622154 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 91705109 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 9d627bc78..27dee726c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.573912 # Number of seconds simulated -sim_ticks 47573912126000 # Number of ticks simulated -final_tick 47573912126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.381663 # Number of seconds simulated +sim_ticks 47381662864000 # Number of ticks simulated +final_tick 47381662864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125865 # Simulator instruction rate (inst/s) -host_op_rate 148024 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6578075559 # Simulator tick rate (ticks/s) -host_mem_usage 723980 # Number of bytes of host memory used -host_seconds 7232.19 # Real time elapsed on the host -sim_insts 910282032 # Number of instructions simulated -sim_ops 1070541696 # Number of ops (including micro ops) simulated +host_inst_rate 174071 # Simulator instruction rate (inst/s) +host_op_rate 204726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9833457902 # Simulator tick rate (ticks/s) +host_mem_usage 805560 # Number of bytes of host memory used +host_seconds 4818.41 # Real time elapsed on the host +sim_insts 838745469 # Number of instructions simulated +sim_ops 986455629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 153088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 136640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7678784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 42964232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17895808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 154176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 129664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3679616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 16152336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14975872 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 446400 # Number of bytes read from this memory -system.physmem.bytes_read::total 104366616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7678784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3679616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11358400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83323200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 42368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 41792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 6976384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35367624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9096640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 59520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 61888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3056960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 12429456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7583744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 432640 # Number of bytes read from this memory +system.physmem.bytes_read::total 75149016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 6976384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3056960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10033344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 59523200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 83343784 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2135 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 119981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 671329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 279622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57494 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 252393 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 233998 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6975 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1630754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1301925 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 59543784 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 109006 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 552632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 142135 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 194223 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118496 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6760 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1174229 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 930050 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1304499 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 161407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 903105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 376169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 339521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 314792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2193778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 161407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77345 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 238753 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1751447 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 932624 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 147238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 746441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 191987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 262326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1586036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147238 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 211756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1256250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1751880 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1751447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3218 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 161407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 903537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 376169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 339521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 314792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3945658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1630754 # Number of read requests accepted -system.physmem.writeReqs 1304499 # Number of write requests accepted -system.physmem.readBursts 1630754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1304499 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104327040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 41216 # Total number of bytes read from write queue -system.physmem.bytesWritten 83343168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104366616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 83343784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 644 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 221732 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 95834 # Per bank write bursts -system.physmem.perBankRdBursts::1 103052 # Per bank write bursts -system.physmem.perBankRdBursts::2 97330 # Per bank write bursts -system.physmem.perBankRdBursts::3 103782 # Per bank write bursts -system.physmem.perBankRdBursts::4 100129 # Per bank write bursts -system.physmem.perBankRdBursts::5 106515 # Per bank write bursts -system.physmem.perBankRdBursts::6 99389 # Per bank write bursts -system.physmem.perBankRdBursts::7 99717 # Per bank write bursts -system.physmem.perBankRdBursts::8 91352 # Per bank write bursts -system.physmem.perBankRdBursts::9 148680 # Per bank write bursts -system.physmem.perBankRdBursts::10 90509 # Per bank write bursts -system.physmem.perBankRdBursts::11 96337 # Per bank write bursts -system.physmem.perBankRdBursts::12 96747 # Per bank write bursts -system.physmem.perBankRdBursts::13 106196 # Per bank write bursts -system.physmem.perBankRdBursts::14 95843 # Per bank write bursts -system.physmem.perBankRdBursts::15 98698 # Per bank write bursts -system.physmem.perBankWrBursts::0 79474 # Per bank write bursts -system.physmem.perBankWrBursts::1 83004 # Per bank write bursts -system.physmem.perBankWrBursts::2 79696 # Per bank write bursts -system.physmem.perBankWrBursts::3 83932 # Per bank write bursts -system.physmem.perBankWrBursts::4 80263 # Per bank write bursts -system.physmem.perBankWrBursts::5 85902 # Per bank write bursts -system.physmem.perBankWrBursts::6 82233 # Per bank write bursts -system.physmem.perBankWrBursts::7 81457 # Per bank write bursts -system.physmem.perBankWrBursts::8 76873 # Per bank write bursts -system.physmem.perBankWrBursts::9 82502 # Per bank write bursts -system.physmem.perBankWrBursts::10 77306 # Per bank write bursts -system.physmem.perBankWrBursts::11 81622 # Per bank write bursts -system.physmem.perBankWrBursts::12 79893 # Per bank write bursts -system.physmem.perBankWrBursts::13 86888 # Per bank write bursts -system.physmem.perBankWrBursts::14 78601 # Per bank write bursts -system.physmem.perBankWrBursts::15 82591 # Per bank write bursts +system.physmem.bw_write::total 1256684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1256250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 147238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 746876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 191987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 262326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2842720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1174229 # Number of read requests accepted +system.physmem.writeReqs 932624 # Number of write requests accepted +system.physmem.readBursts 1174229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 932624 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 75113152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37504 # Total number of bytes read from write queue +system.physmem.bytesWritten 59543040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 75149016 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 59543784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 586 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 448232 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71067 # Per bank write bursts +system.physmem.perBankRdBursts::1 73380 # Per bank write bursts +system.physmem.perBankRdBursts::2 69314 # Per bank write bursts +system.physmem.perBankRdBursts::3 74537 # Per bank write bursts +system.physmem.perBankRdBursts::4 66547 # Per bank write bursts +system.physmem.perBankRdBursts::5 79030 # Per bank write bursts +system.physmem.perBankRdBursts::6 66275 # Per bank write bursts +system.physmem.perBankRdBursts::7 68082 # Per bank write bursts +system.physmem.perBankRdBursts::8 68948 # Per bank write bursts +system.physmem.perBankRdBursts::9 127738 # Per bank write bursts +system.physmem.perBankRdBursts::10 63222 # Per bank write bursts +system.physmem.perBankRdBursts::11 73993 # Per bank write bursts +system.physmem.perBankRdBursts::12 67075 # Per bank write bursts +system.physmem.perBankRdBursts::13 69321 # Per bank write bursts +system.physmem.perBankRdBursts::14 63089 # Per bank write bursts +system.physmem.perBankRdBursts::15 72025 # Per bank write bursts +system.physmem.perBankWrBursts::0 57427 # Per bank write bursts +system.physmem.perBankWrBursts::1 61393 # Per bank write bursts +system.physmem.perBankWrBursts::2 59144 # Per bank write bursts +system.physmem.perBankWrBursts::3 61303 # Per bank write bursts +system.physmem.perBankWrBursts::4 56823 # Per bank write bursts +system.physmem.perBankWrBursts::5 63517 # Per bank write bursts +system.physmem.perBankWrBursts::6 54876 # Per bank write bursts +system.physmem.perBankWrBursts::7 56576 # Per bank write bursts +system.physmem.perBankWrBursts::8 56101 # Per bank write bursts +system.physmem.perBankWrBursts::9 62480 # Per bank write bursts +system.physmem.perBankWrBursts::10 54750 # Per bank write bursts +system.physmem.perBankWrBursts::11 61148 # Per bank write bursts +system.physmem.perBankWrBursts::12 54574 # Per bank write bursts +system.physmem.perBankWrBursts::13 57375 # Per bank write bursts +system.physmem.perBankWrBursts::14 53605 # Per bank write bursts +system.physmem.perBankWrBursts::15 59268 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 61 # Number of times write queue was full causing retry -system.physmem.totGap 47573910147500 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 47381660751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1630724 # Read request sizes (log2) +system.physmem.readPktSize::6 1174199 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1301925 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 998903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 33585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 31320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 28483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 22337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1220 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 81 # What read queue length does an incoming req see +system.physmem.writePktSize::6 930050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 756841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 295232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 26539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 15837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,162 +188,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 64725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 69469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 81831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 83061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 87643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 87918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 95292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 88789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 82985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 78170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 186.082044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.846498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.592795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 603416 59.83% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198742 19.71% 79.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66381 6.58% 86.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35101 3.48% 89.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23988 2.38% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 15328 1.52% 93.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10269 1.02% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9973 0.99% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45334 4.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008532 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 74360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.921678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 319.874978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 74357 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 16213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 45390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 50223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 52287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 55018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58169 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::36 611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 709891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 189.684557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 114.673344 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.164844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 431942 60.85% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 132623 18.68% 79.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44376 6.25% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24102 3.40% 89.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15088 2.13% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9957 1.40% 92.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7669 1.08% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7642 1.08% 94.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 36492 5.14% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 709891 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 51534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.773974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.344580 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 51531 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 74360 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 74360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.512601 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.043743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.433062 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70224 94.44% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1905 2.56% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 313 0.42% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 309 0.42% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 95 0.13% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 310 0.42% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 189 0.25% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 82 0.11% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 85 0.11% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 110 0.15% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 46 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 59 0.08% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 410 0.55% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 26 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 107 0.14% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 51534 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 51534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.053324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.386136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.764507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48029 93.20% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1359 2.64% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 210 0.41% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 316 0.61% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 0.15% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 304 0.59% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 196 0.38% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 89 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 103 0.20% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 90 0.17% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 42 0.08% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 57 0.11% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 406 0.79% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 44 0.09% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 34 0.07% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 103 0.20% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 20 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 74360 # Writes before turning the bus around for reads -system.physmem.totQLat 52515283986 # Total ticks spent queuing -system.physmem.totMemAccLat 83079846486 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8150550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32215.79 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 51534 # Writes before turning the bus around for reads +system.physmem.totQLat 26583019130 # Total ticks spent queuing +system.physmem.totMemAccLat 48588825380 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5868215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22650.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50965.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41400.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.59 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 1305984 # Number of row buffer hits during reads -system.physmem.writeRowHits 617830 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.44 # Row buffer hit rate for writes -system.physmem.avgGap 16207771.58 # Average gap between requests -system.physmem.pageHitRate 65.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3848576760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2099917875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6284834400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4250627280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1215004983300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27478552093500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31817337547515 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.798037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45712218150079 # Time in different power states -system.physmem_0.memoryStateTime::REF 1588597400000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.83 # Average write queue length when enqueuing +system.physmem.readRowHits 952385 # Number of row buffer hits during reads +system.physmem.writeRowHits 441721 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 47.48 # Row buffer hit rate for writes +system.physmem.avgGap 22489305.50 # Average gap between requests +system.physmem.pageHitRate 66.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2710380960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1478878500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4432209600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3052442880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1177500235590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27396100823250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31680014630220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.613444 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45575607610794 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582177740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 273094361171 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223874273456 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3775925160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2060276625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6429961200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4187868480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1217449094850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27476408136000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31817607776715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.803717 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45708592383178 # Time in different power states -system.physmem_1.memoryStateTime::REF 1588597400000 # Time in different power states +system.physmem_1.actEnergy 2656364760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1449405375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4722003000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2976166800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094739659440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1182079758375 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27392083725750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31680707083500 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.628058 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45568857815114 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582177740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 276721037822 # Time in different power states +system.physmem_1.memoryStateTime::ACT 230624127636 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -374,18 +376,18 @@ system.realview.nvmem.bw_total::total 28 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 141076080 # Number of BP lookups -system.cpu0.branchPred.condPredicted 100250771 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6354710 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 105662880 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77608899 # Number of BTB hits +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 125258409 # Number of BP lookups +system.cpu0.branchPred.condPredicted 88001025 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5802079 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 93100413 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 67841086 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.449540 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16417680 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1072595 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.868727 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15085862 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1028654 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -416,63 +418,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 302583 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 302583 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11677 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91984 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 302583 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 302583 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 302583 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 103661 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 102356 98.74% 98.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 962 0.93% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 38 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 45 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 103661 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 91984 88.74% 88.74% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11677 11.26% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 103661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302583 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 252652 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 252652 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7537 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 66702 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 252652 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 252652 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 252652 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 74239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22181.016716 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20809.120487 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13879.929548 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 73678 99.24% 99.24% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 179 0.24% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 332 0.45% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 74239 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66702 89.85% 89.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 7537 10.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 74239 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 252652 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302583 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 252652 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 74239 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 406244 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 74239 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 326891 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91224751 # DTB read hits -system.cpu0.dtb.read_misses 252123 # DTB read misses -system.cpu0.dtb.write_hits 79969156 # DTB write hits -system.cpu0.dtb.write_misses 50460 # DTB write misses +system.cpu0.dtb.read_hits 81678885 # DTB read hits +system.cpu0.dtb.read_misses 209727 # DTB read misses +system.cpu0.dtb.write_hits 70936828 # DTB write hits +system.cpu0.dtb.write_misses 42925 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 39295 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 989 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 11229 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 33720 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 8048 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11007 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91476874 # DTB read accesses -system.cpu0.dtb.write_accesses 80019616 # DTB write accesses +system.cpu0.dtb.perms_faults 9709 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81888612 # DTB read accesses +system.cpu0.dtb.write_accesses 70979753 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 171193907 # DTB hits -system.cpu0.dtb.misses 302583 # DTB misses -system.cpu0.dtb.accesses 171496490 # DTB accesses +system.cpu0.dtb.hits 152615713 # DTB hits +system.cpu0.dtb.misses 252652 # DTB misses +system.cpu0.dtb.accesses 152868365 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -502,187 +502,191 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 69790 # Table walker walks requested -system.cpu0.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 704 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58261 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 58965 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 57570 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1255 2.13% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 40 0.07% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.08% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 58965 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58261 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 704 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58965 # Table walker page sizes translated +system.cpu0.itb.walker.walks 57977 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57977 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 503 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46742 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57977 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57977 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 47245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 24873.087099 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23068.832563 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17067.215870 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 43882 92.88% 92.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2853 6.04% 98.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 11 0.02% 98.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 288 0.61% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 169 0.36% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 4 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 47245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46742 98.94% 98.94% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 503 1.06% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 47245 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57977 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57977 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58965 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58965 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 128755 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 253370493 # ITB inst hits -system.cpu0.itb.inst_misses 69790 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 47245 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 47245 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 105222 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 224840362 # ITB inst hits +system.cpu0.itb.inst_misses 57977 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28357 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24328 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 216294 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 193753 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 253440283 # ITB inst accesses -system.cpu0.itb.hits 253370493 # DTB hits -system.cpu0.itb.misses 69790 # DTB misses -system.cpu0.itb.accesses 253440283 # DTB accesses -system.cpu0.numCycles 1081338531 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 224898339 # ITB inst accesses +system.cpu0.itb.hits 224840362 # DTB hits +system.cpu0.itb.misses 57977 # DTB misses +system.cpu0.itb.accesses 224898339 # DTB accesses +system.cpu0.numCycles 954325944 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 467223626 # Number of instructions committed -system.cpu0.committedOps 548903732 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 48040966 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5433 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 94067362325 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.314392 # CPI: cycles per instruction -system.cpu0.ipc 0.432079 # IPC: instructions per cycle +system.cpu0.committedInsts 417810947 # Number of instructions committed +system.cpu0.committedOps 490605107 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 41344261 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4694 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93809718025 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.284109 # CPI: cycles per instruction +system.cpu0.ipc 0.437807 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5510 # number of quiesce instructions executed -system.cpu0.tickCycles 755200178 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 326138353 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5943709 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.631098 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 162232873 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5944219 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.292546 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.631098 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.993420 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.993420 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 345517845 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 345517845 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 83485003 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83485003 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 74196086 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 74196086 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 250296 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 250296 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125849 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 125849 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1837182 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1837182 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1810329 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1810329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 157681089 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 157681089 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 157931385 # number of overall hits -system.cpu0.dcache.overall_hits::total 157931385 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3676950 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3676950 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2497111 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2497111 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 700297 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 700297 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 789920 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 789920 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172643 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172643 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197460 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197460 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6174061 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6174061 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6874358 # number of overall misses -system.cpu0.dcache.overall_misses::total 6874358 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 65602264000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 65602264000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 59773944000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 59773944000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 75379073500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 75379073500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2981608500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2981608500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4714245500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4714245500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5404500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5404500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 125376208000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125376208000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 125376208000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125376208000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87161953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 87161953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76693197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76693197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 950593 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 950593 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 915769 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 915769 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2009825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2007789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2007789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163855150 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 163855150 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164805743 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164805743 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.042185 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.042185 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032560 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.032560 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.736695 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.736695 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.862576 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.862576 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098347 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098347 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037680 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.037680 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041712 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.041712 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17841.489278 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17841.489278 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23937.239474 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23937.239474 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 95426.212148 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 95426.212148 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 17270.370070 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 17270.370070 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23874.432797 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23874.432797 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 4756 # number of quiesce instructions executed +system.cpu0.tickCycles 674001287 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 280324657 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5190067 # number of replacements +system.cpu0.dcache.tags.tagsinuse 482.757722 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 144829115 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5190578 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.902310 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.757722 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942886 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.942886 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 307937411 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 307937411 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 74836049 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 74836049 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 65744025 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 65744025 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 248898 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 248898 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 135683 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 135683 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1688860 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1688860 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1659238 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1659238 # number of StoreCondReq hits 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+system.cpu0.dcache.WriteReq_miss_latency::total 55065851500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 67163849000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 67163849000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2254990500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2254990500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5008928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5008928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5076500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5076500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 106109526500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 106109526500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 106109526500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 106109526500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78040185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78040185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 67915964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 67915964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 832328 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 832328 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 864557 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 864557 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1839410 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1839410 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1837806 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1837806 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 145956149 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 145956149 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 146788477 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 146788477 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041058 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041058 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031980 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.031980 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.700962 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.700962 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843061 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843061 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081847 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081847 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097164 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097164 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036833 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.036833 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040599 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.040599 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15930.558191 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15930.558191 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25353.314020 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25353.314020 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92147.406822 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92147.406822 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14978.349386 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14978.349386 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28050.538170 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28050.538170 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20306.927321 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20306.927321 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18238.242466 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18238.242466 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19737.359784 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19737.359784 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17805.090607 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17805.090607 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,161 +695,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3994886 # number of writebacks -system.cpu0.dcache.writebacks::total 3994886 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471328 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 471328 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1040644 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1040644 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 61 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 61 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43748 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43748 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 50 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1511972 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1511972 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1511972 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1511972 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3205622 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3205622 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1456467 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1456467 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 694705 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 694705 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 789859 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 789859 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128895 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128895 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 197410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4662089 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4662089 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356794 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5356794 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14687 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14687 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15563 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15563 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30250 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30250 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51339121000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51339121000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33967610000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33967610000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18528677500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18528677500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 74583001500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 74583001500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1907396500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1907396500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4514361000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4514361000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5031000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5031000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85306731000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 85306731000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103835408500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 103835408500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2448224000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2448224000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2535196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2535196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4983420500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4983420500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036778 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036778 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.730812 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.730812 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.862509 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.862509 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032504 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032504 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23321.922158 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5190079 # number of writebacks +system.cpu0.dcache.writebacks::total 5190079 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 389569 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 389569 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 893829 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 893829 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 64 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 64 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40085 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40085 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 63 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1283398 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1283398 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1283398 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1283398 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814567 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2814567 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1278110 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1278110 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 581694 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 581694 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 728810 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 728810 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110465 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110465 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 178505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 178505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4092677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4092677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4674371 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4674371 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16748 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16748 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18251 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18251 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34999 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34999 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40095557000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40095557000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32063318500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32063318500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14032843000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14032843000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 66427837000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 66427837000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1488538500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1488538500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4826102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4826102000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4518500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4518500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 72158875500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 72158875500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 86191718500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 86191718500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3021431000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3021431000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3257996500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3257996500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6279427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6279427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036066 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036066 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018819 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.698876 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.698876 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842987 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842987 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060055 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060055 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097129 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028040 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028040 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031844 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031844 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.728384 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14245.728384 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25086.509377 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25086.509377 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24124.097893 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.097893 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91145.616827 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91145.616827 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13475.204816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13475.204816 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27036.228677 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27036.228677 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19383.871864 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164741.173554 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17631.216805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17631.216805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18439.212142 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18439.212142 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180405.481251 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180405.481251 # average ReadReq mshr uncacheable latency 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-system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890260 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999786 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999786 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 8911456 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 215729294 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 8911968 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.206695 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor 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515987824 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 243455405 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 243455405 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 243455405 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 243455405 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 243455405 # number of overall hits -system.cpu0.icache.overall_hits::total 243455405 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9692338 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9692338 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9692338 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9692338 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9692338 # number of overall misses -system.cpu0.icache.overall_misses::total 9692338 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102847685000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 102847685000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 102847685000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 102847685000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 102847685000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 102847685000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 253147743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 253147743 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 253147743 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 253147743 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 253147743 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 253147743 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038287 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038287 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038287 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038287 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038287 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038287 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10611.235906 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10611.235906 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10611.235906 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10611.235906 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10611.235906 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 458194521 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 458194521 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 215729294 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 215729294 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 215729294 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 215729294 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 215729294 # number of overall hits +system.cpu0.icache.overall_hits::total 215729294 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8911978 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 8911978 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8911978 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 8911978 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8911978 # number of overall misses +system.cpu0.icache.overall_misses::total 8911978 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92482342000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 92482342000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 92482342000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 92482342000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 92482342000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 92482342000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 224641272 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 224641272 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 224641272 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 224641272 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 224641272 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 224641272 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039672 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039672 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039672 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039672 # miss rate for demand accesses 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was blocked @@ -854,506 +858,499 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9692338 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9692338 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9692338 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9692338 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9692338 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9692338 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 8911456 # number of writebacks +system.cpu0.icache.writebacks::total 8911456 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8911978 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 8911978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8911978 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 8911978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8911978 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 8911978 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 98001516000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 98001516000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 98001516000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 98001516000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 98001516000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 98001516000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038287 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038287 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038287 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038287 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10111.235906 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10111.235906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10111.235906 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88026353500 # number of ReadReq MSHR miss cycles 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cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039672 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039672 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039672 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039672 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9877.308214 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9877.308214 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9877.308214 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7930582 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7930908 # number of prefetch candidates identified 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uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3121073500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3121073500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6008334000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13004489000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027689 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552649 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552649 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.816952 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816952 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999527 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999527 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215996 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215996 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084825 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.266802 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266802 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.750042 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.750042 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139080 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239772 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239772 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074243 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256623 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256623 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772261 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772261 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.129745 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021659 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046434 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.074243 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252758 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187852 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178601 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26106.536022 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41102.047113 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30802.220271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30802.220271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19512.736623 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19512.736623 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1031874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55487.890257 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.890257 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31490.545606 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30754.680317 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30754.680317 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108194.184996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108194.184996 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34358.895348 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24927.224880 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27816.749931 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31490.545606 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36135.828071 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41102.047113 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36203.474366 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172394.345594 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143119.676499 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171008.355707 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171008.355707 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171671.590617 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 148949.569341 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 32152230 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16420555 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 569005 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 568969 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 939547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 14756064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15563 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15563 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5525670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 13869690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1023479 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 455350 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 356742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 509038 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1302016 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1231079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9692338 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5147566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 792720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 788675 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29179671 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19139148 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 387023 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1234112 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 49939954 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623657344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598500446 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1429032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4559656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1228146478 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6651761 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 39123003 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.023394 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.151159 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 29004574 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14815953 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2223 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1990994 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1990568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 781840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13286786 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18251 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4847792 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 10690718 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2645908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 891756 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 320296 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 480335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1119465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1052013 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8911978 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4503059 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 735449 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 726880 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26838850 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16809682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 328338 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1022103 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 44998973 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1143972032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629474552 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3859768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1778547864 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6630650 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21811897 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104823 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.306390 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 38207781 97.66% 97.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 915186 2.34% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 36 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19525925 89.52% 89.52% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2285546 10.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 426 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 39123003 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 20385491499 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 189810874 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21811897 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 28866629481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 172367004 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14619906616 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 13449935466 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8517245437 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7428549534 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 208413461 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 173196405 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 664225858 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 539756748 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 135994038 # Number of BP lookups -system.cpu1.branchPred.condPredicted 97681271 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5923294 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 101767942 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 74881085 # Number of BTB hits +system.cpu1.branchPred.lookups 127068265 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89752795 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6099791 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 94409743 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 68319168 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.580229 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15572056 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1048784 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.364531 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15069899 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 999135 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1383,62 +1380,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 278179 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 278179 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9856 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80934 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 278179 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 278179 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 278179 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 90790 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 89574 98.66% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 162 0.18% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 899 0.99% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 47 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 21 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 36 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 90790 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80934 89.14% 89.14% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9856 10.86% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90790 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 278179 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 271482 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 271482 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7964 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78105 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 271482 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 271482 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 271482 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 86069 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22755.010515 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21243.396519 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15660.005020 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 85331 99.14% 99.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 168 0.20% 99.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 495 0.58% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 14 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 20 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 86069 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78105 90.75% 90.75% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7964 9.25% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 86069 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 271482 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 278179 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 271482 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 86069 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90790 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 368969 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 86069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 357551 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 86408994 # DTB read hits -system.cpu1.dtb.read_misses 229031 # DTB read misses -system.cpu1.dtb.write_hits 76265809 # DTB write hits -system.cpu1.dtb.write_misses 49148 # DTB write misses +system.cpu1.dtb.read_hits 82675138 # DTB read hits +system.cpu1.dtb.read_misses 225741 # DTB read misses +system.cpu1.dtb.write_hits 73180273 # DTB write hits +system.cpu1.dtb.write_misses 45741 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36480 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1565 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 7972 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37272 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1666 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8268 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11612 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 86638025 # DTB read accesses -system.cpu1.dtb.write_accesses 76314957 # DTB write accesses +system.cpu1.dtb.perms_faults 11369 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 82900879 # DTB read accesses +system.cpu1.dtb.write_accesses 73226014 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162674803 # DTB hits -system.cpu1.dtb.misses 278179 # DTB misses -system.cpu1.dtb.accesses 162952982 # DTB accesses +system.cpu1.dtb.hits 155855411 # DTB hits +system.cpu1.dtb.misses 271482 # DTB misses +system.cpu1.dtb.accesses 156126893 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1468,189 +1465,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61280 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61280 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 546 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52744 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 61280 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61280 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61280 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53290 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 52075 97.72% 97.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1075 2.02% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 69604 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69604 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 666 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61994 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 69604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69604 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 62660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25321.249601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23483.555874 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17582.582178 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 61881 98.76% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 12 0.02% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 712 1.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53290 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52744 98.98% 98.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 546 1.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53290 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 62660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61994 98.94% 98.94% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 666 1.06% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62660 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61280 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69604 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69604 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53290 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53290 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 114570 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 242169117 # ITB inst hits -system.cpu1.itb.inst_misses 61280 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132264 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 226404999 # ITB inst hits +system.cpu1.itb.inst_misses 69604 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25722 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37374 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1001 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26762 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205735 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203402 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 242230397 # ITB inst accesses -system.cpu1.itb.hits 242169117 # DTB hits -system.cpu1.itb.misses 61280 # DTB misses -system.cpu1.itb.accesses 242230397 # DTB accesses -system.cpu1.numCycles 953928196 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 226474603 # ITB inst accesses +system.cpu1.itb.hits 226404999 # DTB hits +system.cpu1.itb.misses 69604 # DTB misses +system.cpu1.itb.accesses 226474603 # DTB accesses +system.cpu1.numCycles 896249910 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 443058406 # Number of instructions committed -system.cpu1.committedOps 521637964 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 48259182 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94194636881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.153053 # CPI: cycles per instruction -system.cpu1.ipc 0.464457 # IPC: instructions per cycle +system.cpu1.committedInsts 420934522 # Number of instructions committed +system.cpu1.committedOps 495850522 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 42911431 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4588 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93867828238 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.129191 # CPI: cycles per instruction +system.cpu1.ipc 0.469662 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13665 # number of quiesce instructions executed -system.cpu1.tickCycles 720990302 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 232937894 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5271409 # number of replacements -system.cpu1.dcache.tags.tagsinuse 430.049497 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154587010 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5271921 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.322710 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.049497 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839940 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.839940 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 13511 # number of quiesce instructions executed +system.cpu1.tickCycles 680922299 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 215327611 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4921419 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.899025 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 148299852 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4921931 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.130421 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.899025 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896287 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.896287 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 327906694 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 327906694 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79069141 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79069141 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70951579 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70951579 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 254478 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 254478 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 200049 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 200049 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1835496 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1835496 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1797284 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1797284 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150020720 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150020720 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150275198 # number of overall hits -system.cpu1.dcache.overall_hits::total 150275198 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3348164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3348164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2321727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2321727 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 675333 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 675333 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 453842 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 453842 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 163069 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 163069 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199393 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199393 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5669891 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5669891 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6345224 # number of overall misses -system.cpu1.dcache.overall_misses::total 6345224 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55281073500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 55281073500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 48428743000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 48428743000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20617335000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20617335000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2629405000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2629405000 # number of LoadLockedReq miss cycles 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accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73273306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73273306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 929811 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 929811 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653891 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 653891 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998565 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1998565 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1996677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1996677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 155690611 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 155690611 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 156620422 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 156620422 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040625 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.040625 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031686 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031686 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.726312 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.726312 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.694064 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.694064 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081593 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081593 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099862 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099862 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036418 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.036418 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040513 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040513 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 313981831 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 313981831 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 76035057 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76035057 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68321160 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68321160 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 232478 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 232478 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 184182 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 184182 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1549703 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1549703 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1524262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1524262 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 144356217 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 144356217 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144588695 # number of overall hits +system.cpu1.dcache.overall_hits::total 144588695 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3124160 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3124160 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2104338 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2104338 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 561771 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 561771 # number of SoftPFReq misses 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StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7589000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 92781043500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 92781043500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 92781043500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 92781043500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 79159217 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 79159217 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70425498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70425498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 794249 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 794249 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 694902 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 694902 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1706247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1706247 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1704699 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1704699 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 149584715 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 149584715 # number of demand (read+write) accesses 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0.091748 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091748 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105847 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105847 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034953 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034953 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038505 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.038505 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15435.130403 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15435.130403 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21174.937914 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21174.937914 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37795.435855 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37795.435855 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15508.518372 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15508.518372 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28286.967196 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28286.967196 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17745.257529 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17745.257529 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16023.615397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16023.615397 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1659,161 +1653,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3447609 # number of writebacks -system.cpu1.dcache.writebacks::total 3447609 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379178 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 379178 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 964484 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 964484 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 92 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 92 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41281 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41281 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1343662 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1343662 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1343662 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1343662 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2968986 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2968986 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1357243 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1357243 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 675071 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 675071 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 453750 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 453750 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121788 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121788 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199325 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 199325 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326229 # number of demand (read+write) MSHR misses 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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44110385000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27847514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27847514500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16178845000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16178845000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20154706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20154706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1764852000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1764852000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4482506000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4482506000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3997500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3997500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71957899500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 71957899500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88136744500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 88136744500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4055697500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4055697500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3925636000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3925636000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7981333500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7981333500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036024 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036024 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018523 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018523 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.726030 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.726030 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.693923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.693923 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060938 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060938 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099828 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099828 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027787 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027787 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031933 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031933 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14857.053890 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14857.053890 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20517.707220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20517.707220 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23966.138377 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23966.138377 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44418.084848 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44418.084848 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14491.181397 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14491.181397 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22488.428446 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22488.428446 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4921438 # number of writebacks +system.cpu1.dcache.writebacks::total 4921438 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 336855 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 336855 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 865157 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 865157 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 99 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39963 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39963 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1202012 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1202012 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1202012 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1202012 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2787305 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2787305 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1239181 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1239181 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 561309 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 561309 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 510621 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 510621 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116581 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116581 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 180393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 180393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4026486 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4026486 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4587795 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4587795 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20902 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20902 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19312 # number of WriteReq MSHR uncacheable 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+system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18783135000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18783135000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1568875000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1568875000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4920605000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4920605000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7128000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7128000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 65275568000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 65275568000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 77920489000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 77920489000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3868216000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3868216000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3618681000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3618681000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7486897000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7486897000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035211 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035211 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017596 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017596 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706717 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706717 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.734810 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.734810 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068326 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105821 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105821 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030508 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030508 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13935.147930 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13935.147930 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21331.880089 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21331.880089 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22527.557905 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22527.557905 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36784.885463 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36784.885463 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13457.381563 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13457.381563 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27277.139357 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27277.139357 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16632.938178 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16632.938178 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17622.766981 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17622.766981 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172421.456509 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172421.456509 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174340.986810 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174340.986810 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173360.270640 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173360.270640 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16211.547240 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16211.547240 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16984.300519 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16984.300519 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185064.395752 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185064.395752 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 187379.919221 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187379.919221 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 186176.381360 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 186176.381360 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9020173 # number of replacements -system.cpu1.icache.tags.tagsinuse 506.865133 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 232936753 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9020685 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.822513 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.865133 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989971 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.989971 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 9409188 # number of replacements +system.cpu1.icache.tags.tagsinuse 506.684863 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 216784534 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9409700 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 23.038411 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684863 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 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ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 241957448 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 241957448 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 241957448 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 241957448 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 241957448 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037282 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037282 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037282 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037282 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037282 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037282 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10594.907321 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10594.907321 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10594.907321 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10594.907321 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10594.907321 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 461798168 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 461798168 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 216784534 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 216784534 # number of ReadReq hits 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ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 95979801000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 95979801000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 95979801000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 95979801000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 226194234 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 226194234 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 226194234 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 226194234 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 226194234 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 226194234 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041600 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.041600 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041600 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.041600 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041600 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.041600 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10200.091501 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10200.091501 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10200.091501 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10200.091501 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10200.091501 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1822,257 +1816,254 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9020695 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9020695 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9020695 # number of demand (read+write) MSHR misses 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system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91063080500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 91063080500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91063080500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 91063080500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91063080500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 91063080500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.037282 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037282 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.037282 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10094.907377 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10094.907377 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10094.907377 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91274951000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 91274951000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91274951000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 91274951000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91274951000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 91274951000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.041600 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041600 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.041600 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9700.091501 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9700.091501 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9700.091501 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7367099 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7368207 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6599308 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6600409 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 970 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 915185 # number of prefetches not generated due to page crossing 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accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208501 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208501 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087133 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268660 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268660 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595440 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595440 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.141188 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024845 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.056312 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087133 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.254587 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226292 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226292 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073464 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248519 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248519 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.523368 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.523368 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.123409 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019792 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.040647 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.073464 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243392 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191657 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3584500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3584500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.169835 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30203.043311 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36118.703029 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32496.215800 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32496.215800 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19755.934430 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19755.934430 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1303599.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1303599.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 40767.089256 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 40767.089256 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29425.314202 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29525.390105 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29525.390105 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 55213.942832 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 55213.942832 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30957.803939 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28555.709773 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32431.123770 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29425.314202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31936.723887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36118.703029 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32368.597869 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177059.252703 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176865.151948 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179877.200704 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179877.200704 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 178412.518029 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 178308.328785 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 29416501 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15028447 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 554511 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 554502 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 9 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 803941 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 13684916 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4553047 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 13043260 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 982334 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 29428527 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15006964 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2768 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1972954 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1972589 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 365 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 814249 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13775310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 19312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 19312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4142105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11232116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2703238 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 874176 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 414162 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 473685 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1229561 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1158646 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9020695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4893253 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 460729 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 452056 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27060072 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17084009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332493 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1088108 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 45564682 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 577330304 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 542008212 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1195776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3926416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1124460708 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6177589 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 35784390 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.024790 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.155485 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 401941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 322763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 444037 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1114947 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1047219 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9409700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4456605 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 514166 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 508289 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28226960 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15947748 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 397923 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1113211 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 45685842 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1204298752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609360975 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1520224 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4222808 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1819402759 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6269077 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 21677519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.104647 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.306153 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 34897315 97.52% 97.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 887066 2.48% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 9 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 19409393 89.54% 89.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2267761 10.46% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 365 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 35784390 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 18416469994 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 187934075 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21677519 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 29325134974 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 172530424 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13533732383 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14118247362 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7841048470 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7236066136 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 183047447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 207955878 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 597345920 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 585496227 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40341 # Transaction distribution -system.iobus.trans_dist::ReadResp 40341 # Transaction distribution -system.iobus.trans_dist::WriteReq 136603 # Transaction distribution -system.iobus.trans_dist::WriteResp 136603 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47670 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40404 # Transaction distribution +system.iobus.trans_dist::ReadResp 40404 # Transaction distribution +system.iobus.trans_dist::WriteReq 136972 # Transaction distribution +system.iobus.trans_dist::WriteResp 136972 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47770 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2327,18 +2310,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231760 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47690 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354752 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47790 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2348,797 +2331,798 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155927 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36193000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513405 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47202500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25874502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36406501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 123500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 566159223 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 566812397 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92927000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147952000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148200000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115609 # number of replacements -system.iocache.tags.tagsinuse 11.261931 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115625 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9146785142000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.823570 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.438361 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.238973 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464898 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.703871 # Average percentage of cache occupancy +system.iocache.tags.replacements 115872 # number of replacements +system.iocache.tags.tagsinuse 11.264501 # Cycle average of tags in use +system.iocache.tags.total_refs 6 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115888 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000052 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9145998133000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.414921 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.849581 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463433 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.240599 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.704031 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041009 # Number of tag accesses -system.iocache.tags.data_accesses 1041009 # Number of data accesses +system.iocache.tags.tag_accesses 1043272 # Number of tag accesses +system.iocache.tags.data_accesses 1043272 # Number of data accesses +system.iocache.WriteLineReq_hits::realview.ide 2 # number of WriteLineReq hits +system.iocache.WriteLineReq_hits::total 2 # number of WriteLineReq hits system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8900 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8937 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8896 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8933 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106982 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106982 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8900 # number of demand (read+write) misses -system.iocache.demand_misses::total 8940 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8896 # number of demand (read+write) misses +system.iocache.demand_misses::total 8936 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8900 # number of overall misses -system.iocache.overall_misses::total 8940 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1696302972 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1701497972 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8896 # number of overall misses +system.iocache.overall_misses::total 8936 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5261000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1700094991 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1705355991 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13913628251 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13913628251 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1696302972 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1701866972 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1696302972 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1701866972 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 14013428406 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 14013428406 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5630000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1700094991 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1705724991 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5630000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1700094991 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1705724991 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8900 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8937 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8896 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8933 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8900 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8940 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8896 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8936 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8900 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8940 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8896 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8936 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 0.999981 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 0.999981 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190595.839551 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190388.046548 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142189.189189 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191107.800247 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190905.182022 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130365.304803 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130365.304803 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190365.433110 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 190595.839551 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190365.433110 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34247 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130988.656092 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130988.656092 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140750 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190882.384848 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140750 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 191107.800247 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190882.384848 # average overall miss latency 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-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80365.304803 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80365.304803 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 140595.839551 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140365.433110 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80988.656092 # average WriteLineReq mshr miss latency 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131670.738530 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.283558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311704 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.296629 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.222890 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219180 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.220975 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.735273 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389634 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.622169 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.143630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.127885 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.152296 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.250397 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.103583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.142888 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.085730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.435394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.313127 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.124332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.165497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068977 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.214194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.262921 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.250397 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73405.101388 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73447.407332 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73425.747080 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76522.838199 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.421053 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76500.089851 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129078.519295 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124079.362956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 128054.050765 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126097.370539 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 126467.494956 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 136875.285945 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126851.963746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128692.955590 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122985.737708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 128580.058033 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150428.056539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126927.956989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126634.953464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123319.428715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 125035.044479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148442.832748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 132299.122166 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154383.299498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159070.933014 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131241.202012 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153993.698975 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162871.815452 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158558.142321 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154180.133718 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160896.324480 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 139282.030687 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90608 # Transaction distribution -system.membus.trans_dist::ReadResp 1019089 # Transaction distribution -system.membus.trans_dist::WriteReq 38080 # Transaction distribution -system.membus.trans_dist::WriteResp 38080 # Transaction distribution -system.membus.trans_dist::Writeback 1301925 # Transaction distribution -system.membus.trans_dist::CleanEvict 271570 # Transaction distribution -system.membus.trans_dist::UpgradeReq 429176 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 310200 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115027 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 674063 # Transaction distribution -system.membus.trans_dist::ReadExResp 652544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 928481 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122552 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 90049 # Transaction distribution +system.membus.trans_dist::ReadResp 640443 # Transaction distribution +system.membus.trans_dist::WriteReq 37563 # Transaction distribution +system.membus.trans_dist::WriteResp 37563 # Transaction distribution +system.membus.trans_dist::WritebackDirty 930050 # Transaction distribution +system.membus.trans_dist::CleanEvict 190296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 413026 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 280293 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150977 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 593740 # Transaction distribution +system.membus.trans_dist::ReadExResp 574320 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 550394 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106981 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106981 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24802 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5589312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5736718 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342877 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342877 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6079595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4211327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4356581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 343179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4699760 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155927 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180435584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 180642194 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7274816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 187917010 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 648574 # Total snoops (count) -system.membus.snoop_fanout::samples 4152999 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 44580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 127415488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 127617319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7277312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7277312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 134894631 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 564682 # Total snoops (count) +system.membus.snoop_fanout::samples 3194785 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4152999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3194785 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4152999 # Request fanout histogram -system.membus.reqLayer0.occupancy 109607499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3194785 # Request fanout histogram +system.membus.reqLayer0.occupancy 109901497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20503498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 18632000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9125026082 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6680198838 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8873044520 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6549107858 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230408874 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 229362666 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3149,11 +3133,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3192,52 +3176,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12411375 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6308416 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2241470 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 182770 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 168316 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14454 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90610 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5207811 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38080 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38080 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3858986 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1729776 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481704 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 322377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 804081 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1151274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1151274 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 5124442 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9065091 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7602046 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16667137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 281816078 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 221579908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 503395986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3440017 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 14338060 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.337750 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.475069 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11369480 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6166084 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1983565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 99756 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 89163 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 10593 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 90051 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4379282 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 37563 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 37563 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3408225 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1479469 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 686639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 358765 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1045403 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1072017 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1072017 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4296486 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106981 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8273345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7109938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15383283 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 249443752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200422911 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 449866663 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2689125 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7811601 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.375584 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.487066 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9509841 66.33% 66.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4813765 33.57% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14454 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4888281 62.58% 62.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2912727 37.29% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 10593 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 14338060 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9248164097 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7811601 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8585712934 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2627637 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2584443 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5363594791 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4648327252 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4586237114 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4065319209 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 8edb1ca7a..4adb13d39 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.667490 # Number of seconds simulated -sim_ticks 51667489826000 # Number of ticks simulated -final_tick 51667489826000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.667600 # Number of seconds simulated +sim_ticks 51667599599000 # Number of ticks simulated +final_tick 51667599599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98445 # Simulator instruction rate (inst/s) -host_op_rate 115675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5518412939 # Simulator tick rate (ticks/s) -host_mem_usage 676348 # Number of bytes of host memory used -host_seconds 9362.74 # Real time elapsed on the host -sim_insts 921716010 # Number of instructions simulated -sim_ops 1083032845 # Number of ops (including micro ops) simulated +host_inst_rate 178939 # Simulator instruction rate (inst/s) +host_op_rate 210249 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10020424354 # Simulator tick rate (ticks/s) +host_mem_usage 726764 # Number of bytes of host memory used +host_seconds 5156.23 # Real time elapsed on the host +sim_insts 922648651 # Number of instructions simulated +sim_ops 1084091117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 356224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 294592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10211648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 93641864 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 394368 # Number of bytes read from this memory -system.physmem.bytes_read::total 104898696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10211648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10211648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87439552 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 355648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 310272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 9988672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94253512 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory +system.physmem.bytes_read::total 105321992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9988672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9988672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87921472 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 87460132 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1463167 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1639055 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1366243 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87942052 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 156073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1472724 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1645669 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1373773 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1368816 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 6895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1812394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2030265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1692351 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1376346 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 6883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 193326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1824229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2038453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 193326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 193326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1701675 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1692750 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1692351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 6895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1812793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3723015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1639055 # Number of read requests accepted -system.physmem.writeReqs 1368816 # Number of write requests accepted -system.physmem.readBursts 1639055 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1368816 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104838592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 60928 # Total number of bytes read from write queue -system.physmem.bytesWritten 87458560 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104898696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87460132 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 952 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 145140 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 96907 # Per bank write bursts -system.physmem.perBankRdBursts::1 103074 # Per bank write bursts -system.physmem.perBankRdBursts::2 99514 # Per bank write bursts -system.physmem.perBankRdBursts::3 96513 # Per bank write bursts -system.physmem.perBankRdBursts::4 97689 # Per bank write bursts -system.physmem.perBankRdBursts::5 108359 # Per bank write bursts -system.physmem.perBankRdBursts::6 97886 # Per bank write bursts -system.physmem.perBankRdBursts::7 97902 # Per bank write bursts -system.physmem.perBankRdBursts::8 96810 # Per bank write bursts -system.physmem.perBankRdBursts::9 157961 # Per bank write bursts -system.physmem.perBankRdBursts::10 100161 # Per bank write bursts -system.physmem.perBankRdBursts::11 104541 # Per bank write bursts -system.physmem.perBankRdBursts::12 94779 # Per bank write bursts -system.physmem.perBankRdBursts::13 97199 # Per bank write bursts -system.physmem.perBankRdBursts::14 94176 # Per bank write bursts -system.physmem.perBankRdBursts::15 94632 # Per bank write bursts -system.physmem.perBankWrBursts::0 82268 # Per bank write bursts -system.physmem.perBankWrBursts::1 85491 # Per bank write bursts -system.physmem.perBankWrBursts::2 84713 # Per bank write bursts -system.physmem.perBankWrBursts::3 83877 # Per bank write bursts -system.physmem.perBankWrBursts::4 85039 # Per bank write bursts -system.physmem.perBankWrBursts::5 91961 # Per bank write bursts -system.physmem.perBankWrBursts::6 84027 # Per bank write bursts -system.physmem.perBankWrBursts::7 85348 # Per bank write bursts -system.physmem.perBankWrBursts::8 84923 # Per bank write bursts -system.physmem.perBankWrBursts::9 91534 # Per bank write bursts -system.physmem.perBankWrBursts::10 85936 # Per bank write bursts -system.physmem.perBankWrBursts::11 89456 # Per bank write bursts -system.physmem.perBankWrBursts::12 82822 # Per bank write bursts -system.physmem.perBankWrBursts::13 84269 # Per bank write bursts -system.physmem.perBankWrBursts::14 82271 # Per bank write bursts -system.physmem.perBankWrBursts::15 82605 # Per bank write bursts +system.physmem.bw_write::total 1702073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1701675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 6883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 193326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1824627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3740527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1645669 # Number of read requests accepted +system.physmem.writeReqs 1376346 # Number of write requests accepted +system.physmem.readBursts 1645669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1376346 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 105266752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 56064 # Total number of bytes read from write queue +system.physmem.bytesWritten 87940608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 105321992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87942052 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 876 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 378251 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 98784 # Per bank write bursts +system.physmem.perBankRdBursts::1 105100 # Per bank write bursts +system.physmem.perBankRdBursts::2 100845 # Per bank write bursts +system.physmem.perBankRdBursts::3 95977 # Per bank write bursts +system.physmem.perBankRdBursts::4 103819 # Per bank write bursts +system.physmem.perBankRdBursts::5 113338 # Per bank write bursts +system.physmem.perBankRdBursts::6 98145 # Per bank write bursts +system.physmem.perBankRdBursts::7 99955 # Per bank write bursts +system.physmem.perBankRdBursts::8 93968 # Per bank write bursts +system.physmem.perBankRdBursts::9 154563 # Per bank write bursts +system.physmem.perBankRdBursts::10 98779 # Per bank write bursts +system.physmem.perBankRdBursts::11 100711 # Per bank write bursts +system.physmem.perBankRdBursts::12 92945 # Per bank write bursts +system.physmem.perBankRdBursts::13 97659 # Per bank write bursts +system.physmem.perBankRdBursts::14 91699 # Per bank write bursts +system.physmem.perBankRdBursts::15 98506 # Per bank write bursts +system.physmem.perBankWrBursts::0 83240 # Per bank write bursts +system.physmem.perBankWrBursts::1 87253 # Per bank write bursts +system.physmem.perBankWrBursts::2 86416 # Per bank write bursts +system.physmem.perBankWrBursts::3 83797 # Per bank write bursts +system.physmem.perBankWrBursts::4 90075 # Per bank write bursts +system.physmem.perBankWrBursts::5 95693 # Per bank write bursts +system.physmem.perBankWrBursts::6 84431 # Per bank write bursts +system.physmem.perBankWrBursts::7 87097 # Per bank write bursts +system.physmem.perBankWrBursts::8 83064 # Per bank write bursts +system.physmem.perBankWrBursts::9 88599 # Per bank write bursts +system.physmem.perBankWrBursts::10 84727 # Per bank write bursts +system.physmem.perBankWrBursts::11 86277 # Per bank write bursts +system.physmem.perBankWrBursts::12 82015 # Per bank write bursts +system.physmem.perBankWrBursts::13 84756 # Per bank write bursts +system.physmem.perBankWrBursts::14 80845 # Per bank write bursts +system.physmem.perBankWrBursts::15 85787 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 26 # Number of times write queue was full causing retry -system.physmem.totGap 51667488071000 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 51667597819500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1639040 # Read request sizes (log2) +system.physmem.readPktSize::6 1645654 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1366243 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1313990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 317969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 534 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1094 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1373773 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1321004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 317364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,163 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 65910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 82508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 83232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 84019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 389 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::27 84668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 92346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 82532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 83696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 80480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see 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an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.579894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.167741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.754919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 255622 39.42% 39.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156386 24.12% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60110 9.27% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34859 5.38% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25315 3.90% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18876 2.91% 85.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13882 2.14% 87.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12930 1.99% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70401 10.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648381 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.660314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 283.326654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 79282 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 648118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.103938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.284544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.148793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253468 39.11% 39.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156556 24.16% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60545 9.34% 72.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34961 5.39% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 26042 4.02% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18689 2.88% 84.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14146 2.18% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13035 2.01% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70676 10.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 648118 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79768 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.619672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 282.463170 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 79765 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79285 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79285 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.235795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.792425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.378813 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 77022 97.15% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 299 0.38% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 59 0.07% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 299 0.38% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 54 0.07% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 317 0.40% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 225 0.28% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 58 0.07% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 133 0.17% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.03% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 40 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 480 0.61% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 132 0.17% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 79768 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79768 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.225855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.793439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.200790 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 77436 97.08% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 326 0.41% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 71 0.09% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 315 0.39% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 43 0.05% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 360 0.45% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 211 0.26% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.03% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 65 0.08% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 125 0.16% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 20 0.03% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 34 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 501 0.63% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 30 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 120 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 23 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79285 # Writes before turning the bus around for reads -system.physmem.totQLat 26536419219 # Total ticks spent queuing -system.physmem.totMemAccLat 57250850469 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8190515000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16199.48 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 79768 # Writes before turning the bus around for reads +system.physmem.totQLat 26467861730 # Total ticks spent queuing +system.physmem.totMemAccLat 57307730480 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8223965000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16091.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34949.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34841.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 1330988 # Number of row buffer hits during reads -system.physmem.writeRowHits 1025273 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes -system.physmem.avgGap 17177428.18 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2459736720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1342118250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6223136400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4424051520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1319911106400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29842673702250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34551702734580 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.732053 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49645039210452 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725290840000 # Time in different power states +system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing +system.physmem.readRowHits 1338706 # Number of row buffer hits during reads +system.physmem.writeRowHits 1032034 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 17097068.62 # Average gap between requests +system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2524404960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1377403500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6364503600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4523001120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1325410671600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29837914926750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34552790914410 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.751704 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49637080843701 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725294480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 297159003548 # Time in different power states +system.physmem_0.memoryStateTime::ACT 305218373299 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2442023640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1332453375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6554020200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4431127680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1320412056885 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29842234272000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34552074836820 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.739255 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49644231851772 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725290840000 # Time in different power states +system.physmem_1.actEnergy 2375306640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1296050250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6464827200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4380881760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1318079999925 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29844345348750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34551618417405 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.729010 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49647781129555 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725294480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 297961425728 # Time in different power states +system.physmem_1.memoryStateTime::ACT 294523106445 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +337,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 252436095 # Number of BP lookups -system.cpu.branchPred.condPredicted 176405196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11951074 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 185535740 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131467669 # Number of BTB hits +system.cpu.branchPred.lookups 252640803 # Number of BP lookups +system.cpu.branchPred.condPredicted 176566458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11942340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 185523828 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131623059 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.858407 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30937069 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2133020 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.946714 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30927608 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2129490 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,63 +376,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 560363 # Table walker walks requested -system.cpu.dtb.walker.walksLong 560363 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20601 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178609 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 560363 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 560363 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 560363 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 199210 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27145.243713 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 23005.972162 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20907.221064 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 196938 98.86% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1933 0.97% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 58 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 84 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 561342 # Table walker walks requested +system.cpu.dtb.walker.walksLong 561342 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20890 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 179371 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 561342 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 561342 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 561342 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 200261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 197960 98.85% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 98.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1973 0.99% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 114 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 41 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 90 0.04% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 199210 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 178610 89.66% 89.66% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20601 10.34% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 199211 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560363 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 200261 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 179372 89.57% 89.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20890 10.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 200262 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561342 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560363 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561342 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 200262 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199211 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 759574 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 200262 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 761604 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 178192284 # DTB read hits -system.cpu.dtb.read_misses 462603 # DTB read misses -system.cpu.dtb.write_hits 157870024 # DTB write hits -system.cpu.dtb.write_misses 97760 # DTB write misses +system.cpu.dtb.read_hits 178417728 # DTB read hits +system.cpu.dtb.read_misses 463663 # DTB read misses +system.cpu.dtb.write_hits 158017805 # DTB write hits +system.cpu.dtb.write_misses 97679 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78455 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14585 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 77601 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23059 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 178654887 # DTB read accesses -system.cpu.dtb.write_accesses 157967784 # DTB write accesses +system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 178881391 # DTB read accesses +system.cpu.dtb.write_accesses 158115484 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 336062308 # DTB hits -system.cpu.dtb.misses 560363 # DTB misses -system.cpu.dtb.accesses 336622671 # DTB accesses +system.cpu.dtb.hits 336435533 # DTB hits +system.cpu.dtb.misses 561342 # DTB misses +system.cpu.dtb.accesses 336996875 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,183 +462,190 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 134893 # Table walker walks requested -system.cpu.itb.walker.walksLong 134893 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1070 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117642 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134893 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118712 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30207.312656 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25802.029077 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23121.543530 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116190 97.88% 97.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 6 0.01% 97.88% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2295 1.93% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 67 0.06% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 109 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118712 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117642 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1070 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118712 # Table walker page sizes translated +system.cpu.itb.walker.walks 135051 # Table walker walks requested +system.cpu.itb.walker.walksLong 135051 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1071 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117673 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 135051 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 135051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 135051 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118744 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30328.088156 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 58823 49.54% 49.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 57227 48.19% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.73% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 5 0.00% 97.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 2006 1.69% 99.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 464 0.39% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 29 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 88 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 29 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 14 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118744 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 117673 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1071 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118744 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134893 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134893 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135051 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 135051 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118712 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118712 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253605 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 438788360 # ITB inst hits -system.cpu.itb.inst_misses 134893 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118744 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253795 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 439141642 # ITB inst hits +system.cpu.itb.inst_misses 135051 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56501 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 55572 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 359579 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 356769 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 438923253 # ITB inst accesses -system.cpu.itb.hits 438788360 # DTB hits -system.cpu.itb.misses 134893 # DTB misses -system.cpu.itb.accesses 438923253 # DTB accesses -system.cpu.numCycles 2560804207 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 439276693 # ITB inst accesses +system.cpu.itb.hits 439141642 # DTB hits +system.cpu.itb.misses 135051 # DTB misses +system.cpu.itb.accesses 439276693 # DTB accesses +system.cpu.numCycles 2565959423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 921716010 # Number of instructions committed -system.cpu.committedOps 1083032845 # Number of ops (including micro ops) committed -system.cpu.discardedOps 92871017 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7624 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100775316475 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.778301 # CPI: cycles per instruction -system.cpu.ipc 0.359932 # IPC: instructions per cycle +system.cpu.committedInsts 922648651 # Number of instructions committed +system.cpu.committedOps 1084091117 # Number of ops (including micro ops) committed +system.cpu.discardedOps 92858708 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100770378430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.781080 # CPI: cycles per instruction +system.cpu.ipc 0.359573 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16484 # number of quiesce instructions executed -system.cpu.tickCycles 1740208465 # Number of cycles that the object actually ticked -system.cpu.idleCycles 820595742 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10718531 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930101 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320228714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10719043 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.874749 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930101 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed +system.cpu.tickCycles 1742118066 # Number of cycles that the object actually ticked +system.cpu.idleCycles 823841357 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10735802 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930082 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320587267 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10736314 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.860087 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930082 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1345217745 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1345217745 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 163909013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 163909013 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 147410694 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 147410694 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 512357 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 512357 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335795 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335795 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3851860 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3851860 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4160801 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4160801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 311319707 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 311319707 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 311832064 # number of overall hits -system.cpu.dcache.overall_hits::total 311832064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6365428 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6365428 # number of ReadReq misses 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overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 170274441 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 170274441 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 151540355 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 151540355 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911814 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1911814 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574746 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1574746 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4162508 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4162508 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4160802 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4160802 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321814796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321814796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323726610 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323726610 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027251 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027251 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732005 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.732005 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786762 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786762 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074630 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074630 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 319227057000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 319227057000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 319227057000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 319227057000 # number of overall miss cycles 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accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163173 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4163173 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 322180476 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322180476 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324093034 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324093034 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037394 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027248 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027248 # miss rate for WriteReq accesses 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036743 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18423.283556 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18423.283556 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.601960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.601960 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68167.765715 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68167.765715 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16542.454804 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16542.454804 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032617 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032617 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036747 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036747 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18470.462780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18470.462780 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48744.363767 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48744.363767 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245 # average LoadLockedReq miss latency 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+system.cpu.dcache.overall_avg_miss_latency::total 26804.514918 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,155 +654,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8229800 # number of writebacks -system.cpu.dcache.writebacks::total 8229800 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778718 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 778718 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821021 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1821021 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69509 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69509 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2599739 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2599739 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2599739 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2599739 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5586710 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5586710 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2308640 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2308640 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391918 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1391918 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238799 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1238799 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241139 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 241139 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 8239619 # number of writebacks +system.cpu.dcache.writebacks::total 8239619 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 773301 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 773301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1821450 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 142 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 142 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70152 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70152 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2594751 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2594751 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2594751 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2594751 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5602079 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5602079 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2311763 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2311763 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1393294 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1393294 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238719 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1238719 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 238457 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 238457 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7895350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7895350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9287268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9287268 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7913842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7913842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9307136 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9307136 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 95942539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 95942539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106127468000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 106127468000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26584469000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26584469000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83210863500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83210863500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3483152500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3483152500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96321163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 96321163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26939627500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26939627500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 82952613500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 82952613500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3468831500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3468831500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202070007500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 202070007500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228654476500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 228654476500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831192500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831192500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5820427500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5820427500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11651620000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11651620000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032810 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015234 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015234 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728061 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728061 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786666 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786666 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057931 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 203225321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230164948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6198462000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6198462000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207588500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207588500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12406050500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12406050500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015240 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015240 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728498 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728498 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786450 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786450 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057254 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024534 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024534 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028689 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028689 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17173.352384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17173.352384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45969.691247 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45969.691247 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19099.163169 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19099.163169 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67170.593050 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67170.593050 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14444.583829 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14444.583829 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024563 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024563 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028717 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028717 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25593.546518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25593.546518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24620.208709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24620.208709 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173047.823248 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.823248 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172682.237584 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172682.237584 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172865.006009 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172865.006009 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24130706 # number of replacements -system.cpu.icache.tags.tagsinuse 511.872431 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 414285199 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24131218 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.168019 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.872431 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 24189642 # number of replacements +system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 414582353 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24190154 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.138475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 462547654 # Number of tag accesses -system.cpu.icache.tags.data_accesses 462547654 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 414285199 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414285199 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414285199 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414285199 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414285199 # number of overall hits -system.cpu.icache.overall_hits::total 414285199 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24131228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24131228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24131228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24131228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24131228 # number of overall misses -system.cpu.icache.overall_misses::total 24131228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 326882606500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 326882606500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 326882606500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 326882606500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 326882606500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 326882606500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 438416427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 438416427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 438416427 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 438416427 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 438416427 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 438416427 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13546.041109 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13546.041109 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13546.041109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13546.041109 # average overall miss latency +system.cpu.icache.tags.tag_accesses 462962680 # Number of tag accesses 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ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.276582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004291 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044124 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044124 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.426872 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.426872 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030366 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030366 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127069.485824 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70780.463753 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70780.463753 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122757.794444 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122757.794444 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122275.211142 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122275.211142 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124960.043991 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124960.043991 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128749.529981 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128749.529981 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160545.953646 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131920.429970 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161163.783896 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161163.783896 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160854.910019 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140154.161655 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70442734 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35592438 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2280 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 70595106 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35668602 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4412 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2257 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2257 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1728553 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33080077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1731880 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33156424 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 9596069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 26854364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9613409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24185917 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2732498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 47963 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2260770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2260770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24131228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7228389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1345463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1238799 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72494093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32387839 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 691084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2167479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 107740495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1547746112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133685906 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2304392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7423736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2691160146 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2148445 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 73231054 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009642 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097721 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 47964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2264033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2264033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24190164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7242479 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238719 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72670859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32439334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687653 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 107961586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3099416704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135424530 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2273208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7370944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4244485386 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2167477 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38466398 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018246 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133841 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 72524927 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 706127 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 37764532 98.18% 98.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 701866 1.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 73231054 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 44001619997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38466398 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68278869995 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1484887 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1476392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36281501081 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36370852681 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14914900069 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14941078957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 403060948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403557888 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1239526970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1242412419 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.trans_dist::ReadReq 40327 # Transaction distribution +system.iobus.trans_dist::ReadResp 40327 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1249,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1270,104 +1281,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42171500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25807000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 34147000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 120500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565802629 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565729644 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 42000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147772000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.440024 # Cycle average of tags in use +system.iocache.tags.replacements 115488 # number of replacements +system.iocache.tags.tagsinuse 10.440019 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115504 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13160095292000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13160148501000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919182 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919178 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.tags.tag_accesses 1039911 # Number of tag accesses +system.iocache.tags.data_accesses 1039911 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses -system.iocache.demand_misses::total 8880 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses +system.iocache.demand_misses::total 8882 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8840 # number of overall misses -system.iocache.overall_misses::total 8880 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1641330150 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1646399150 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8842 # number of overall misses +system.iocache.overall_misses::total 8882 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1658170108 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1663256608 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13825092479 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13825092479 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1641330150 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1646750150 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1641330150 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1646750150 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13863609036 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13863609036 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1658170108 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1663607608 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1658170108 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1663607608 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1381,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185670.831448 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185467.967782 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187324.767204 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129613.482328 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129613.482328 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185444.836712 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185444.836712 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32333 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187301.014186 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187301.014186 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34622 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3346 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.663180 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.886351 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199330150 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1202549150 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216070108 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1219306608 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8491892479 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8491892479 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1199330150 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1202750150 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1199330150 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1202750150 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530409036 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8530409036 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1216070108 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1219507608 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1216070108 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1219507608 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1443,73 +1454,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135670.831448 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135467.967782 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79613.482328 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79613.482328 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 526484 # Transaction distribution +system.membus.trans_dist::ReadResp 528253 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::Writeback 1366243 # Transaction distribution -system.membus.trans_dist::CleanEvict 236394 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38482 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1373773 # Transaction distribution +system.membus.trans_dist::CleanEvict 233285 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 38483 # Transaction distribution -system.membus.trans_dist::ReadExReq 1149637 # Transaction distribution -system.membus.trans_dist::ReadExResp 1149637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 440478 # Transaction distribution +system.membus.trans_dist::UpgradeResp 38309 # Transaction distribution +system.membus.trans_dist::ReadExReq 1154179 # Transaction distribution +system.membus.trans_dist::ReadExResp 1154179 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 442247 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4838609 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4968261 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340944 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5309205 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4854992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4984644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5326203 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185140076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185310482 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192529234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3380 # Total snoops (count) -system.membus.snoop_fanout::samples 3460550 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186025772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186196178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7238272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 193434450 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3077 # Total snoops (count) +system.membus.snoop_fanout::samples 3470793 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3460550 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3470793 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3460550 # Request fanout histogram -system.membus.reqLayer0.occupancy 102447500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3470793 # Request fanout histogram +system.membus.reqLayer0.occupancy 102553500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5490500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5511000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9255992894 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9297161713 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8767241103 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8798501817 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228448107 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227863618 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 225315f7c..3c5f4dcb0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.331518 # Number of seconds simulated -sim_ticks 51331518104000 # Number of ticks simulated -final_tick 51331518104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.331535 # Number of seconds simulated +sim_ticks 51331535316000 # Number of ticks simulated +final_tick 51331535316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55750 # Simulator instruction rate (inst/s) -host_op_rate 65505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3383587938 # Simulator tick rate (ticks/s) -host_mem_usage 679676 # Number of bytes of host memory used -host_seconds 15170.74 # Real time elapsed on the host -sim_insts 845761974 # Number of instructions simulated -sim_ops 993759083 # Number of ops (including micro ops) simulated +host_inst_rate 76705 # Simulator instruction rate (inst/s) +host_op_rate 90129 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4658243300 # Simulator tick rate (ticks/s) +host_mem_usage 731992 # Number of bytes of host memory used +host_seconds 11019.51 # Real time elapsed on the host +sim_insts 845255961 # Number of instructions simulated +sim_ops 993175006 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 196736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5673888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 72271240 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441728 # Number of bytes read from this memory -system.physmem.bytes_read::total 78788712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5673888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5673888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67330112 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 205184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 203136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5579360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 71974536 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439872 # Number of bytes read from this memory +system.physmem.bytes_read::total 78402088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5579360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5579360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67218688 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67350692 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104607 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1129251 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6902 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1247039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1052033 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67239268 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 103130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1124615 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1240998 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050292 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1054606 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1407931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1311672 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1052865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1402150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1527367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1309501 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1312073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1311672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1408332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2846972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1247039 # Number of read requests accepted -system.physmem.writeReqs 1054606 # Number of write requests accepted -system.physmem.readBursts 1247039 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1054606 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79759552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50944 # Total number of bytes read from write queue -system.physmem.bytesWritten 67349568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78788712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67350692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 796 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1309902 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1309501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1402551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2837269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1240998 # Number of read requests accepted +system.physmem.writeReqs 1052865 # Number of write requests accepted +system.physmem.readBursts 1240998 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1052865 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79374080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49792 # Total number of bytes read from write queue +system.physmem.bytesWritten 67238272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78402088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67239268 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 778 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 141264 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74145 # Per bank write bursts -system.physmem.perBankRdBursts::1 81438 # Per bank write bursts -system.physmem.perBankRdBursts::2 79571 # Per bank write bursts -system.physmem.perBankRdBursts::3 74681 # Per bank write bursts -system.physmem.perBankRdBursts::4 75850 # Per bank write bursts -system.physmem.perBankRdBursts::5 80076 # Per bank write bursts -system.physmem.perBankRdBursts::6 74234 # Per bank write bursts -system.physmem.perBankRdBursts::7 74770 # Per bank write bursts -system.physmem.perBankRdBursts::8 71012 # Per bank write bursts -system.physmem.perBankRdBursts::9 102127 # Per bank write bursts -system.physmem.perBankRdBursts::10 78424 # Per bank write bursts -system.physmem.perBankRdBursts::11 78933 # Per bank write bursts -system.physmem.perBankRdBursts::12 75355 # Per bank write bursts -system.physmem.perBankRdBursts::13 78384 # Per bank write bursts -system.physmem.perBankRdBursts::14 73014 # Per bank write bursts -system.physmem.perBankRdBursts::15 74229 # Per bank write bursts -system.physmem.perBankWrBursts::0 61794 # Per bank write bursts -system.physmem.perBankWrBursts::1 67391 # Per bank write bursts -system.physmem.perBankWrBursts::2 68136 # Per bank write bursts -system.physmem.perBankWrBursts::3 64875 # Per bank write bursts -system.physmem.perBankWrBursts::4 65862 # Per bank write bursts -system.physmem.perBankWrBursts::5 67755 # Per bank write bursts -system.physmem.perBankWrBursts::6 63835 # Per bank write bursts -system.physmem.perBankWrBursts::7 65687 # Per bank write bursts -system.physmem.perBankWrBursts::8 61691 # Per bank write bursts -system.physmem.perBankWrBursts::9 69909 # Per bank write bursts -system.physmem.perBankWrBursts::10 65651 # Per bank write bursts -system.physmem.perBankWrBursts::11 67939 # Per bank write bursts -system.physmem.perBankWrBursts::12 65356 # Per bank write bursts -system.physmem.perBankWrBursts::13 67578 # Per bank write bursts -system.physmem.perBankWrBursts::14 64108 # Per bank write bursts -system.physmem.perBankWrBursts::15 64770 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 323831 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 73630 # Per bank write bursts +system.physmem.perBankRdBursts::1 80699 # Per bank write bursts +system.physmem.perBankRdBursts::2 78276 # Per bank write bursts +system.physmem.perBankRdBursts::3 74217 # Per bank write bursts +system.physmem.perBankRdBursts::4 73666 # Per bank write bursts +system.physmem.perBankRdBursts::5 79970 # Per bank write bursts +system.physmem.perBankRdBursts::6 75195 # Per bank write bursts +system.physmem.perBankRdBursts::7 74032 # Per bank write bursts +system.physmem.perBankRdBursts::8 71713 # Per bank write bursts +system.physmem.perBankRdBursts::9 100993 # Per bank write bursts +system.physmem.perBankRdBursts::10 77049 # Per bank write bursts +system.physmem.perBankRdBursts::11 78387 # Per bank write bursts +system.physmem.perBankRdBursts::12 77207 # Per bank write bursts +system.physmem.perBankRdBursts::13 77888 # Per bank write bursts +system.physmem.perBankRdBursts::14 72930 # Per bank write bursts +system.physmem.perBankRdBursts::15 74368 # Per bank write bursts +system.physmem.perBankWrBursts::0 61890 # Per bank write bursts +system.physmem.perBankWrBursts::1 67926 # Per bank write bursts +system.physmem.perBankWrBursts::2 67010 # Per bank write bursts +system.physmem.perBankWrBursts::3 65080 # Per bank write bursts +system.physmem.perBankWrBursts::4 64889 # Per bank write bursts +system.physmem.perBankWrBursts::5 68021 # Per bank write bursts +system.physmem.perBankWrBursts::6 64968 # Per bank write bursts +system.physmem.perBankWrBursts::7 65143 # Per bank write bursts +system.physmem.perBankWrBursts::8 62358 # Per bank write bursts +system.physmem.perBankWrBursts::9 69100 # Per bank write bursts +system.physmem.perBankWrBursts::10 64674 # Per bank write bursts +system.physmem.perBankWrBursts::11 67475 # Per bank write bursts +system.physmem.perBankWrBursts::12 66848 # Per bank write bursts +system.physmem.perBankWrBursts::13 67005 # Per bank write bursts +system.physmem.perBankWrBursts::14 63727 # Per bank write bursts +system.physmem.perBankWrBursts::15 64484 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 51331516800500 # Total gap between requests +system.physmem.numWrRetry 26 # Number of times write queue was full causing retry +system.physmem.totGap 51331533904500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1225754 # Read request sizes (log2) +system.physmem.readPktSize::6 1219713 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1052033 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 635607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 328525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 149631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050292 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 631662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 326376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 149637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,120 +159,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 31214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 65872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 66221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 71514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 66478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 79594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 84129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 64906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 476504 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.725081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.620621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.470597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186131 39.06% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 111955 23.50% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45179 9.48% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23084 4.84% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18337 3.85% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11525 2.42% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10900 2.29% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8098 1.70% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61295 12.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 476504 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59915 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.799683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 269.572248 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 59912 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 11849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 65206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 65786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 66222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 66143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 84167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 64432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 475699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.203229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.287854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.241632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186276 39.16% 39.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 111535 23.45% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45072 9.47% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23389 4.92% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18072 3.80% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11535 2.42% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10579 2.22% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8108 1.70% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61133 12.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 475699 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.735663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 269.812069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 59807 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59915 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59915 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.563832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.981523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.290123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 57069 95.25% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 858 1.43% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 58 0.10% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 312 0.52% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.06% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 354 0.59% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 211 0.35% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.04% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 62 0.10% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 123 0.21% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 28 0.05% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 35 0.06% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 500 0.83% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 31 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 125 0.21% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59810 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.565591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.987331 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.225331 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56970 95.25% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 839 1.40% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 56 0.09% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 337 0.56% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 42 0.07% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 348 0.58% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 200 0.33% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 22 0.04% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.11% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.21% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.05% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 506 0.85% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 125 0.21% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 19 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59915 # Writes before turning the bus around for reads -system.physmem.totQLat 31917471814 # Total ticks spent queuing -system.physmem.totMemAccLat 55284528064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6231215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25610.95 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59810 # Writes before turning the bus around for reads +system.physmem.totQLat 31819415784 # Total ticks spent queuing +system.physmem.totMemAccLat 55073540784 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6201100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25656.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44360.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44406.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s @@ -281,56 +281,56 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.76 # Average write queue length when enqueuing -system.physmem.readRowHits 1024444 # Number of row buffer hits during reads -system.physmem.writeRowHits 797630 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing +system.physmem.readRowHits 1019502 # Number of row buffer hits during reads +system.physmem.writeRowHits 795615 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 22302099.93 # Average gap between requests -system.physmem.pageHitRate 79.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1809644760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 987405375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4795167000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3404170800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235982378375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29714714061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34314417854910 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.486362 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49432942986454 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714072100000 # Time in different power states +system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes +system.physmem.avgGap 22377767.94 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1796611320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 980293875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4755496200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3401526960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352726044720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1234173509595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716310123250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34314143605920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.480817 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49435613390416 # Time in different power states +system.physmem_0.memoryStateTime::REF 1714072620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184500143546 # Time in different power states +system.physmem_0.memoryStateTime::ACT 181848672584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1792725480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 978173625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4925481600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3414972960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1238461921980 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712539014500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34314837317745 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494534 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429295042072 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714072100000 # Time in different power states +system.physmem_1.actEnergy 1799673120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 981964500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4918173000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3406348080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352726044720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1238619690855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712409964250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34314861858525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494809 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49429083175074 # Time in different power states +system.physmem_1.memoryStateTime::REF 1714072620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 188150328928 # Time in different power states +system.physmem_1.memoryStateTime::ACT 188374993676 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). @@ -339,15 +339,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 223690256 # Number of BP lookups -system.cpu.branchPred.condPredicted 149470273 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12181359 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157723580 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103180902 # Number of BTB hits +system.cpu.branchPred.lookups 223536271 # Number of BP lookups +system.cpu.branchPred.condPredicted 149385948 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12169974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157736918 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103109650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.418818 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30739943 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 342702 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.368115 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30707782 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 342742 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,45 +378,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 196399 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 196399 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 196399 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 196399 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 196399 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples -1585443796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 -1585443796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total -1585443796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 153599 91.92% 91.92% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 13493 8.08% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 167092 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 196399 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 196595 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 196595 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 196595 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 196595 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 196595 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 153567 91.80% 91.80% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 13723 8.20% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 167290 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 196595 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 196399 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 167092 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 196595 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 167290 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 167092 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 363491 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 167290 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 363885 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159160853 # DTB read hits -system.cpu.checker.dtb.read_misses 146855 # DTB read misses -system.cpu.checker.dtb.write_hits 144325246 # DTB write hits -system.cpu.checker.dtb.write_misses 49544 # DTB write misses +system.cpu.checker.dtb.read_hits 159060610 # DTB read hits +system.cpu.checker.dtb.read_misses 146851 # DTB read misses +system.cpu.checker.dtb.write_hits 144228364 # DTB write hits +system.cpu.checker.dtb.write_misses 49744 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_mva_asid 78296 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71588 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 71608 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 6477 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 6498 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 18958 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159307708 # DTB read accesses -system.cpu.checker.dtb.write_accesses 144374790 # DTB write accesses +system.cpu.checker.dtb.perms_faults 18956 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 159207461 # DTB read accesses +system.cpu.checker.dtb.write_accesses 144278108 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 303486099 # DTB hits -system.cpu.checker.dtb.misses 196399 # DTB misses -system.cpu.checker.dtb.accesses 303682498 # DTB accesses +system.cpu.checker.dtb.hits 303288974 # DTB hits +system.cpu.checker.dtb.misses 196595 # DTB misses +system.cpu.checker.dtb.accesses 303485569 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,46 +446,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 119834 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119834 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119834 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119834 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples -1586395296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 -1586395296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total -1586395296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107995 98.82% 98.82% # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 119842 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 119842 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 119842 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 119842 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 119842 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108003 98.82% 98.82% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.18% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109281 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109289 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119834 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119834 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119842 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119842 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109281 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109281 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 229115 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 846167011 # ITB inst hits -system.cpu.checker.itb.inst_misses 119834 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109289 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109289 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 229131 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 845660985 # ITB inst hits +system.cpu.checker.itb.inst_misses 119842 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_mva_asid 78296 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51635 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 51575 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 846286845 # ITB inst accesses -system.cpu.checker.itb.hits 846167011 # DTB hits -system.cpu.checker.itb.misses 119834 # DTB misses -system.cpu.checker.itb.accesses 846286845 # DTB accesses -system.cpu.checker.numCycles 994327079 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 845780827 # ITB inst accesses +system.cpu.checker.itb.hits 845660985 # DTB hits +system.cpu.checker.itb.misses 119842 # DTB misses +system.cpu.checker.itb.accesses 845780827 # DTB accesses +system.cpu.checker.numCycles 993742997 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -517,87 +517,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 934978 # Table walker walks requested -system.cpu.dtb.walker.walksLong 934978 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15042 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154863 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 425141 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 509837 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2238.847906 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 506434 99.33% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1917 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 986 0.19% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 153 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 25 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 51 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 509837 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 473320 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 462482 97.71% 97.71% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7672 1.62% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2249 0.48% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 179 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 532 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 62 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 112 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 23 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 473320 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 784047304876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.724244 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519446 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 781857637876 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1171824000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 476098500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 199009000 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 143211000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 120940000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 26747000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 49238000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2599500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 784047304876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 154864 91.15% 91.15% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15042 8.85% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 169906 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 934978 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 935593 # Table walker walks requested +system.cpu.dtb.walker.walksLong 935593 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15313 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154778 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 425408 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 510185 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2222.203710 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 506821 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1912 0.37% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 970 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 202 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 19 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 50 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 510185 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 473757 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 462892 97.71% 97.71% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7688 1.62% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2250 0.47% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 174 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 494 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 87 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 117 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 41 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 473757 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 784064516876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722483 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520538 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 781865994376 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1176082000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 477234000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 199500000 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 146109500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 120981500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 26256500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 49725000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2626500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 784064516876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 154779 91.00% 91.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15313 9.00% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 170092 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 935593 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 934978 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169906 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 935593 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 170092 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169906 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1104884 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 170092 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1105685 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168982671 # DTB read hits -system.cpu.dtb.read_misses 669792 # DTB read misses -system.cpu.dtb.write_hits 147065605 # DTB write hits -system.cpu.dtb.write_misses 265186 # DTB write misses +system.cpu.dtb.read_hits 168870430 # DTB read hits +system.cpu.dtb.read_misses 669785 # DTB read misses +system.cpu.dtb.write_hits 146966916 # DTB write hits +system.cpu.dtb.write_misses 265808 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 78296 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71824 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 71844 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 98 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9312 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9429 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69742 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 169652463 # DTB read accesses -system.cpu.dtb.write_accesses 147330791 # DTB write accesses +system.cpu.dtb.perms_faults 69613 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169540215 # DTB read accesses +system.cpu.dtb.write_accesses 147232724 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316048276 # DTB hits -system.cpu.dtb.misses 934978 # DTB misses -system.cpu.dtb.accesses 316983254 # DTB accesses +system.cpu.dtb.hits 315837346 # DTB hits +system.cpu.dtb.misses 935593 # DTB misses +system.cpu.dtb.accesses 316772939 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -627,180 +625,177 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161206 # Table walker walks requested -system.cpu.itb.walker.walksLong 161206 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1436 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 121549 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17620 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 143586 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1244.532893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9274.227664 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 142628 99.33% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 542 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 55 0.04% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 79 0.06% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 218 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 29 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161130 # Table walker walks requested +system.cpu.itb.walker.walksLong 161130 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1443 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121427 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17608 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143522 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1275.602347 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9467.048086 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142512 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 586 0.41% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 51 0.04% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 83 0.06% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 223 0.16% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 32 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 14 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 143586 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 140605 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28864.162014 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 137806 98.01% 98.01% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 710 0.50% 98.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1778 1.26% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 108 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 117 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 38 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 35 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 140605 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 663785102088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.942542 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.233053 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 38191035356 5.75% 5.75% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 625543374232 94.24% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 49878500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 812000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 663785102088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 121549 98.83% 98.83% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1436 1.17% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122985 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143522 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140478 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29089.590541 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137385 97.80% 97.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 891 0.63% 98.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1925 1.37% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 93 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 119 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140478 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 668097269884 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944108 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230056 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37393446856 5.60% 5.60% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 630652469528 94.40% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 50695000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 657500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 668097269884 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121427 98.83% 98.83% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1443 1.17% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 122870 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161206 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161130 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161130 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122985 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122985 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 284191 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 355626065 # ITB inst hits -system.cpu.itb.inst_misses 161206 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122870 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 122870 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284000 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 355391745 # ITB inst hits +system.cpu.itb.inst_misses 161130 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 78296 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52940 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52871 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 369021 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369048 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 355787271 # ITB inst accesses -system.cpu.itb.hits 355626065 # DTB hits -system.cpu.itb.misses 161206 # DTB misses -system.cpu.itb.accesses 355787271 # DTB accesses -system.cpu.numCycles 1638586091 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 355552875 # ITB inst accesses +system.cpu.itb.hits 355391745 # DTB hits +system.cpu.itb.misses 161130 # DTB misses +system.cpu.itb.accesses 355552875 # DTB accesses +system.cpu.numCycles 1639149006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 642614268 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 998103903 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223690256 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133920845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 910005464 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26014386 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3801464 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9302327 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1031206 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 853 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 355240310 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6091194 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48629 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1579791741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.146164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 642133876 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 997446842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 223536271 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133817432 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 910640256 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 25987402 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3814067 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27748 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9296817 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1023598 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 983 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 355005878 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6082209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48751 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1579931046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.739715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145918 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1024362050 64.84% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213190505 13.49% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70458696 4.46% 82.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 271780490 17.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1024858413 64.87% 64.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213048750 13.48% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70422001 4.46% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 271601882 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1579791741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136514 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.609125 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 522893988 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 566130284 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 431833495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49726107 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9207867 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33553949 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3859168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1081567524 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28956293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9207867 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 567372760 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 69190624 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 368823691 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 437050453 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 128146346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1061861877 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6771880 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5087051 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 328687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 662195 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 77193560 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1009820206 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1635273516 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1255804175 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1470464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 944392449 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65427754 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26765768 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23112103 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 102007080 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173010630 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150618329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9860591 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8967243 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1027007600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27059230 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1042343751 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3268943 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60307743 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33600701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 312855 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1579791741 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.659798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917984 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1579931046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136373 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.608515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 522505611 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 567007663 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 431520293 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49702709 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9194770 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33525771 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3859042 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1080875290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28941730 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9194770 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 566963257 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68325752 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 370117398 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 436739828 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 128590041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1061188804 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6761282 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5074872 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 331009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 667465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 77645177 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20261 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1009236679 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1634390089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1255037462 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1470821 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 943893813 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65342863 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26761446 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23109655 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101993436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172887729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150512713 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9835963 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8956761 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1026341207 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27052915 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1041697414 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3264017 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60219112 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33542548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 311458 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1579931046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.659331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917837 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 934526324 59.16% 59.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 332943694 21.08% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234048480 14.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 71809082 4.55% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6444954 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19207 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 935073091 59.18% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 332737212 21.06% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 233873919 14.80% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 71794095 4.54% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6433566 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19163 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1579791741 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1579931046 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57575402 35.04% 35.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100057 0.06% 35.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57548727 35.04% 35.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100099 0.06% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available @@ -823,19 +818,19 @@ system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # at system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 764 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 757 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44168987 26.88% 62.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62424891 38.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44132085 26.87% 62.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62410380 38.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 717769712 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2531817 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122691 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 717342377 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2532202 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122567 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 8 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -857,102 +852,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121277 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121087 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172853843 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 148944351 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172736633 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 148842483 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1042343751 # Type of FU issued -system.cpu.iq.rate 0.636124 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164296841 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3829567748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1113568735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1024464263 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477278 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947290 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909965 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1205083989 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1556592 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4287735 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1041697414 # Type of FU issued +system.cpu.iq.rate 0.635511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164218799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157645 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3828331710 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1112806179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1023834597 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2476979 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 946356 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909820 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1204359624 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1556578 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4281868 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13755130 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14415 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6290239 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13732493 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 140572 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6281305 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2513645 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1546946 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2514322 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1544139 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9207867 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6935208 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9652893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1054288001 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9194770 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6870613 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9053250 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1053615244 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173010630 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150618329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22687803 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56498 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9524585 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3650015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5096410 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8746425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1031209628 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 168969861 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10209992 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 172887729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150512713 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22684457 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 56400 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8925068 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 140572 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3644333 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5090402 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8734735 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1030574997 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 168857481 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10197714 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221171 # number of nop insts executed -system.cpu.iew.exec_refs 316030804 # number of memory reference insts executed -system.cpu.iew.exec_branches 195653401 # Number of branches executed -system.cpu.iew.exec_stores 147060943 # Number of stores executed -system.cpu.iew.exec_rate 0.629329 # Inst execution rate -system.cpu.iew.wb_sent 1026179606 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1025374228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 436457494 # num instructions producing a value -system.cpu.iew.wb_consumers 705894723 # num instructions consuming a value +system.cpu.iew.exec_nop 221122 # number of nop insts executed +system.cpu.iew.exec_refs 315819616 # number of memory reference insts executed +system.cpu.iew.exec_branches 195518777 # Number of branches executed +system.cpu.iew.exec_stores 146962135 # Number of stores executed +system.cpu.iew.exec_rate 0.628726 # Inst execution rate +system.cpu.iew.wb_sent 1025549780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1024744417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 436186320 # num instructions producing a value +system.cpu.iew.wb_consumers 705504935 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.625768 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618304 # average fanout of values written-back +system.cpu.iew.wb_rate 0.625169 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618261 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51232529 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26746375 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8382033 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1567845308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.633837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.270098 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51156578 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26741457 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8371043 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1568002280 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.633402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1057713558 67.46% 67.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 286814809 18.29% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120141410 7.66% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36433500 2.32% 95.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28325160 1.81% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13966043 0.89% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8603569 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4169387 0.27% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11677872 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1058124948 67.48% 67.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 286691231 18.28% 85.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120053535 7.66% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36420041 2.32% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28336916 1.81% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13959603 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8598360 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4160425 0.27% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11657221 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1567845308 # Number of insts commited each cycle -system.cpu.commit.committedInsts 845761974 # Number of instructions committed -system.cpu.commit.committedOps 993759083 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1568002280 # Number of insts commited each cycle +system.cpu.commit.committedInsts 845255961 # Number of instructions committed +system.cpu.commit.committedOps 993175006 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 303583589 # Number of memory references committed -system.cpu.commit.loads 159255499 # Number of loads committed -system.cpu.commit.membars 6904959 # Number of memory barriers committed -system.cpu.commit.branches 188760643 # Number of branches committed -system.cpu.commit.fp_insts 896514 # Number of committed floating point instructions. -system.cpu.commit.int_insts 913055926 # Number of committed integer instructions. -system.cpu.commit.function_calls 25211674 # Number of function calls committed. +system.cpu.commit.refs 303386643 # Number of memory references committed +system.cpu.commit.loads 159155235 # Number of loads committed +system.cpu.commit.membars 6901293 # Number of memory barriers committed +system.cpu.commit.branches 188640484 # Number of branches committed +system.cpu.commit.fp_insts 896738 # Number of committed floating point instructions. +system.cpu.commit.int_insts 912506063 # Number of committed integer instructions. +system.cpu.commit.function_calls 25186659 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 687818920 69.21% 69.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2146460 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98075 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 687431731 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2146648 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 97945 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -979,531 +974,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159255499 16.03% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144328090 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159155235 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144231408 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 993759083 # Class of committed instruction -system.cpu.commit.bw_lim_events 11677872 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2593635375 # The number of ROB reads -system.cpu.rob.rob_writes 2101836328 # The number of ROB writes -system.cpu.timesIdled 8111566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58794350 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101024450248 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 845761974 # Number of Instructions Simulated -system.cpu.committedOps 993759083 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.937408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.937408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.516154 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.516154 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1220647692 # number of integer regfile reads -system.cpu.int_regfile_writes 729132737 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462075 # number of floating regfile reads -system.cpu.fp_regfile_writes 783592 # number of floating regfile writes -system.cpu.cc_regfile_reads 224479860 # number of cc regfile reads -system.cpu.cc_regfile_writes 225129726 # number of cc regfile writes -system.cpu.misc_regfile_reads 2563991678 # number of misc regfile reads -system.cpu.misc_regfile_writes 26780868 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9656863 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972805 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 282353083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9657375 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.237042 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972805 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 993175006 # Class of committed instruction +system.cpu.commit.bw_lim_events 11657221 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2593153041 # The number of ROB reads +system.cpu.rob.rob_writes 2100498051 # The number of ROB writes +system.cpu.timesIdled 8123602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59217960 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101023921760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 845255961 # Number of Instructions Simulated +system.cpu.committedOps 993175006 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.939234 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.939234 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515668 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515668 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1219925781 # number of integer regfile reads +system.cpu.int_regfile_writes 728690577 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462315 # number of floating regfile reads +system.cpu.fp_regfile_writes 782072 # number of floating regfile writes +system.cpu.cc_regfile_reads 224390859 # number of cc regfile reads +system.cpu.cc_regfile_writes 225039549 # number of cc regfile writes +system.cpu.misc_regfile_reads 2563491272 # number of misc regfile reads +system.cpu.misc_regfile_writes 26777143 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9646522 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 282175483 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9647034 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.249973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233161168 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233161168 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146769345 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146769345 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127879890 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127879890 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 376551 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 376551 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324490 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324490 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3281849 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3281849 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3677222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3677222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 274649235 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 274649235 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 275025786 # number of overall hits -system.cpu.dcache.overall_hits::total 275025786 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9521174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9521174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11203473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11203473 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1164152 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1164152 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1231188 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1231188 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446606 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446606 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1232341715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1232341715 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146679057 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146679057 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127793945 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127793945 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377283 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377283 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324111 # number of WriteLineReq hits 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# average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17454.269137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38894.088562 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38894.088562 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72497.431046 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72497.431046 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15322.830414 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15322.830414 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55300 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55300 # average StoreCondReq miss latency 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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19871.354660 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19871.354660 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71599.791887 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71599.791887 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14039.246564 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14039.246564 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22607.621836 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22607.621836 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22223.712273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22223.712273 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173081.878378 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173081.878378 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173214.297454 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173214.297454 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173148.105605 # average overall mshr uncacheable latency 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latency +system.cpu.icache.overall_avg_miss_latency::total 13513.184590 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 22549 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1385 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1395 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.331408 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.164158 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed 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128827.977905 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50050277 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25391485 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3463 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2168 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2168 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 49994853 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25364266 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3498 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2149 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2149 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1617253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23096406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1617841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23069110 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8520965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17374022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8520195 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14980289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2361594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43251 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1956286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1956286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15001430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6485775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1330832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224168 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45043419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29192673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728958 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 76882383 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960419312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017977630 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2410856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6261232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1987069030 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1835462 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 52366647 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.013365 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.114833 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1955542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1955542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14983570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6475758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224581 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 44989806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29161893 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 76798843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918014176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017349854 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2414752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6259448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2944038230 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1831110 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27676926 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156737 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 51666749 98.66% 98.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 699898 1.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 26979426 97.48% 97.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 697500 2.52% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 52366647 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32990991996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27676926 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 47946942997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1490388 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1474889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22530796241 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22505485675 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13336103780 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13321051501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 427917846 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 427763271 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1135029759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1135810761 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40289 # Transaction distribution -system.iobus.trans_dist::ReadResp 40289 # Transaction distribution +system.iobus.trans_dist::ReadReq 40286 # Transaction distribution +system.iobus.trans_dist::ReadResp 40286 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1724,11 +1726,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353714 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1745,104 +1747,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41870500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25173000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36497500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565927033 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565751099 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 44500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147690000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115449 # number of replacements -system.iocache.tags.tagsinuse 10.422254 # Cycle average of tags in use +system.iocache.tags.replacements 115446 # number of replacements +system.iocache.tags.tagsinuse 10.422238 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103107121000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.543889 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878365 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429898 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651391 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103145499000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.543896 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878342 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221494 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429896 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039569 # Number of tag accesses -system.iocache.tags.data_accesses 1039569 # Number of data accesses +system.iocache.tags.tag_accesses 1039542 # Number of tag accesses +system.iocache.tags.data_accesses 1039542 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8801 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8838 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8804 # number of demand (read+write) misses -system.iocache.demand_misses::total 8844 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8801 # number of demand (read+write) misses +system.iocache.demand_misses::total 8841 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8804 # number of overall misses -system.iocache.overall_misses::total 8844 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5106000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1685439007 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1690545007 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8801 # number of overall misses +system.iocache.overall_misses::total 8841 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1693888006 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1698957506 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13827154026 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13827154026 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5457000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1685439007 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1690896007 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5457000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1685439007 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1690896007 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13866022593 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13866022593 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1693888006 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1699308506 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1693888006 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1699308506 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8804 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8841 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8801 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8804 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8844 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8801 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8841 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8804 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8844 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8801 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8841 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1856,55 +1858,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 138000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191440.141640 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191216.492139 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192233.254809 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129632.809814 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129632.809814 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 136425 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191191.316938 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 136425 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191191.316938 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34672 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192465.402341 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192207.726049 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 192465.402341 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192207.726049 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36226 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3621 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.923297 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.004419 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8804 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8801 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8838 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8804 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8801 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8841 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8804 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3256000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245239007 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1248495007 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8801 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8841 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1253838006 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1257057506 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8493954026 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8493954026 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3457000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1245239007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1248696007 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3457000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1245239007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1248696007 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8532822593 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8532822593 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1253838006 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1257258506 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1253838006 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1257258506 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1918,73 +1920,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141440.141640 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141216.492139 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79632.809814 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79632.809814 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142207.726049 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142207.726049 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54973 # Transaction distribution -system.membus.trans_dist::ReadResp 402008 # Transaction distribution +system.membus.trans_dist::ReadReq 54972 # Transaction distribution +system.membus.trans_dist::ReadResp 398274 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1052033 # Transaction distribution -system.membus.trans_dist::CleanEvict 186512 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34605 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1050292 # Transaction distribution +system.membus.trans_dist::CleanEvict 182485 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34687 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34608 # Transaction distribution -system.membus.trans_dist::ReadExReq 881317 # Transaction distribution -system.membus.trans_dist::ReadExResp 881317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347035 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34690 # Transaction distribution +system.membus.trans_dist::ReadExReq 879035 # Transaction distribution +system.membus.trans_dist::ReadExResp 879035 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 343302 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3680509 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3810131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4152525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3662907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3792527 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4134863 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138873356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 139043342 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146309390 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2606 # Total snoops (count) -system.membus.snoop_fanout::samples 2698981 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138377164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138547134 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145811326 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2632 # Total snoops (count) +system.membus.snoop_fanout::samples 2687314 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2698981 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2687314 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2698981 # Request fanout histogram -system.membus.reqLayer0.occupancy 104149000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2687314 # Request fanout histogram +system.membus.reqLayer0.occupancy 103976500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5470500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5452000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7144084722 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7124848125 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6645299856 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6613283400 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228305891 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227684837 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index a0d86b26c..b4e7404dd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.395178 # Number of seconds simulated -sim_ticks 47395178174000 # Number of ticks simulated -final_tick 47395178174000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.314506 # Number of seconds simulated +sim_ticks 47314506373000 # Number of ticks simulated +final_tick 47314506373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85380 # Simulator instruction rate (inst/s) -host_op_rate 100389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4378207332 # Simulator tick rate (ticks/s) -host_mem_usage 733200 # Number of bytes of host memory used -host_seconds 10825.25 # Real time elapsed on the host -sim_insts 924259255 # Number of instructions simulated -sim_ops 1086731985 # Number of ops (including micro ops) simulated +host_inst_rate 99848 # Simulator instruction rate (inst/s) +host_op_rate 117399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5125940674 # Simulator tick rate (ticks/s) +host_mem_usage 814164 # Number of bytes of host memory used +host_seconds 9230.40 # Real time elapsed on the host +sim_insts 921635123 # Number of instructions simulated +sim_ops 1083644532 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 172224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 5051936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 46751112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21558016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 154688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2266144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 13742800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14572608 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 453056 # Number of bytes read from this memory -system.physmem.bytes_read::total 105025112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 5051936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2266144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7318080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87763520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 141824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 130048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4236960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43669256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 19384064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 193856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 178880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3171232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 16700240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15629760 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 443968 # Number of bytes read from this memory +system.physmem.bytes_read::total 103880088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4236960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3171232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7408192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 86326016 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 87784104 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2691 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 94889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 730499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 336844 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 35452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 214744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 227697 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 7079 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1657039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1371305 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 86346600 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82155 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 682345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 302876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 49594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 260954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 244215 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6937 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1639148 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1348844 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1373879 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 106592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 986411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 454857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 289962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 307470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2215945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 106592 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 154406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1851739 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1351418 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 922957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 409685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 67025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 352962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 330338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2195523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 67025 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1824515 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1851739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 106592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 986845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 454857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 289962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 307470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4068119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1657039 # Number of read requests accepted -system.physmem.writeReqs 1373879 # Number of write requests accepted -system.physmem.readBursts 1657039 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1373879 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106020736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 29760 # Total number of bytes read from write queue -system.physmem.bytesWritten 87783296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 105025112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87784104 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 465 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1824950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1824515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 923392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 409685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3781 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 67025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 330338 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4020473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1639148 # Number of read requests accepted +system.physmem.writeReqs 1351418 # Number of write requests accepted +system.physmem.readBursts 1639148 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1351418 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104871744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue +system.physmem.bytesWritten 86344960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103880088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 86346600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 224488 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 100246 # Per bank write bursts -system.physmem.perBankRdBursts::1 102501 # Per bank write bursts -system.physmem.perBankRdBursts::2 99063 # Per bank write bursts -system.physmem.perBankRdBursts::3 111016 # Per bank write bursts -system.physmem.perBankRdBursts::4 103342 # Per bank write bursts -system.physmem.perBankRdBursts::5 111704 # Per bank write bursts -system.physmem.perBankRdBursts::6 101938 # Per bank write bursts -system.physmem.perBankRdBursts::7 100431 # Per bank write bursts -system.physmem.perBankRdBursts::8 95106 # Per bank write bursts -system.physmem.perBankRdBursts::9 125245 # Per bank write bursts -system.physmem.perBankRdBursts::10 101573 # Per bank write bursts -system.physmem.perBankRdBursts::11 106068 # Per bank write bursts -system.physmem.perBankRdBursts::12 95582 # Per bank write bursts -system.physmem.perBankRdBursts::13 100418 # Per bank write bursts -system.physmem.perBankRdBursts::14 101028 # Per bank write bursts -system.physmem.perBankRdBursts::15 101313 # Per bank write bursts -system.physmem.perBankWrBursts::0 83566 # Per bank write bursts -system.physmem.perBankWrBursts::1 87156 # Per bank write bursts -system.physmem.perBankWrBursts::2 83944 # Per bank write bursts -system.physmem.perBankWrBursts::3 90509 # Per bank write bursts -system.physmem.perBankWrBursts::4 85224 # Per bank write bursts -system.physmem.perBankWrBursts::5 91500 # Per bank write bursts -system.physmem.perBankWrBursts::6 84276 # Per bank write bursts -system.physmem.perBankWrBursts::7 85215 # Per bank write bursts -system.physmem.perBankWrBursts::8 82233 # Per bank write bursts -system.physmem.perBankWrBursts::9 88133 # Per bank write bursts -system.physmem.perBankWrBursts::10 85317 # Per bank write bursts -system.physmem.perBankWrBursts::11 88722 # Per bank write bursts -system.physmem.perBankWrBursts::12 80882 # Per bank write bursts -system.physmem.perBankWrBursts::13 85628 # Per bank write bursts -system.physmem.perBankWrBursts::14 84824 # Per bank write bursts -system.physmem.perBankWrBursts::15 84485 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 532498 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 106578 # Per bank write bursts +system.physmem.perBankRdBursts::1 104344 # Per bank write bursts +system.physmem.perBankRdBursts::2 100892 # Per bank write bursts +system.physmem.perBankRdBursts::3 102125 # Per bank write bursts +system.physmem.perBankRdBursts::4 100013 # Per bank write bursts +system.physmem.perBankRdBursts::5 109287 # Per bank write bursts +system.physmem.perBankRdBursts::6 101103 # Per bank write bursts +system.physmem.perBankRdBursts::7 99682 # Per bank write bursts +system.physmem.perBankRdBursts::8 97394 # Per bank write bursts +system.physmem.perBankRdBursts::9 128253 # Per bank write bursts +system.physmem.perBankRdBursts::10 98226 # Per bank write bursts +system.physmem.perBankRdBursts::11 99141 # Per bank write bursts +system.physmem.perBankRdBursts::12 97088 # Per bank write bursts +system.physmem.perBankRdBursts::13 102696 # Per bank write bursts +system.physmem.perBankRdBursts::14 95500 # Per bank write bursts +system.physmem.perBankRdBursts::15 96299 # Per bank write bursts +system.physmem.perBankWrBursts::0 86551 # Per bank write bursts +system.physmem.perBankWrBursts::1 88756 # Per bank write bursts +system.physmem.perBankWrBursts::2 83871 # Per bank write bursts +system.physmem.perBankWrBursts::3 85066 # Per bank write bursts +system.physmem.perBankWrBursts::4 83226 # Per bank write bursts +system.physmem.perBankWrBursts::5 90269 # Per bank write bursts +system.physmem.perBankWrBursts::6 84251 # Per bank write bursts +system.physmem.perBankWrBursts::7 84163 # Per bank write bursts +system.physmem.perBankWrBursts::8 81439 # Per bank write bursts +system.physmem.perBankWrBursts::9 87752 # Per bank write bursts +system.physmem.perBankWrBursts::10 80936 # Per bank write bursts +system.physmem.perBankWrBursts::11 83767 # Per bank write bursts +system.physmem.perBankWrBursts::12 81736 # Per bank write bursts +system.physmem.perBankWrBursts::13 86099 # Per bank write bursts +system.physmem.perBankWrBursts::14 79882 # Per bank write bursts +system.physmem.perBankWrBursts::15 81376 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 47395176675500 # Total gap between requests +system.physmem.numWrRetry 31 # Number of times write queue was full causing retry +system.physmem.totGap 47314504873500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1635681 # Read request sizes (log2) +system.physmem.readPktSize::6 1617790 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1371305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 618737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 421038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 166212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 166706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 103650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 63464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 8186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4495 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1348844 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 620628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 413232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 168696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 160410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 100263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 61902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 33280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31024 # What read queue length does an incoming req see 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incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,178 +188,183 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 20142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 34959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 52927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 71450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 89148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 92391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 97124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 100685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 113079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 104553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 98049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 87257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1046566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 185.180531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 114.222366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.012748 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 630659 60.26% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 204416 19.53% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 66292 6.33% 86.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36110 3.45% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25913 2.48% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 14303 1.37% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14388 1.37% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7964 0.76% 95.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46521 4.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1046566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 78027 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.230689 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 247.022438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 78024 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 21855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 78343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 84949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 88390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 97634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 95478 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::40 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 230 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1061449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.146498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.187522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.320652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 660214 62.20% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 197053 18.56% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 62946 5.93% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34930 3.29% 89.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24785 2.34% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13743 1.29% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13849 1.30% 94.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7639 0.72% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46290 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1061449 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 76381 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.453032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249.608933 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 76378 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 78027 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 78027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.578710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.107570 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.499017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 72603 93.05% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2990 3.83% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 480 0.62% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 334 0.43% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 81 0.10% 98.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 301 0.39% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 173 0.22% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 106 0.14% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 88 0.11% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 126 0.16% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.05% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 56 0.07% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 406 0.52% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 31 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 123 0.16% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 78027 # Writes before turning the bus around for reads -system.physmem.totQLat 82234419314 # Total ticks spent queuing -system.physmem.totMemAccLat 113295181814 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8282870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49641.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 76381 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 76381 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.663293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.185244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.515109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70865 92.78% 92.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3094 4.05% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 460 0.60% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 346 0.45% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 86 0.11% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 303 0.40% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 170 0.22% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 108 0.14% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 111 0.15% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 84 0.11% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 42 0.05% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 72 0.09% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 382 0.50% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 49 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 81 0.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 17 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 76381 # Writes before turning the bus around for reads +system.physmem.totQLat 70826288095 # Total ticks spent queuing +system.physmem.totMemAccLat 101550431845 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8193105000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43223.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68391.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 61973.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 1332435 # Number of row buffer hits during reads -system.physmem.writeRowHits 649185 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 47.33 # Row buffer hit rate for writes -system.physmem.avgGap 15637234.88 # Average gap between requests -system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4004169120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2184814500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6475833000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4480207200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1180796903550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27401319159750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31694883606720 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.736482 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45584100048214 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582629100000 # Time in different power states +system.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing +system.physmem.readRowHits 1314681 # Number of row buffer hits during reads +system.physmem.writeRowHits 611629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.33 # Row buffer hit rate for writes +system.physmem.avgGap 15821254.20 # Average gap between requests +system.physmem.pageHitRate 64.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4090980600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2232181875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6427387200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4446271440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1181376195975 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27352407006750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31641333353280 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.744914 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45502947755010 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579935240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 228448334286 # Time in different power states +system.physmem_0.memoryStateTime::ACT 231620211240 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3907869840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2132270250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6445397400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4407851520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1181668397355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27400554691500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31694738997465 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.733431 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45582807436264 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582629100000 # Time in different power states +system.physmem_1.actEnergy 3933573840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2146295250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6353809800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4296155760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1178540083170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27354894825000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31640518072260 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.727683 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45507092069935 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579935240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 229740006236 # Time in different power states +system.physmem_1.memoryStateTime::ACT 227478372065 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) @@ -379,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 146971248 # Number of BP lookups -system.cpu0.branchPred.condPredicted 97492286 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7372479 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 103605243 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 68020426 # Number of BTB hits +system.cpu0.branchPred.lookups 132773230 # Number of BP lookups +system.cpu0.branchPred.condPredicted 87983669 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6601963 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 93351299 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61553732 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.653459 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20148210 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 220615 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.937735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18245658 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 197691 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,88 +423,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 621589 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 621589 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13120 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97816 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 286624 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 334965 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2330.974878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 332297 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1432 0.43% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 943 0.28% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 84 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 574649 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 574649 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12370 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88781 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 269295 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 305354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2428.535405 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 302828 99.17% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1395 0.46% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 849 0.28% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 146 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 334965 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 317874 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 314157 98.83% 98.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.26% 99.09% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2043 0.64% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 147 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 407 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 108 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 100 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 317874 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 575732613804 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.609948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.538779 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 574368413804 99.76% 99.76% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 774580000 0.13% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 276702000 0.05% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 125012500 0.02% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 99386000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 49877000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16787500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21052000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 785500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 575732613804 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 97816 88.17% 88.17% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13120 11.83% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 110936 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 621589 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 305354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 295785 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 292925 99.03% 99.03% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 638 0.22% 99.25% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1609 0.54% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 142 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 290 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 60 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 29 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 295785 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 533721818468 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.601728 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.544409 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 532429522968 99.76% 99.76% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 722596500 0.14% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 256398500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 121663500 0.02% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 95265000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 53651000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 19676500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 22307000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 728500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 533721818468 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88781 87.77% 87.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 12370 12.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101151 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 574649 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 621589 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110936 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 574649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101151 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110936 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 732525 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101151 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 675800 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106854280 # DTB read hits -system.cpu0.dtb.read_misses 451291 # DTB read misses -system.cpu0.dtb.write_hits 87452638 # DTB write hits -system.cpu0.dtb.write_misses 170298 # DTB write misses +system.cpu0.dtb.read_hits 96498807 # DTB read hits +system.cpu0.dtb.read_misses 413728 # DTB read misses +system.cpu0.dtb.write_hits 78559139 # DTB write hits +system.cpu0.dtb.write_misses 160921 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41576 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 658 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7382 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38359 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 510 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7352 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40291 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 107305571 # DTB read accesses -system.cpu0.dtb.write_accesses 87622936 # DTB write accesses +system.cpu0.dtb.perms_faults 37571 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 96912535 # DTB read accesses +system.cpu0.dtb.write_accesses 78720060 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 194306918 # DTB hits -system.cpu0.dtb.misses 621589 # DTB misses -system.cpu0.dtb.accesses 194928507 # DTB accesses +system.cpu0.dtb.hits 175057946 # DTB hits +system.cpu0.dtb.misses 574649 # DTB misses +system.cpu0.dtb.accesses 175632595 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -529,1172 +531,1177 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 88821 # Table walker walks requested -system.cpu0.itb.walker.walksLong 88821 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1050 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63713 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10161 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 78660 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1640.999237 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 77771 98.87% 98.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 446 0.57% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 46 0.06% 99.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 60 0.08% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 236 0.30% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 63 0.08% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 78486 # Table walker walks requested +system.cpu0.itb.walker.walksLong 78486 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 887 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55688 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9272 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 69214 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1487.228017 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11268.156243 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 68484 98.95% 98.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 441 0.64% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 33 0.05% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 145 0.21% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 56 0.08% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 78660 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 74924 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 72785 97.15% 97.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 128 0.17% 97.32% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1706 2.28% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 120 0.16% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 74924 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 438261516832 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.857100 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62664607652 14.30% 14.30% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 375564750680 85.69% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 27774000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4139500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walkWaitTime::total 69214 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 65847 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26575.804517 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 64258 97.59% 97.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 112 0.17% 97.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1232 1.87% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 99 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 79 0.12% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 65847 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 404869617088 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.839049 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.367685 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 65190904252 16.10% 16.10% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 339654890336 83.89% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 21211000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2423500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 57000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 438261516832 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 63713 98.38% 98.38% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1050 1.62% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64763 # Table walker page sizes translated +system.cpu0.itb.walker.walksPending::total 404869617088 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55688 98.43% 98.43% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 887 1.57% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56575 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88821 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88821 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78486 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78486 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64763 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64763 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 153584 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 231690538 # ITB inst hits -system.cpu0.itb.inst_misses 88821 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56575 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56575 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135061 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 209228100 # ITB inst hits +system.cpu0.itb.inst_misses 78486 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30101 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27529 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 229340 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 202656 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 231779359 # ITB inst accesses -system.cpu0.itb.hits 231690538 # DTB hits -system.cpu0.itb.misses 88821 # DTB misses -system.cpu0.itb.accesses 231779359 # DTB accesses -system.cpu0.numCycles 863793222 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 209306586 # ITB inst accesses +system.cpu0.itb.hits 209228100 # DTB hits +system.cpu0.itb.misses 78486 # DTB misses +system.cpu0.itb.accesses 209306586 # DTB accesses +system.cpu0.numCycles 789288757 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 99193613 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 650316460 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 146971248 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 88168636 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 710473999 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15870286 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2085677 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 375453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6582690 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 821108 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 973136 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 231460528 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1900058 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 29560 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 828440819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.919217 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.204961 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88186567 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 587222731 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 132773230 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 79799390 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 653950437 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14236776 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1849931 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 326899 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5945958 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 775108 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 835772 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 209027134 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1689441 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 26384 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 758989060 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.905560 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.200949 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 463819781 55.99% 55.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 141489715 17.08% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49366419 5.96% 79.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 173764904 20.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 429796828 56.63% 56.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 127839256 16.84% 73.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 44588296 5.87% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 156764680 20.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 828440819 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.170146 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.752861 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 116939951 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 422028211 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 244586455 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39268558 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5617644 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 21189817 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2362286 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 672848975 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 25418616 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5617644 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 154577177 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 70595603 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 261705373 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 245642920 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 90302102 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 654266166 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6467849 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 11101204 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 403453 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 928162 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 53323892 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11721 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 625141147 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1009026275 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 772228505 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 892399 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 562735066 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 62406074 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16247606 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14088158 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79534921 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 107241964 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 91079408 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9519471 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8265411 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 630985849 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16282634 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 634912655 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2916139 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 58420750 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 38187791 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 288602 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 828440819 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.766395 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.051588 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 758989060 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.168219 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.743990 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 104466806 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 394260374 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 219139619 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 36084867 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5037394 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19164568 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2120604 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 606612799 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 22830363 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5037394 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 138662412 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 63104555 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 247113571 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 220473798 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 84597330 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 589875332 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 5798642 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10641909 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 381250 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 853231 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 50687884 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 10092 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 564041119 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 911558490 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 696481853 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 699850 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 508008632 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 56032481 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14857922 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12905611 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 72985645 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 96647129 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 81788442 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8697028 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7422933 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 568689811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14912069 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 572654206 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2621739 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 52458189 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 34404562 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258659 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 758989060 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.754496 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.046900 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 482464203 58.24% 58.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 143786503 17.36% 75.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 123657330 14.93% 90.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 70325398 8.49% 99.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8201627 0.99% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5758 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 446419238 58.82% 58.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 130584028 17.20% 76.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 111330924 14.67% 90.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 63215854 8.33% 99.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7434312 0.98% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4704 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 828440819 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 758989060 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65751499 45.58% 45.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 72629 0.05% 45.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 24296 0.02% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 30 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.64% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37784970 26.19% 71.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40630472 28.16% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 59334745 45.62% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 61701 0.05% 45.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34211739 26.30% 71.98% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 36440950 28.02% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 434162938 68.38% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1557110 0.25% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 85116 0.01% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 3 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 85507 0.01% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 110176891 17.35% 86.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88845090 13.99% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 391815865 68.42% 68.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1438003 0.25% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 75602 0.01% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 42288 0.01% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 99488891 17.37% 86.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 79793556 13.93% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 634912655 # Type of FU issued -system.cpu0.iq.rate 0.735029 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 144263896 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227218 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2243978291 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 705234549 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 616677073 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1467869 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 599303 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 545442 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 778270494 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 906057 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2895519 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 572654206 # Type of FU issued +system.cpu0.iq.rate 0.725532 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 130064790 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227126 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2035873022 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 635743875 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 556160378 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1110977 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 443650 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 409772 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 702028683 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 690312 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2617659 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13298175 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 18246 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 145606 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6202009 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 11976787 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15696 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 128509 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5549515 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2767326 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4824800 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2485031 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4622903 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5617644 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8735359 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7907130 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 647396791 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5037394 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7963594 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7170717 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 583715188 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 107241964 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 91079408 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13794371 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 59022 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7772545 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 145606 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2195305 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3186569 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5381874 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 626447733 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106847652 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7850968 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 96647129 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 81788442 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12627210 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54569 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7047111 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 128509 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1976888 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2838838 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4815726 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 565090405 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 96493854 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6996299 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 128308 # number of nop insts executed -system.cpu0.iew.exec_refs 194298385 # number of memory reference insts executed -system.cpu0.iew.exec_branches 118240799 # Number of branches executed -system.cpu0.iew.exec_stores 87450733 # Number of stores executed -system.cpu0.iew.exec_rate 0.725229 # Inst execution rate -system.cpu0.iew.wb_sent 618051464 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 617222515 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 300479191 # num instructions producing a value -system.cpu0.iew.wb_consumers 493067457 # num instructions consuming a value +system.cpu0.iew.exec_nop 113308 # number of nop insts executed +system.cpu0.iew.exec_refs 175051410 # number of memory reference insts executed +system.cpu0.iew.exec_branches 106737211 # Number of branches executed +system.cpu0.iew.exec_stores 78557556 # Number of stores executed +system.cpu0.iew.exec_rate 0.715949 # Inst execution rate +system.cpu0.iew.wb_sent 557331942 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 556570150 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 270940614 # num instructions producing a value +system.cpu0.iew.wb_consumers 444738310 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.714549 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609408 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.705154 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609214 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50926327 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15994032 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 5054980 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 818740070 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.719212 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.525829 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 45776609 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14653410 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4520969 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 750266004 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.707940 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.517135 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 561213375 68.55% 68.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 132109065 16.14% 84.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 58113446 7.10% 91.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19548895 2.39% 94.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13854430 1.69% 95.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9447713 1.15% 97.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6268110 0.77% 97.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3880157 0.47% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14304879 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 517711139 69.00% 69.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 119807975 15.97% 84.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 52242096 6.96% 91.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 17345693 2.31% 94.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 12502849 1.67% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8569717 1.14% 97.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5628818 0.75% 97.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3480187 0.46% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 12977530 1.73% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 818740070 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 501771314 # Number of instructions committed -system.cpu0.commit.committedOps 588847718 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 750266004 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 452897446 # Number of instructions committed +system.cpu0.commit.committedOps 531143684 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 178821180 # Number of memory references committed -system.cpu0.commit.loads 93943789 # Number of loads committed -system.cpu0.commit.membars 3938709 # Number of memory barriers committed -system.cpu0.commit.branches 112215548 # Number of branches committed -system.cpu0.commit.fp_insts 531565 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 540152053 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14962116 # Number of function calls committed. +system.cpu0.commit.refs 160909268 # Number of memory references committed +system.cpu0.commit.loads 84670341 # Number of loads committed +system.cpu0.commit.membars 3612111 # Number of memory barriers committed +system.cpu0.commit.branches 101352463 # Number of branches committed +system.cpu0.commit.fp_insts 401266 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 487082373 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13540419 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 408576800 69.39% 69.39% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1307130 0.22% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 67517 0.01% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 75091 0.01% 69.63% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93943789 15.95% 85.59% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84877391 14.41% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368934944 69.46% 69.46% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1203387 0.23% 69.69% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 59505 0.01% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 36580 0.01% 69.71% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84670341 15.94% 85.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 76238927 14.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 588847718 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14304879 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1439565573 # The number of ROB reads -system.cpu0.rob.rob_writes 1289210941 # The number of ROB writes -system.cpu0.timesIdled 1140163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 35352403 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93926563172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 501771314 # Number of Instructions Simulated -system.cpu0.committedOps 588847718 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.721488 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.721488 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.580893 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.580893 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 739095549 # number of integer regfile reads -system.cpu0.int_regfile_writes 439787902 # number of integer regfile writes -system.cpu0.fp_regfile_reads 872002 # number of floating regfile reads -system.cpu0.fp_regfile_writes 484356 # number of floating regfile writes -system.cpu0.cc_regfile_reads 137161341 # number of cc regfile reads -system.cpu0.cc_regfile_writes 137881500 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1443535644 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16079939 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6407370 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.018138 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 166146345 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6407881 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.928438 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.018138 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992223 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992223 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 371124901 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 371124901 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 87218466 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 87218466 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73809320 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73809320 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228978 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 228978 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263867 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 263867 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1900288 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1900288 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1938762 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1938762 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 161027786 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 161027786 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 161256764 # number of overall hits -system.cpu0.dcache.overall_hits::total 161256764 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7088028 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7088028 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7798635 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7798635 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740346 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 740346 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 850980 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 850980 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273336 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 273336 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194663 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194663 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14886663 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14886663 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15627009 # number of overall misses -system.cpu0.dcache.overall_misses::total 15627009 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 124519522000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 124519522000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171455239141 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 171455239141 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 101116390498 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 101116390498 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4428125500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4428125500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4749567500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4749567500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4799500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4799500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 295974761141 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 295974761141 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 295974761141 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 295974761141 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 94306494 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 94306494 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81607955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81607955 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 969324 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 969324 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1114847 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1114847 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2173624 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2173624 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2133425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2133425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 175914449 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 175914449 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 176883773 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 176883773 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075159 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075159 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095562 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.095562 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763776 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763776 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763316 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763316 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.125751 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.125751 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091244 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091244 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084624 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084624 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088346 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088346 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17567.583254 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17567.583254 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21985.288341 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 21985.288341 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118823.462946 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118823.462946 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16200.301095 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16200.301095 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24398.922754 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24398.922754 # average StoreCondReq miss latency +system.cpu0.commit.op_class_0::total 531143684 # Class of committed instruction +system.cpu0.commit.bw_lim_events 12977530 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1309875410 # The number of ROB reads +system.cpu0.rob.rob_writes 1162529912 # The number of ROB writes +system.cpu0.timesIdled 987855 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30299697 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93839724027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 452897446 # Number of Instructions Simulated +system.cpu0.committedOps 531143684 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.742754 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.742754 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.573805 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.573805 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 666947650 # number of integer regfile reads +system.cpu0.int_regfile_writes 396615179 # number of integer regfile writes +system.cpu0.fp_regfile_reads 682678 # number of floating regfile reads +system.cpu0.fp_regfile_writes 298828 # number of floating regfile writes +system.cpu0.cc_regfile_reads 124079442 # number of cc regfile reads +system.cpu0.cc_regfile_writes 124706529 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1318525921 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14734262 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5881965 # number of replacements +system.cpu0.dcache.tags.tagsinuse 478.956800 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149156359 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5882471 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.356072 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.956800 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.935463 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.935463 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 506 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 334047120 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 334047120 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78452229 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78452229 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 65886147 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 65886147 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209885 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 209885 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258671 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 258671 # number of WriteLineReq hits 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+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 689122 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 689122 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 817042 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 817042 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 245228 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 245228 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193470 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 193470 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13747428 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13747428 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14436550 # number of overall misses +system.cpu0.dcache.overall_misses::total 14436550 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 110052955500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 170225463786 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91498155223 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 91498155223 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3890581500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3890581500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5535454500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5535454500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 8571500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 8571500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 280278419286 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 280278419286 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 84911513 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 84911513 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73174291 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73174291 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899007 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 899007 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1075713 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1075713 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2002276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2002276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1967058 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1967058 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 158085804 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 158085804 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 158984811 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 158984811 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076071 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.076071 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099600 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.099600 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759535 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759535 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122475 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122475 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098355 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098355 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086962 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086962 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090805 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.090805 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 31639371 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 26128725 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 779388 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 763893 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.595148 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.204692 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20387.698651 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19414.501338 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 28857818 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25701299 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 757026 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 713337 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.119983 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 36.029673 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4315919 # number of writebacks -system.cpu0.dcache.writebacks::total 4315919 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3584647 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3584647 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6264689 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6264689 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4628 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4628 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 139100 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 139100 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9849336 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9849336 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9849336 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9849336 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3503381 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3503381 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1533946 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1533946 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733362 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 733362 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 846352 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 846352 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 134236 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134236 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194661 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 194661 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5037327 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5037327 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5770689 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5770689 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33238 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66643 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56780867000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56780867000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38418617555 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38418617555 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19943250500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19943250500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1962249500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1962249500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4554969500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4554969500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4736500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4736500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95199484555 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 95199484555 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5997592500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5997592500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5944742000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5944742000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11942334500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11942334500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037149 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037149 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018797 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018797 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756571 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756571 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759164 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.759164 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061757 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061757 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028635 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028635 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032624 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032624 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5882015 # number of writebacks +system.cpu0.dcache.writebacks::total 5882015 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3286907 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3286907 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5842010 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5842010 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4476 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4476 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 122858 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 122858 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9128917 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9128917 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9128917 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9128917 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3172377 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3172377 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1446134 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1446134 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 682277 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 682277 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 812566 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 812566 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122370 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 193461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4618511 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4618511 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5300788 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5300788 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32879 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995905500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49995905500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39710234771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39710234771 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17655223500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17655223500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90433652723 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90433652723 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1780369000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1780369000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5342108500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5342108500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 8456500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 8456500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89706140271 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 89706140271 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 107361363771 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6303225000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6303225000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6238855500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6238855500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12542080500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12542080500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037361 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037361 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019763 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019763 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758923 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758923 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755374 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755374 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061115 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061115 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029215 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029215 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033341 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033341 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6757482 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.935144 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224272608 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6757994 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.186269 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit. 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ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224272608 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224272608 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224272608 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224272608 # number of overall hits -system.cpu0.icache.overall_hits::total 224272608 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7158551 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 7158551 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7158551 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 7158551 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7158551 # number of overall misses -system.cpu0.icache.overall_misses::total 7158551 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 82703845756 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 82703845756 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 82703845756 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 82703845756 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 82703845756 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 82703845756 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 231431159 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 231431159 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 231431159 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 231431159 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 231431159 # number of overall (read+write) accesses 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overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11553.154508 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13180342 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1608 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 863819 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 424004104 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 424004104 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 202641946 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 202641946 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 202641946 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 202641946 # number of demand (read+write) hits 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72002088632 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 72002088632 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 72002088632 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 208999164 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 208999164 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 208999164 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 208999164 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 208999164 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 208999164 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030417 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.030417 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030417 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.030417 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030417 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.030417 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11326.037369 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11326.037369 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11168048 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1595 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 759109 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.258222 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 114.857143 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.712048 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 113.928571 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 400520 # number of ReadReq MSHR hits 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-system.cpu0.icache.overall_mshr_miss_latency::total 74295068991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.029201 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses 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-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency +system.cpu0.icache.writebacks::writebacks 6005225 # number of writebacks +system.cpu0.icache.writebacks::total 6005225 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351442 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 351442 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 351442 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 351442 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 351442 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 351442 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6005776 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6005776 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6005776 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6005776 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6005776 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6005776 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64732998531 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 64732998531 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64732998531 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 64732998531 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64732998531 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 64732998531 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028736 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028736 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028736 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8609545 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8618519 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8045 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7993443 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8002831 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 8432 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1094401 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2903307 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16246.409963 # Cycle average of tags in use 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uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8820099500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5985704467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5985704467 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12025721467 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14805803967 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.025505 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546510 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546510 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814437 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814437 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997902 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997902 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207605 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207605 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.102860 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248180 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248180 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747342 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747342 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156510 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221153 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221153 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092567 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.246000 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.246000 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.758950 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.758950 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.152043 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219344 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.221033 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 27252548 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13981170 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2244 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 570842 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 570828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 1016473 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 12252394 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33406 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33405 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5923375 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 10861944 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1063583 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 463812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352945 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 515465 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1384026 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1310731 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6758031 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5399513 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 852147 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 844897 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20314687 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20641650 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 432749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348262 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 42737348 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 432852704 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 646893668 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1600696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4951880 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1086298948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6525445 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 34111599 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.027918 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.164740 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 24664078 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12671171 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2001831 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2001348 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 483 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 921539 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11008242 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32982 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32981 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5510686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8013020 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2592060 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1056695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 478539 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354281 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 520874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1281558 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1212477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6005776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4986753 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 818816 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 810530 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18057865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19072336 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391759 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1260604 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 38782564 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 768948880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 715383853 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1495872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4784112 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1490612717 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7046224 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20167865 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.116092 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.320411 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 33159285 97.21% 97.21% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 952300 2.79% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 17827011 88.39% 88.39% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2340371 11.60% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 483 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 34111599 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 18295414402 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 218599021 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 20167865 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 24544733928 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 212322671 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 10163463729 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9035902540 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9200637125 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8451585698 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 233049222 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 205222100 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 729789968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 663162345 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 123149965 # Number of BP lookups -system.cpu1.branchPred.condPredicted 82495484 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5956200 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 86779618 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56690061 # Number of BTB hits +system.cpu1.branchPred.lookups 136771271 # Number of BP lookups +system.cpu1.branchPred.condPredicted 91615454 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6699408 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 96252672 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62838118 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 65.326470 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16440472 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 156518 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.284544 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 18248077 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 178326 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1724,87 +1731,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 527411 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 527411 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10595 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86487 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 240409 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 287002 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2359.187392 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 284807 99.24% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1123 0.39% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 785 0.27% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 587464 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 587464 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12287 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93954 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 273243 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 314221 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2460.273184 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 311748 99.21% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1254 0.40% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 917 0.29% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 287002 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 269681 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 266977 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 731 0.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1349 0.50% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 143 0.05% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 295 0.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 94 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::851968-917503 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 269681 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 429707115240 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.574612 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.551988 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 428613446240 99.75% 99.75% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 584261000 0.14% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 233148000 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 115723000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 78401000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 45162000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15712000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 20912500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 429707115240 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86487 89.09% 89.09% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10595 10.91% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97082 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527411 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 314221 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 302969 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 299168 98.75% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 939 0.31% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1914 0.63% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.05% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 510 0.17% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 121 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 110 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 28 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 302969 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 477883045620 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.598615 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.553378 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 476579478620 99.73% 99.73% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 689019500 0.14% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 279828500 0.06% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 139297000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 94668000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 55014500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 17997000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 27375000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 352000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 15500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 477883045620 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 93955 88.43% 88.43% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 12287 11.57% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 106242 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 587464 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527411 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97082 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 587464 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106242 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97082 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 624493 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106242 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 693706 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91393564 # DTB read hits -system.cpu1.dtb.read_misses 362569 # DTB read misses -system.cpu1.dtb.write_hits 75279430 # DTB write hits -system.cpu1.dtb.write_misses 164842 # DTB write misses +system.cpu1.dtb.read_hits 101377575 # DTB read hits +system.cpu1.dtb.read_misses 401827 # DTB read misses +system.cpu1.dtb.write_hits 83690670 # DTB write hits +system.cpu1.dtb.write_misses 185637 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36642 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5827 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39959 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 225 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6406 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40054 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91756133 # DTB read accesses -system.cpu1.dtb.write_accesses 75444272 # DTB write accesses +system.cpu1.dtb.perms_faults 43965 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 101779402 # DTB read accesses +system.cpu1.dtb.write_accesses 83876307 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 166672994 # DTB hits -system.cpu1.dtb.misses 527411 # DTB misses -system.cpu1.dtb.accesses 167200405 # DTB accesses +system.cpu1.dtb.hits 185068245 # DTB hits +system.cpu1.dtb.misses 587464 # DTB misses +system.cpu1.dtb.accesses 185655709 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1834,1160 +1841,1166 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 82282 # Table walker walks requested -system.cpu1.itb.walker.walksLong 82282 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 773 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59282 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9946 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 72336 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1446.824541 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 71995 99.53% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 83 0.11% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 237 0.33% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 72336 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 68717 98.17% 98.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 87 0.12% 98.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 984 1.41% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 73 0.10% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 83 0.12% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 391052327076 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.846616 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.360520 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 60001678208 15.34% 15.34% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 331032470368 84.65% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 15971500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 2073000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 134000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 391052327076 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 59282 98.71% 98.71% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 773 1.29% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 60055 # Table walker page sizes translated +system.cpu1.itb.walker.walks 92227 # Table walker walks requested +system.cpu1.itb.walker.walksLong 92227 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 973 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66704 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 11080 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 81147 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1613.670253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12323.334174 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 80305 98.96% 98.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 403 0.50% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 81 0.10% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 234 0.29% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 81147 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 78757 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26873.185876 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 76775 97.48% 97.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 153 0.19% 97.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1519 1.93% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 117 0.15% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 110 0.14% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 35 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 36 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 78757 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 434901307160 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.857521 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.349757 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 61992873300 14.25% 14.25% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 372883353360 85.74% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 22166000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 2474500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 253500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 186500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 434901307160 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 66704 98.56% 98.56% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 973 1.44% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 67677 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82282 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82282 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 92227 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 92227 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60055 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60055 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 142337 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 193960223 # ITB inst hits -system.cpu1.itb.inst_misses 82282 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 67677 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 67677 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 159904 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 215454990 # ITB inst hits +system.cpu1.itb.inst_misses 92227 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26113 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28858 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 206259 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 231246 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 194042505 # ITB inst accesses -system.cpu1.itb.hits 193960223 # DTB hits -system.cpu1.itb.misses 82282 # DTB misses -system.cpu1.itb.accesses 194042505 # DTB accesses -system.cpu1.numCycles 680051209 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 215547217 # ITB inst accesses +system.cpu1.itb.hits 215454990 # DTB hits +system.cpu1.itb.misses 92227 # DTB misses +system.cpu1.itb.accesses 215547217 # DTB accesses +system.cpu1.numCycles 759155378 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 76309039 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 545586843 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 123149965 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 73130533 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 567094976 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12846360 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1862646 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 285569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6032568 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 729307 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 772817 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 193732934 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1488213 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 27982 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 659510102 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.972600 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.218843 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 87128814 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 606063748 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 136771271 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81086195 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 630037393 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14425462 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2172177 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 325931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6736887 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 827556 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 851702 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 215200214 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1679756 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 31517 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 735293191 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.969104 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.218230 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 352323655 53.42% 53.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 119769188 18.16% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 40581175 6.15% 77.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 146836084 22.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 394185812 53.61% 53.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 132782093 18.06% 71.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 45182528 6.14% 77.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 163142758 22.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 659510102 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.181089 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.802273 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 93216709 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 325116567 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 201438015 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 35171632 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4567179 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17405067 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1892222 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 567399835 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20537774 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4567179 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 125466899 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 47033211 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 215743407 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 203915656 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 62783750 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 552356795 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5241539 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9909237 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 240791 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 292344 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 29944703 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11393 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 524936389 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 854810992 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 653637843 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 615050 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 473696954 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 51239429 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15119385 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13351935 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 70628253 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 91219643 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78311402 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8799360 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7480777 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 531265202 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15384643 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 536975559 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2409415 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 48765571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31310459 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 261406 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 659510102 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.814204 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.064087 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 735293191 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.180162 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.798340 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 105275670 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 361149345 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 225652352 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38094367 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5121457 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19322389 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2132865 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 630175710 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23074598 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5121457 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 140790232 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54705867 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 237824642 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 227778492 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 69072501 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 613335461 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5878562 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 11068691 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 265258 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 344448 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 33464644 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 12708 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 582683755 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 946463821 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 725287459 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 802163 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 525337621 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 57346134 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 16349116 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 14383675 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 76724538 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101292205 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87094038 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 9603338 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 8276902 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 590341476 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 16600780 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 596033149 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2703684 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 54441407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 34942140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 296921 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 735293191 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.810606 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.063717 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 364889522 55.33% 55.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 126119203 19.12% 74.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 101926801 15.45% 89.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 59299384 8.99% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7271358 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3834 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408888874 55.61% 55.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 138685440 18.86% 74.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 113812160 15.48% 89.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 65908523 8.96% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7993150 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 5044 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 659510102 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 735293191 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53688772 43.65% 43.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 42849 0.03% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 9758 0.01% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 12 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33350405 27.12% 70.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35903096 29.19% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 59894815 43.89% 43.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 54223 0.04% 43.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 19415 0.01% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36698954 26.89% 70.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 39811710 29.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 365127801 68.00% 68.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1207443 0.22% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 64356 0.01% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 5 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 40592 0.01% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94109837 17.53% 85.77% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76425394 14.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 405160238 67.98% 67.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1323587 0.22% 68.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 73165 0.01% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 6 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 83635 0.01% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 104404803 17.52% 85.74% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84987627 14.26% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 536975559 # Type of FU issued -system.cpu1.iq.rate 0.789610 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 122994892 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.229051 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1857852304 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 595160433 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 521544916 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1013221 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 400944 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 372548 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 659338375 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 631992 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2462766 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 596033149 # Type of FU issued +system.cpu1.iq.rate 0.785127 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 136479130 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228979 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 2065187396 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 660997777 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 578833453 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1354907 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 550149 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 503649 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 731674033 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 838206 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2717332 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11273364 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 14330 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 146929 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5363484 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12501770 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 165759 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5982611 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2532880 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4046276 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2801463 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 4362378 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4567179 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5912411 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2185508 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 546765447 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 5121457 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6701200 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2456436 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 607072203 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 91219643 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78311402 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13149679 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62909 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2062449 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 146929 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1850208 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2506307 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4356515 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 530131647 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 91388835 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6328626 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 101292205 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87094038 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 14166456 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66987 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2327340 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 165759 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2053658 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2840126 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4893784 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 588333719 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 101371104 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7124424 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 115602 # number of nop insts executed -system.cpu1.iew.exec_refs 166669354 # number of memory reference insts executed -system.cpu1.iew.exec_branches 99325061 # Number of branches executed -system.cpu1.iew.exec_stores 75280519 # Number of stores executed -system.cpu1.iew.exec_rate 0.779547 # Inst execution rate -system.cpu1.iew.wb_sent 522591798 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 521917464 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 252132377 # num instructions producing a value -system.cpu1.iew.wb_consumers 413034686 # num instructions consuming a value +system.cpu1.iew.exec_nop 129947 # number of nop insts executed +system.cpu1.iew.exec_refs 185062017 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110209905 # Number of branches executed +system.cpu1.iew.exec_stores 83690913 # Number of stores executed +system.cpu1.iew.exec_rate 0.774985 # Inst execution rate +system.cpu1.iew.wb_sent 580075402 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 579337102 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 280158358 # num instructions producing a value +system.cpu1.iew.wb_consumers 458852190 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.767468 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610439 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.763134 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610563 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 42738935 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15123237 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4100199 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 651431241 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.764293 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.565341 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 47675638 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 16303859 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4608134 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 726275789 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.760731 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.562013 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 432003686 66.32% 66.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 115523895 17.73% 84.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 47761812 7.33% 91.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15857432 2.43% 93.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11422302 1.75% 95.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7738049 1.19% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5451213 0.84% 97.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3205095 0.49% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12467757 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 483439526 66.56% 66.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 126884990 17.47% 84.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 53284484 7.34% 91.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 17968651 2.47% 93.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12727519 1.75% 95.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8624800 1.19% 96.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6048440 0.83% 97.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3562811 0.49% 98.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 13734568 1.89% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 651431241 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 422487941 # Number of instructions committed -system.cpu1.commit.committedOps 497884267 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 726275789 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 468737677 # Number of instructions committed +system.cpu1.commit.committedOps 552500848 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 152894196 # Number of memory references committed -system.cpu1.commit.loads 79946278 # Number of loads committed -system.cpu1.commit.membars 3616952 # Number of memory barriers committed -system.cpu1.commit.branches 94285217 # Number of branches committed -system.cpu1.commit.fp_insts 364520 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 457066504 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12254498 # Number of function calls committed. +system.cpu1.commit.refs 169901862 # Number of memory references committed +system.cpu1.commit.loads 88790435 # Number of loads committed +system.cpu1.commit.membars 3923548 # Number of memory barriers committed +system.cpu1.commit.branches 104577420 # Number of branches committed +system.cpu1.commit.fp_insts 490317 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 507351840 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13608772 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 343931170 69.08% 69.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 972359 0.20% 69.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50623 0.01% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.28% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 35877 0.01% 69.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.29% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 79946278 16.06% 85.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 72947918 14.65% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 381394130 69.03% 69.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1072293 0.19% 69.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 58068 0.01% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 74453 0.01% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 88790435 16.07% 85.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 81111427 14.68% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 497884267 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12467757 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1176002301 # The number of ROB reads -system.cpu1.rob.rob_writes 1089287670 # The number of ROB writes -system.cpu1.timesIdled 891748 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 20541107 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94110305176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 422487941 # Number of Instructions Simulated -system.cpu1.committedOps 497884267 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.609635 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.609635 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.621259 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.621259 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 627139214 # number of integer regfile reads -system.cpu1.int_regfile_writes 370414988 # number of integer regfile writes -system.cpu1.fp_regfile_reads 604419 # number of floating regfile reads -system.cpu1.fp_regfile_writes 299356 # number of floating regfile writes -system.cpu1.cc_regfile_reads 113711382 # number of cc regfile reads -system.cpu1.cc_regfile_writes 114470989 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1170516156 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15242864 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5157965 # number of replacements -system.cpu1.dcache.tags.tagsinuse 429.133488 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 142089244 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5158477 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.544805 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 429.133488 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.838151 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.838151 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 378 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 317144363 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 317144363 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 74103111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74103111 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 63551574 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 63551574 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 164336 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 164336 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50299 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 50299 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740316 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1740316 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762571 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1762571 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 137654685 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 137654685 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 137819021 # number of overall hits -system.cpu1.dcache.overall_hits::total 137819021 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6065944 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6065944 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6987777 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6987777 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664365 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 664365 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 405961 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 405961 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258244 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 258244 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193910 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193910 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13053721 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13053721 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13718086 # number of overall misses -system.cpu1.dcache.overall_misses::total 13718086 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 97739183000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 97739183000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 145756860728 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 145756860728 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16103531712 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 16103531712 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4003848500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4003848500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4624613000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4624613000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5341000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5341000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 243496043728 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 243496043728 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 243496043728 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 243496043728 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80169055 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80169055 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70539351 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70539351 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828701 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 828701 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 456260 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 456260 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998560 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1998560 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956481 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1956481 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 150708406 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 150708406 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 151537107 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 151537107 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075664 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.075664 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099062 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.099062 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801694 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801694 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889758 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889758 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.129215 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.129215 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099112 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099112 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086616 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.086616 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090526 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.090526 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16112.773708 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15504.129815 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15504.129815 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23849.275437 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23849.275437 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 552500848 # Class of committed instruction +system.cpu1.commit.bw_lim_events 13734568 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1308834452 # The number of ROB reads +system.cpu1.rob.rob_writes 1209328543 # The number of ROB writes +system.cpu1.timesIdled 978867 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23862187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93869849108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 468737677 # Number of Instructions Simulated +system.cpu1.committedOps 552500848 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.619574 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.619574 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.617446 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.617446 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 695521161 # number of integer regfile reads +system.cpu1.int_regfile_writes 411377637 # number of integer regfile writes +system.cpu1.fp_regfile_reads 787723 # number of floating regfile reads +system.cpu1.fp_regfile_writes 479172 # number of floating regfile writes +system.cpu1.cc_regfile_reads 125942514 # number of cc regfile reads +system.cpu1.cc_regfile_writes 126793051 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1299771916 # number of misc regfile reads +system.cpu1.misc_regfile_writes 16418490 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5616176 # number of replacements +system.cpu1.dcache.tags.tagsinuse 458.902978 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 158371031 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5616685 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.196531 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.902978 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896295 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.896295 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 352316395 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 352316395 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 82533449 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 82533449 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71018677 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71018677 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 182219 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 182219 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55748 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 55748 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1865594 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1865594 # number of LoadLockedReq hits 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+system.cpu1.dcache.ReadReq_miss_latency::total 112950117500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 162063724604 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18729695563 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 18729695563 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4597585500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 4597585500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5657651000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5657651000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7414500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7414500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 275013842104 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 275013842104 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 89145147 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 89145147 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78514272 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78514272 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 888832 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 888832 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 494679 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 494679 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2154051 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2154051 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2107285 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2107285 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 167659419 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 167659419 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 168548251 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 168548251 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074168 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074168 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095468 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.095468 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794991 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794991 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.887305 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.887305 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.133914 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.133914 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084143 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.084143 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087891 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087891 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18653.381954 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17750.001256 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4190229 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 23645788 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 332306 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 708476 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.609550 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33.375567 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19494.444618 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18564.573186 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4974164 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 25867147 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 359446 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 756404 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.838418 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34.197528 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3362559 # number of writebacks -system.cpu1.dcache.writebacks::total 3362559 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3121386 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3121386 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5664444 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5664444 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3068 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3068 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 133009 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 133009 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8785830 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8785830 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8785830 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8785830 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2944558 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2944558 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1323333 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1323333 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664291 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 664291 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 402893 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 402893 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125235 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125235 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193904 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193904 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4267891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4267891 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4932182 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4932182 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5159 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10041 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44629208000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44629208000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29351732295 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29351732295 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15227596000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15227596000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15536076712 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15536076712 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1817525500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1817525500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4430771000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4430771000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5279000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5279000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73980940295 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 73980940295 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89208536295 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 89208536295 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520581000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520581000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549653500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549653500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1070234500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1070234500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036729 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036729 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018760 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018760 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.801605 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.801605 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.883034 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.883034 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062663 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062663 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099109 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099109 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028319 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028319 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032548 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032548 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15156.504983 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15156.504983 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22180.155936 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22180.155936 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22923.080397 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38561.297198 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14512.919711 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22850.333155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5616192 # number of writebacks +system.cpu1.dcache.writebacks::total 5616192 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3382349 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3382349 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6057293 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 6057293 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3337 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3337 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 147189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 147189 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 9439642 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 9439642 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 9439642 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 9439642 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3229349 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3229349 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1438302 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1438302 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706535 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 706535 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 435594 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 435594 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141268 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141268 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 203504 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 203504 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4667651 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4667651 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374186 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5374186 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5460 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10752 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 50929568500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 50929568500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34490212579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34490212579 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16980659000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16980659000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18123603563 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18123603563 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2072685000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2072685000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5454243000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5454243000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7318500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7318500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85419781079 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 85419781079 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 102400440079 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 594704500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 594704500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 661334500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 661334500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256039000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1256039000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036226 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036226 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018319 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018319 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794903 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794903 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.880559 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.880559 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065582 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065582 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096572 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096572 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027840 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027840 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031885 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031885 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17334.308748 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17334.308748 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18087.032533 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18087.032533 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100907.346385 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 100907.346385 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112587.771405 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 112587.771405 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106586.445573 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 106586.445573 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5202817 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.771617 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 188211208 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5203329 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 36.171306 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.771617 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980023 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980023 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5955939 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.596349 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 208888584 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5956451 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 35.069303 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.596349 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979680 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979680 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 392655056 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 392655056 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 188211208 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 188211208 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 188211208 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 188211208 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 188211208 # number of overall hits -system.cpu1.icache.overall_hits::total 188211208 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5514651 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5514651 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5514651 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5514651 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5514651 # number of overall misses -system.cpu1.icache.overall_misses::total 5514651 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61642094935 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 61642094935 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 61642094935 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 61642094935 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 61642094935 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 61642094935 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 193725859 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 193725859 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 193725859 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 193725859 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 193725859 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 193725859 # number of overall (read+write) accesses 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overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11177.877790 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9398442 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 360 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 665033 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.132294 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 60 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 436342012 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 436342012 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 208888584 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 208888584 # number of ReadReq hits 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ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 70452471315 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 70452471315 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 70452471315 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 70452471315 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 215192775 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 215192775 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 215192775 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 215192775 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 215192775 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 215192775 # number of overall (read+write) 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11175.497588 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 10802796 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 573 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 747541 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.451108 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 114.600000 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311313 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 311313 # number of ReadReq MSHR hits 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MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 55550609345 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 55550609345 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026859 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.026859 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.026859 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10675.956347 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63484136905 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 63484136905 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63484136905 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 63484136905 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63484136905 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 63484136905 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027680 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027680 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.027680 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency 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prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 858524 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2147738 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13168.263726 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17929780 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2163721 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.286549 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 10234175062500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5935.884902 # Average occupied blocks per requestor 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percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055683 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.803727 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1279 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 76 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14628 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 605 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1303 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5317 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4591 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3288 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078064 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892822 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 355115319 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 355115319 # Number of data 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SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 802083 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 802083 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226128 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1099333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1099333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 21572446 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11121796 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 524506 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 524489 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 17 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 847854 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9869269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4882 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4882 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4416651 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 8880510 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 907695 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 421769 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 471619 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1189775 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1122660 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5203338 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4763767 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 409409 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 401778 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15609171 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16649345 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 393406 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1143795 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 33795717 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333013936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 531452177 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1432064 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4124520 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 870022697 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5627139 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 27397107 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.032027 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.176075 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 24065952 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12401926 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1256 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2060689 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2060329 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 360 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 934376 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 11053796 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5292 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5292 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4812576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 8031153 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2767424 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1034593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 454030 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 361772 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 513435 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1276992 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1207288 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5025648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 440267 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 433765 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17868522 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18112795 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 459206 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1298566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 37739089 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762364336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703129592 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1750272 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4881112 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1472125312 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6734851 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19529823 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.125012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.330788 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 26519684 96.80% 96.80% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 877406 3.20% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 17 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 17088727 87.50% 87.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2440736 12.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 360 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27397107 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14402314458 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 173479331 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 19529823 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23888032965 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176197847 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7809268085 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8940771887 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7687735490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8370756543 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 214700392 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 240887058 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 628828296 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 689185473 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40404 # Transaction distribution -system.iobus.trans_dist::ReadResp 40404 # Transaction distribution -system.iobus.trans_dist::WriteReq 136681 # Transaction distribution -system.iobus.trans_dist::WriteResp 136681 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 136623 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -3002,13 +3015,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122554 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353842 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47640 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3023,105 +3036,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155661 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497091 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496595 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36904500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 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utilization (%) -system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92662000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147904000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115614 # number of replacements -system.iocache.tags.tagsinuse 11.301705 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9126915715000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.837722 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.463983 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239858 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466499 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706357 # Average percentage of cache occupancy +system.iocache.tags.replacements 115596 # number of replacements +system.iocache.tags.tagsinuse 11.294963 # Cycle average of tags in use +system.iocache.tags.total_refs 4 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9125681000000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.424342 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.870620 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.464021 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241914 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041045 # Number of tag accesses -system.iocache.tags.data_accesses 1041045 # Number of data accesses +system.iocache.tags.tag_accesses 1040789 # Number of tag accesses +system.iocache.tags.data_accesses 1040789 # Number of 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(read+write) accesses +system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3135,55 +3148,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140513.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 196729.893082 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 196497.256235 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192551.499159 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130503.397094 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130503.397094 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 196472.603757 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 196472.603757 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36915 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130976.533496 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192528.096904 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192528.096904 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36708 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3596 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3726 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.265573 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.851852 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses 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+system.iocache.overall_mshr_miss_latency::total 1270780512 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3197,621 +3210,626 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90513.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 146729.893082 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 146497.256235 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80503.397094 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80503.397094 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1633941 # number of replacements -system.l2c.tags.tagsinuse 63813.673701 # Cycle average of tags in use -system.l2c.tags.total_refs 5902225 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1694519 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.483127 # Average number of references to valid blocks. +system.l2c.tags.replacements 1583129 # number of replacements +system.l2c.tags.tagsinuse 63158.639853 # Cycle average of tags in use +system.l2c.tags.total_refs 6207421 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1642739 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.778702 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18421.604397 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.885026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 177.213344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5018.050694 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11022.844294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.408023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 214.913940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 271.296665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2354.078258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5504.302098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10936.076961 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.281091 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002226 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.168195 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003279 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004140 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.035920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.083989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.166871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.973719 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11165 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 256 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1008 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9608 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 249 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4864 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41332 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.170364 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.750076 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73803894 # Number of tag accesses -system.l2c.tags.data_accesses 73803894 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2578909 # number of Writeback hits -system.l2c.Writeback_hits::total 2578909 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 27661 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 31933 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59594 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6629 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5839 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12468 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166000 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 160567 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 326567 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7163 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4665 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 621325 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 619304 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 290117 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6244 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4367 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 539807 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 573735 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292658 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2959385 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 7163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4665 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 621325 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 785304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 290117 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6244 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4367 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 539807 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 734302 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 292658 # number of demand (read+write) hits -system.l2c.demand_hits::total 3285952 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 7163 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4665 # number of overall hits -system.l2c.overall_hits::cpu0.inst 621325 # number of overall hits -system.l2c.overall_hits::cpu0.data 785304 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 290117 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6244 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4367 # number of overall hits -system.l2c.overall_hits::cpu1.inst 539807 # number of overall hits -system.l2c.overall_hits::cpu1.data 734302 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 292658 # number of overall hits -system.l2c.overall_hits::total 3285952 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 47272 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 44187 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 91459 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10524 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8835 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19359 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 557751 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 109635 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 667386 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2718 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2691 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 73804 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 176754 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 337074 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2418 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2009 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 35546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 108545 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 227714 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 969273 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2718 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2691 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 73804 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 734505 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 337074 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2418 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2009 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 35546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 218180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 227714 # number of demand (read+write) misses -system.l2c.demand_misses::total 1636659 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2718 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2691 # number of overall misses -system.l2c.overall_misses::cpu0.inst 73804 # number of overall misses -system.l2c.overall_misses::cpu0.data 734505 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 337074 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2418 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2009 # number of overall misses -system.l2c.overall_misses::cpu1.inst 35546 # number of overall misses -system.l2c.overall_misses::cpu1.data 218180 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 227714 # number of overall misses -system.l2c.overall_misses::total 1636659 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 726731000 # number of UpgradeReq miss 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of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 381455000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 10138420502 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 125762763001 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 346383500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 287503000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4887103000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 32105034998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of demand (read+write) miss cycles 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overall miss cycles -system.l2c.overall_miss_latency::total 277452972563 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 2578909 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2578909 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 74933 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 76120 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 151053 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 17153 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14674 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 31827 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 723751 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 270202 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 993953 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9881 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7356 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 695129 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 796058 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 627191 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8662 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6376 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 575353 # number of ReadSharedReq accesses(hits+misses) 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# number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 952482 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 520372 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4922611 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9881 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7356 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 695129 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1519809 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 627191 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8662 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6376 # number of overall (read+write) accesses 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latency -system.l2c.demand_avg_miss_latency::cpu1.inst 137486.721431 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 147149.303318 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 169523.995263 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142486.571008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141752.136752 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 137369.526069 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 171221.112179 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143252.067825 # average overall miss latency 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occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3404.413573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 297.158145 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 465.494648 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3968.740099 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9359.576527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.311213 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000566 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.049500 # Average percentage of cache occupancy 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+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59756 # Transaction distribution -system.membus.trans_dist::ReadResp 1037606 # Transaction distribution -system.membus.trans_dist::WriteReq 38287 # Transaction distribution -system.membus.trans_dist::WriteResp 38287 # Transaction distribution -system.membus.trans_dist::Writeback 1371305 # Transaction distribution -system.membus.trans_dist::CleanEvict 262648 # Transaction distribution -system.membus.trans_dist::UpgradeReq 440849 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306045 # Transaction distribution -system.membus.trans_dist::UpgradeResp 117782 # Transaction distribution +system.membus.trans_dist::ReadReq 59697 # Transaction distribution +system.membus.trans_dist::ReadResp 1020888 # Transaction distribution +system.membus.trans_dist::WriteReq 38273 # Transaction distribution +system.membus.trans_dist::WriteResp 38273 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1348844 # Transaction distribution +system.membus.trans_dist::CleanEvict 267564 # Transaction distribution +system.membus.trans_dist::UpgradeReq 448101 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314840 # Transaction distribution +system.membus.trans_dist::UpgradeResp 158230 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 681386 # Transaction distribution -system.membus.trans_dist::ReadExResp 660425 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 977850 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5711814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5860036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 343033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6203069 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 185527680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 185734821 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7281536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 193016357 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 652692 # Total snoops (count) -system.membus.snoop_fanout::samples 4246933 # Request fanout histogram +system.membus.trans_dist::ReadExReq 678893 # Transaction distribution +system.membus.trans_dist::ReadExResp 659308 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 961191 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106727 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106727 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122554 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5713992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5862068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6204827 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155661 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182954368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 183161477 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7272320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190433797 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 627031 # Total snoops (count) +system.membus.snoop_fanout::samples 4226315 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4246933 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4226315 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4246933 # Request fanout histogram -system.membus.reqLayer0.occupancy 98658999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4226315 # Request fanout histogram +system.membus.reqLayer0.occupancy 98488499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21380469 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21525971 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9518454911 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9456985184 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8904498116 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8888143010 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230513312 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228798971 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3865,56 +3883,57 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11772030 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5986527 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2060183 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 193514 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 180675 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 12839 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59758 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4863251 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38287 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38287 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3950228 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1568757 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 493482 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 318513 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 811995 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1145198 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1145198 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4810734 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9122705 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6709100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15831805 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283955252 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196820081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 480775333 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3520564 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13735314 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.326662 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.470981 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12205155 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6621083 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1960564 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 171525 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 155955 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 15570 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59699 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4664873 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38273 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38273 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4247047 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1614803 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 750027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 396749 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1146775 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 211 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1140836 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1140836 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4612412 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106727 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8853195 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7749082 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16602277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269317869 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 224565592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 493883461 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3357154 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8803755 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.347401 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.479844 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9261350 67.43% 67.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4461125 32.48% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 12839 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5760896 65.44% 65.44% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3027289 34.39% 99.82% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 15570 0.18% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13735314 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9000721880 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8803755 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9517655622 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2650288 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2614297 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5320683808 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4898920623 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4098533956 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4389147401 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13032 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 12586 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5368 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5763 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 9406da48a..73bffeadf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.331518 # Number of seconds simulated -sim_ticks 51331518104000 # Number of ticks simulated -final_tick 51331518104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.331535 # Number of seconds simulated +sim_ticks 51331535316000 # Number of ticks simulated +final_tick 51331535316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87398 # Simulator instruction rate (inst/s) -host_op_rate 102692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5304439586 # Simulator tick rate (ticks/s) -host_mem_usage 679424 # Number of bytes of host memory used -host_seconds 9677.09 # Real time elapsed on the host -sim_insts 845761974 # Number of instructions simulated -sim_ops 993759083 # Number of ops (including micro ops) simulated +host_inst_rate 107339 # Simulator instruction rate (inst/s) +host_op_rate 126124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6518614527 # Simulator tick rate (ticks/s) +host_mem_usage 729844 # Number of bytes of host memory used +host_seconds 7874.61 # Real time elapsed on the host +sim_insts 845255961 # Number of instructions simulated +sim_ops 993175006 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 196736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5673888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 72271240 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441728 # Number of bytes read from this memory -system.physmem.bytes_read::total 78788712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5673888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5673888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67330112 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 205184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 203136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5579360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 71974536 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439872 # Number of bytes read from this memory +system.physmem.bytes_read::total 78402088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5579360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5579360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67218688 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67350692 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104607 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1129251 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6902 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1247039 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1052033 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67239268 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 103130 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1124615 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6873 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1240998 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050292 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1054606 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1407931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1534899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110534 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1311672 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1052865 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1402150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1527367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1309501 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1312073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1311672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110534 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1408332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2846972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1247039 # Number of read requests accepted -system.physmem.writeReqs 1054606 # Number of write requests accepted -system.physmem.readBursts 1247039 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1054606 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 79759552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50944 # Total number of bytes read from write queue -system.physmem.bytesWritten 67349568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78788712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67350692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 796 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1309902 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1309501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1402551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2837269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1240998 # Number of read requests accepted +system.physmem.writeReqs 1052865 # Number of write requests accepted +system.physmem.readBursts 1240998 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1052865 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79374080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49792 # Total number of bytes read from write queue +system.physmem.bytesWritten 67238272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78402088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67239268 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 778 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 141264 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74145 # Per bank write bursts -system.physmem.perBankRdBursts::1 81438 # Per bank write bursts -system.physmem.perBankRdBursts::2 79571 # Per bank write bursts -system.physmem.perBankRdBursts::3 74681 # Per bank write bursts -system.physmem.perBankRdBursts::4 75850 # Per bank write bursts -system.physmem.perBankRdBursts::5 80076 # Per bank write bursts -system.physmem.perBankRdBursts::6 74234 # Per bank write bursts -system.physmem.perBankRdBursts::7 74770 # Per bank write bursts -system.physmem.perBankRdBursts::8 71012 # Per bank write bursts -system.physmem.perBankRdBursts::9 102127 # Per bank write bursts -system.physmem.perBankRdBursts::10 78424 # Per bank write bursts -system.physmem.perBankRdBursts::11 78933 # Per bank write bursts -system.physmem.perBankRdBursts::12 75355 # Per bank write bursts -system.physmem.perBankRdBursts::13 78384 # Per bank write bursts -system.physmem.perBankRdBursts::14 73014 # Per bank write bursts -system.physmem.perBankRdBursts::15 74229 # Per bank write bursts -system.physmem.perBankWrBursts::0 61794 # Per bank write bursts -system.physmem.perBankWrBursts::1 67391 # Per bank write bursts -system.physmem.perBankWrBursts::2 68136 # Per bank write bursts -system.physmem.perBankWrBursts::3 64875 # Per bank write bursts -system.physmem.perBankWrBursts::4 65862 # Per bank write bursts -system.physmem.perBankWrBursts::5 67755 # Per bank write bursts -system.physmem.perBankWrBursts::6 63835 # Per bank write bursts -system.physmem.perBankWrBursts::7 65687 # Per bank write bursts -system.physmem.perBankWrBursts::8 61691 # Per bank write bursts -system.physmem.perBankWrBursts::9 69909 # Per bank write bursts -system.physmem.perBankWrBursts::10 65651 # Per bank write bursts -system.physmem.perBankWrBursts::11 67939 # Per bank write bursts -system.physmem.perBankWrBursts::12 65356 # Per bank write bursts -system.physmem.perBankWrBursts::13 67578 # Per bank write bursts -system.physmem.perBankWrBursts::14 64108 # Per bank write bursts -system.physmem.perBankWrBursts::15 64770 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 323831 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 73630 # Per bank write bursts +system.physmem.perBankRdBursts::1 80699 # Per bank write bursts +system.physmem.perBankRdBursts::2 78276 # Per bank write bursts +system.physmem.perBankRdBursts::3 74217 # Per bank write bursts +system.physmem.perBankRdBursts::4 73666 # Per bank write bursts +system.physmem.perBankRdBursts::5 79970 # Per bank write bursts +system.physmem.perBankRdBursts::6 75195 # Per bank write bursts +system.physmem.perBankRdBursts::7 74032 # Per bank write bursts +system.physmem.perBankRdBursts::8 71713 # Per bank write bursts +system.physmem.perBankRdBursts::9 100993 # Per bank write bursts +system.physmem.perBankRdBursts::10 77049 # Per bank write bursts +system.physmem.perBankRdBursts::11 78387 # Per bank write bursts +system.physmem.perBankRdBursts::12 77207 # Per bank write bursts +system.physmem.perBankRdBursts::13 77888 # Per bank write bursts +system.physmem.perBankRdBursts::14 72930 # Per bank write bursts +system.physmem.perBankRdBursts::15 74368 # Per bank write bursts +system.physmem.perBankWrBursts::0 61890 # Per bank write bursts +system.physmem.perBankWrBursts::1 67926 # Per bank write bursts +system.physmem.perBankWrBursts::2 67010 # Per bank write bursts +system.physmem.perBankWrBursts::3 65080 # Per bank write bursts +system.physmem.perBankWrBursts::4 64889 # Per bank write bursts +system.physmem.perBankWrBursts::5 68021 # Per bank write bursts +system.physmem.perBankWrBursts::6 64968 # Per bank write bursts +system.physmem.perBankWrBursts::7 65143 # Per bank write bursts +system.physmem.perBankWrBursts::8 62358 # Per bank write bursts +system.physmem.perBankWrBursts::9 69100 # Per bank write bursts +system.physmem.perBankWrBursts::10 64674 # Per bank write bursts +system.physmem.perBankWrBursts::11 67475 # Per bank write bursts +system.physmem.perBankWrBursts::12 66848 # Per bank write bursts +system.physmem.perBankWrBursts::13 67005 # Per bank write bursts +system.physmem.perBankWrBursts::14 63727 # Per bank write bursts +system.physmem.perBankWrBursts::15 64484 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 51331516800500 # Total gap between requests +system.physmem.numWrRetry 26 # Number of times write queue was full causing retry +system.physmem.totGap 51331533904500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1225754 # Read request sizes (log2) +system.physmem.readPktSize::6 1219713 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1052033 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 635607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 328525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 149631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 126665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050292 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 631662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 326376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 149637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,120 +159,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 31214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 63148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 66981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 65872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 66221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 71514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 66478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 79594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 84129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 64906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 68384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 476504 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.725081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.620621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.470597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 186131 39.06% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 111955 23.50% 62.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45179 9.48% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23084 4.84% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18337 3.85% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11525 2.42% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10900 2.29% 85.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8098 1.70% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61295 12.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 476504 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59915 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.799683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 269.572248 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 59912 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 11849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31106 # What 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+system.physmem.wrQLenPdf::29 84167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 64432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 475699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.203229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.287854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.241632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186276 39.16% 39.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 111535 23.45% 62.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45072 9.47% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23389 4.92% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18072 3.80% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11535 2.42% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10579 2.22% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8108 1.70% 87.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61133 12.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 475699 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.735663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 269.812069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 59807 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59915 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59915 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.563832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.981523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.290123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 57069 95.25% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 858 1.43% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 58 0.10% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 312 0.52% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.06% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 354 0.59% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 211 0.35% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.04% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 62 0.10% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 123 0.21% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 28 0.05% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 35 0.06% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 500 0.83% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 31 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 125 0.21% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59810 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59810 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.565591 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.987331 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.225331 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56970 95.25% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 839 1.40% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 56 0.09% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 337 0.56% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 42 0.07% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 348 0.58% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 200 0.33% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 22 0.04% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.11% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 127 0.21% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.05% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 38 0.06% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 506 0.85% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 125 0.21% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 19 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59915 # Writes before turning the bus around for reads -system.physmem.totQLat 31917471814 # Total ticks spent queuing -system.physmem.totMemAccLat 55284528064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6231215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25610.95 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59810 # Writes before turning the bus around for reads +system.physmem.totQLat 31819415784 # Total ticks spent queuing +system.physmem.totMemAccLat 55073540784 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6201100000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25656.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44360.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44406.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s @@ -281,56 +281,56 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.76 # Average write queue length when enqueuing -system.physmem.readRowHits 1024444 # Number of row buffer hits during reads -system.physmem.writeRowHits 797630 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing +system.physmem.readRowHits 1019502 # Number of row buffer hits during reads +system.physmem.writeRowHits 795615 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 22302099.93 # Average gap between requests -system.physmem.pageHitRate 79.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1809644760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 987405375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4795167000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3404170800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235982378375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29714714061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34314417854910 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.486362 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49432942986454 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714072100000 # Time in different power states +system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes +system.physmem.avgGap 22377767.94 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1796611320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 980293875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4755496200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3401526960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352726044720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1234173509595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716310123250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34314143605920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.480817 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49435613390416 # Time in different power states +system.physmem_0.memoryStateTime::REF 1714072620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184500143546 # Time in different power states +system.physmem_0.memoryStateTime::ACT 181848672584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1792725480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 978173625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4925481600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3414972960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1238461921980 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712539014500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34314837317745 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494534 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49429295042072 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714072100000 # Time in different power states +system.physmem_1.actEnergy 1799673120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 981964500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4918173000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3406348080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352726044720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1238619690855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712409964250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34314861858525 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494809 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49429083175074 # Time in different power states +system.physmem_1.memoryStateTime::REF 1714072620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 188150328928 # Time in different power states +system.physmem_1.memoryStateTime::ACT 188374993676 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory +system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). @@ -339,15 +339,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 223690256 # Number of BP lookups -system.cpu.branchPred.condPredicted 149470273 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12181359 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157723580 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103180902 # Number of BTB hits +system.cpu.branchPred.lookups 223536271 # Number of BP lookups +system.cpu.branchPred.condPredicted 149385948 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12169974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157736918 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103109650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.418818 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30739943 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 342702 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.368115 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30707782 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 342742 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,87 +378,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 934978 # Table walker walks requested -system.cpu.dtb.walker.walksLong 934978 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15042 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154863 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 425141 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 509837 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2238.847906 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 506434 99.33% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1917 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 986 0.19% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 153 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 25 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 51 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 509837 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 473320 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 462482 97.71% 97.71% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7672 1.62% 99.33% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2249 0.48% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 179 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 532 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 62 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 112 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 23 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 473320 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 784047304876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.724244 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.519446 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 781857637876 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1171824000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 476098500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 199009000 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 143211000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 120940000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 26747000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 49238000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2599500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 784047304876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 154864 91.15% 91.15% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15042 8.85% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 169906 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 934978 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 935593 # Table walker walks requested +system.cpu.dtb.walker.walksLong 935593 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15313 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154778 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 425408 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 510185 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2222.203710 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14681.416911 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 506821 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1912 0.37% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 970 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 202 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 19 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 50 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 510185 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 473757 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23106.578900 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18127.358359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20599.365275 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 462892 97.71% 97.71% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7688 1.62% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2250 0.47% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 174 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 494 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 87 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 117 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 41 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 473757 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 784064516876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.722483 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.520538 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 781865994376 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1176082000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 477234000 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 199500000 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 146109500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 120981500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 26256500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 49725000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2626500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 784064516876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 154779 91.00% 91.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15313 9.00% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 170092 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 935593 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 934978 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169906 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 935593 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 170092 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169906 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1104884 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 170092 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1105685 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168982671 # DTB read hits -system.cpu.dtb.read_misses 669792 # DTB read misses -system.cpu.dtb.write_hits 147065605 # DTB write hits -system.cpu.dtb.write_misses 265186 # DTB write misses +system.cpu.dtb.read_hits 168870430 # DTB read hits +system.cpu.dtb.read_misses 669785 # DTB read misses +system.cpu.dtb.write_hits 146966916 # DTB write hits +system.cpu.dtb.write_misses 265808 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 39148 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71824 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 71844 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 98 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9312 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9429 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69742 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 169652463 # DTB read accesses -system.cpu.dtb.write_accesses 147330791 # DTB write accesses +system.cpu.dtb.perms_faults 69613 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169540215 # DTB read accesses +system.cpu.dtb.write_accesses 147232724 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316048276 # DTB hits -system.cpu.dtb.misses 934978 # DTB misses -system.cpu.dtb.accesses 316983254 # DTB accesses +system.cpu.dtb.hits 315837346 # DTB hits +system.cpu.dtb.misses 935593 # DTB misses +system.cpu.dtb.accesses 316772939 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,180 +486,177 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161206 # Table walker walks requested -system.cpu.itb.walker.walksLong 161206 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1436 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 121549 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17620 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 143586 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1244.532893 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9274.227664 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 142628 99.33% 99.33% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 542 0.38% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 55 0.04% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 79 0.06% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 218 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 29 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161130 # Table walker walks requested +system.cpu.itb.walker.walksLong 161130 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1443 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121427 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17608 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143522 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1275.602347 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9467.048086 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142512 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 586 0.41% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 51 0.04% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 83 0.06% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 223 0.16% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 32 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 14 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 13 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 143586 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 140605 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28864.162014 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 137806 98.01% 98.01% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 710 0.50% 98.51% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1778 1.26% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 108 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 117 0.08% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 38 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 35 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 140605 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 663785102088 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.942542 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.233053 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 38191035356 5.75% 5.75% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 625543374232 94.24% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 49878500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 812000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 663785102088 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 121549 98.83% 98.83% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1436 1.17% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122985 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143522 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140478 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29089.590541 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24285.230021 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22670.988579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137385 97.80% 97.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 891 0.63% 98.43% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1925 1.37% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 93 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 119 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 23 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140478 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 668097269884 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944108 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230056 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37393446856 5.60% 5.60% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 630652469528 94.40% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 50695000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 657500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 668097269884 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121427 98.83% 98.83% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1443 1.17% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 122870 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161206 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161206 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161130 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161130 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122985 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122985 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 284191 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 355626065 # ITB inst hits -system.cpu.itb.inst_misses 161206 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122870 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 122870 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 284000 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 355391745 # ITB inst hits +system.cpu.itb.inst_misses 161130 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 39148 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52940 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52871 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 369021 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 369048 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 355787271 # ITB inst accesses -system.cpu.itb.hits 355626065 # DTB hits -system.cpu.itb.misses 161206 # DTB misses -system.cpu.itb.accesses 355787271 # DTB accesses -system.cpu.numCycles 1638586091 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 355552875 # ITB inst accesses +system.cpu.itb.hits 355391745 # DTB hits +system.cpu.itb.misses 161130 # DTB misses +system.cpu.itb.accesses 355552875 # DTB accesses +system.cpu.numCycles 1639149006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 642614268 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 998103903 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223690256 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133920845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 910005464 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26014386 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3801464 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9302327 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1031206 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 853 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 355240310 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6091194 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48629 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1579791741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.146164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 642133876 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 997446842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 223536271 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133817432 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 910640256 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 25987402 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3814067 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27748 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9296817 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1023598 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 983 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 355005878 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6082209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48751 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1579931046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.739715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145918 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1024362050 64.84% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 213190505 13.49% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70458696 4.46% 82.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 271780490 17.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1024858413 64.87% 64.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213048750 13.48% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70422001 4.46% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 271601882 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1579791741 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136514 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.609125 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 522893988 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 566130284 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 431833495 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49726107 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9207867 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33553949 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3859168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1081567524 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28956293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9207867 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 567372760 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 69190624 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 368823691 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 437050453 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 128146346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1061861877 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6771880 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5087051 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 328687 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 662195 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 77193560 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1009820206 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1635273516 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1255804175 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1470464 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 944392449 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65427754 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26765768 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23112103 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 102007080 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173010630 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150618329 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9860591 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8967243 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1027007600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27059230 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1042343751 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3268943 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60307743 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33600701 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 312855 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1579791741 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.659798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917984 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1579931046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136373 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.608515 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 522505611 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 567007663 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 431520293 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49702709 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9194770 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33525771 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3859042 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1080875290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28941730 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9194770 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 566963257 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68325752 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 370117398 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 436739828 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 128590041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1061188804 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6761282 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5074872 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 331009 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 667465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 77645177 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20261 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1009236679 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1634390089 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1255037462 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1470821 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 943893813 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65342863 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26761446 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23109655 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 101993436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172887729 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150512713 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9835963 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8956761 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1026341207 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27052915 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1041697414 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3264017 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60219112 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33542548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 311458 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1579931046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.659331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917837 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 934526324 59.16% 59.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 332943694 21.08% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234048480 14.82% 95.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 71809082 4.55% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6444954 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19207 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 935073091 59.18% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 332737212 21.06% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 233873919 14.80% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 71794095 4.54% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6433566 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19163 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1579791741 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1579931046 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57575402 35.04% 35.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100057 0.06% 35.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57548727 35.04% 35.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100099 0.06% 35.10% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26751 0.02% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available @@ -684,19 +679,19 @@ system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # at system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 764 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 757 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44168987 26.88% 62.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62424891 38.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44132085 26.87% 62.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62410380 38.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 717769712 68.86% 68.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2531817 0.24% 69.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122691 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 717342377 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2532202 0.24% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122567 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 8 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -718,102 +713,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121277 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121087 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 172853843 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 148944351 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 172736633 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 148842483 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1042343751 # Type of FU issued -system.cpu.iq.rate 0.636124 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164296841 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3829567748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1113568735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1024464263 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477278 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 947290 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909965 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1205083989 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1556592 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4287735 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1041697414 # Type of FU issued +system.cpu.iq.rate 0.635511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164218799 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157645 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3828331710 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1112806179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1023834597 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2476979 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 946356 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909820 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1204359624 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1556578 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4281868 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13755130 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14415 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6290239 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13732493 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 140572 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6281305 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2513645 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1546946 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2514322 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1544139 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9207867 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6935208 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9652893 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1054288001 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9194770 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6870613 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9053250 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1053615244 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173010630 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150618329 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22687803 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56498 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9524585 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3650015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5096410 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8746425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1031209628 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 168969861 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10209992 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 172887729 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150512713 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22684457 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 56400 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8925068 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 140572 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3644333 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5090402 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8734735 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1030574997 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 168857481 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10197714 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221171 # number of nop insts executed -system.cpu.iew.exec_refs 316030804 # number of memory reference insts executed -system.cpu.iew.exec_branches 195653401 # Number of branches executed -system.cpu.iew.exec_stores 147060943 # Number of stores executed -system.cpu.iew.exec_rate 0.629329 # Inst execution rate -system.cpu.iew.wb_sent 1026179606 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1025374228 # cumulative count of insts written-back -system.cpu.iew.wb_producers 436457494 # num instructions producing a value -system.cpu.iew.wb_consumers 705894723 # num instructions consuming a value +system.cpu.iew.exec_nop 221122 # number of nop insts executed +system.cpu.iew.exec_refs 315819616 # number of memory reference insts executed +system.cpu.iew.exec_branches 195518777 # Number of branches executed +system.cpu.iew.exec_stores 146962135 # Number of stores executed +system.cpu.iew.exec_rate 0.628726 # Inst execution rate +system.cpu.iew.wb_sent 1025549780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1024744417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 436186320 # num instructions producing a value +system.cpu.iew.wb_consumers 705504935 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.625768 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618304 # average fanout of values written-back +system.cpu.iew.wb_rate 0.625169 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618261 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51232529 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26746375 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8382033 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1567845308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.633837 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.270098 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51156578 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26741457 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8371043 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1568002280 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.633402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1057713558 67.46% 67.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 286814809 18.29% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120141410 7.66% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36433500 2.32% 95.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28325160 1.81% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13966043 0.89% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8603569 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4169387 0.27% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11677872 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1058124948 67.48% 67.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 286691231 18.28% 85.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120053535 7.66% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36420041 2.32% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28336916 1.81% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13959603 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8598360 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4160425 0.27% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11657221 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1567845308 # Number of insts commited each cycle -system.cpu.commit.committedInsts 845761974 # Number of instructions committed -system.cpu.commit.committedOps 993759083 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1568002280 # Number of insts commited each cycle +system.cpu.commit.committedInsts 845255961 # Number of instructions committed +system.cpu.commit.committedOps 993175006 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 303583589 # Number of memory references committed -system.cpu.commit.loads 159255499 # Number of loads committed -system.cpu.commit.membars 6904959 # Number of memory barriers committed -system.cpu.commit.branches 188760643 # Number of branches committed -system.cpu.commit.fp_insts 896514 # Number of committed floating point instructions. -system.cpu.commit.int_insts 913055926 # Number of committed integer instructions. -system.cpu.commit.function_calls 25211674 # Number of function calls committed. +system.cpu.commit.refs 303386643 # Number of memory references committed +system.cpu.commit.loads 159155235 # Number of loads committed +system.cpu.commit.membars 6901293 # Number of memory barriers committed +system.cpu.commit.branches 188640484 # Number of branches committed +system.cpu.commit.fp_insts 896738 # Number of committed floating point instructions. +system.cpu.commit.int_insts 912506063 # Number of committed integer instructions. +system.cpu.commit.function_calls 25186659 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 687818920 69.21% 69.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2146460 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98075 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 687431731 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2146648 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 97945 0.01% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction @@ -840,531 +835,537 @@ system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159255499 16.03% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144328090 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159155235 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144231408 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 993759083 # Class of committed instruction -system.cpu.commit.bw_lim_events 11677872 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2593635375 # The number of ROB reads -system.cpu.rob.rob_writes 2101836328 # The number of ROB writes -system.cpu.timesIdled 8111566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58794350 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101024450248 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 845761974 # Number of Instructions Simulated -system.cpu.committedOps 993759083 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.937408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.937408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.516154 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.516154 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1220647692 # number of integer regfile reads -system.cpu.int_regfile_writes 729132584 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462075 # number of floating regfile reads -system.cpu.fp_regfile_writes 783592 # number of floating regfile writes -system.cpu.cc_regfile_reads 224479860 # number of cc regfile reads -system.cpu.cc_regfile_writes 225129726 # number of cc regfile writes -system.cpu.misc_regfile_reads 2563991678 # number of misc regfile reads -system.cpu.misc_regfile_writes 26780868 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9656863 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972805 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 282353083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9657375 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.237042 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972805 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 993175006 # Class of committed instruction +system.cpu.commit.bw_lim_events 11657221 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2593153041 # The number of ROB reads +system.cpu.rob.rob_writes 2100498051 # The number of ROB writes +system.cpu.timesIdled 8123602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59217960 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101023921760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 845255961 # Number of Instructions Simulated +system.cpu.committedOps 993175006 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.939234 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.939234 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515668 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515668 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1219925781 # number of integer regfile reads +system.cpu.int_regfile_writes 728690424 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462315 # number of floating regfile reads +system.cpu.fp_regfile_writes 782072 # number of floating regfile writes +system.cpu.cc_regfile_reads 224390859 # number of cc regfile reads +system.cpu.cc_regfile_writes 225039549 # number of cc regfile writes +system.cpu.misc_regfile_reads 2563491272 # number of misc regfile reads +system.cpu.misc_regfile_writes 26777143 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9646522 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 282175483 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9647034 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.249973 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233161168 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233161168 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146769345 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146769345 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127879890 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127879890 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 376551 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 376551 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 324490 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 324490 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3281849 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3281849 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3677222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3677222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 274649235 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 274649235 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 275025786 # number of overall hits -system.cpu.dcache.overall_hits::total 275025786 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9521174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9521174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11203473 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11203473 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1164152 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1164152 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1231188 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1231188 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446606 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446606 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1232341715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1232341715 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146679057 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146679057 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127793945 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127793945 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377283 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377283 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324111 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 324111 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 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StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160324821421 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 160324821421 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183323291421 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 183323291421 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829051500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829051500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836628967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836628967 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665680467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11665680467 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032602 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032602 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751195 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751195 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786904 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786904 # mshr miss rate for WriteLineReq accesses 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+system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87447550388 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3189935000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3189935000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160004807667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160004807667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182887797167 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 182887797167 # number of overall MSHR miss cycles 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+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750762 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750762 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787171 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787171 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061057 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061057 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024009 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024009 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027782 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16481.896697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16481.896697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38242.985935 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38242.985935 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19871.354660 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19871.354660 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71599.791887 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71599.791887 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14039.246564 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14039.246564 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22607.621836 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22607.621836 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22223.712273 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22223.712273 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173081.878378 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173081.878378 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173214.297454 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173214.297454 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173148.105605 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173148.105605 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023990 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023990 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027764 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027764 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16466.557160 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16466.557160 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38215.528492 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38215.528492 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19778.480143 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19778.480143 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71410.180615 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71410.180615 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14017.009702 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14017.009702 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54100 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54100 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22595.831006 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22595.831006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22200.161853 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22200.161853 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183884.256785 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183884.256785 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184836.923196 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184836.923196 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184360.717250 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184360.717250 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15000702 # number of replacements -system.cpu.icache.tags.tagsinuse 511.916861 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 339450182 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15001214 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.628181 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.916861 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 14982836 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916862 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 339236129 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14983348 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.640876 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916862 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 370220442 # Number of tag accesses -system.cpu.icache.tags.data_accesses 370220442 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 339450182 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 339450182 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 339450182 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 339450182 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 339450182 # number of overall hits -system.cpu.icache.overall_hits::total 339450182 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15768830 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15768830 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15768830 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15768830 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15768830 # number of overall misses -system.cpu.icache.overall_misses::total 15768830 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 212844795884 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 212844795884 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 212844795884 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 212844795884 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 212844795884 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 212844795884 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 355219012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 355219012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 355219012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 355219012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 355219012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 355219012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044392 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044392 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044392 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044392 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044392 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044392 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13497.817903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13497.817903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13497.817903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13497.817903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13497.817903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13497.817903 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 22619 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 369968151 # Number of tag accesses +system.cpu.icache.tags.data_accesses 369968151 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 339236129 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 339236129 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 339236129 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 339236129 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 339236129 # number of overall hits +system.cpu.icache.overall_hits::total 339236129 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15748452 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15748452 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15748452 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15748452 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15748452 # number of overall misses +system.cpu.icache.overall_misses::total 15748452 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 212811738878 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 212811738878 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 212811738878 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 212811738878 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 212811738878 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 212811738878 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 354984581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 354984581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 354984581 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 354984581 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 354984581 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 354984581 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044364 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044364 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044364 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044364 # miss rate for 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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005464 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075140 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029445 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004097 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010515 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005464 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075140 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029445 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127642.407057 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128147.962382 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70771.209706 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70771.209706 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128807.494258 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128807.494258 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124607.335662 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124607.335662 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128900.599082 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128900.599082 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145058.604546 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145058.604546 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127642.407057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124607.335662 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128843.715731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128356.573108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128648.471616 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127642.407057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124607.335662 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128843.715731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128356.573108 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171379.654374 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148993.796842 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173202.590812 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173202.590812 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172291.366106 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158193.728290 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50050277 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25391485 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3463 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2168 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2168 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 49994853 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25364266 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3498 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2149 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2149 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1617253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23096406 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1617841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23069110 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8520965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 17374022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8520195 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14980289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2361594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43251 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1956286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1956286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15001430 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6485775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1330832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1224168 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45043419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29192673 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728958 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917333 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 76882383 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960419312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017977630 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2410856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6261232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1987069030 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1835462 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 52366647 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.013365 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.114833 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1955542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1955542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14983570 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6475758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224581 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 44989806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29161893 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 76798843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918014176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017349854 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2414752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6259448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2944038230 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1831110 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27676926 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156737 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 51666749 98.66% 98.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 699898 1.34% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 26979426 97.48% 97.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 697500 2.52% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 52366647 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32990991996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27676926 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 47946942997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1490388 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1474889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22530796241 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22505485675 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13336103780 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13321051501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 427917846 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 427763271 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1135029759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1135810761 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40289 # Transaction distribution -system.iobus.trans_dist::ReadResp 40289 # Transaction distribution +system.iobus.trans_dist::ReadReq 40286 # Transaction distribution +system.iobus.trans_dist::ReadResp 40286 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1585,11 +1587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353714 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1606,104 +1608,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41870500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25173000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36497500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565927033 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565751099 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 44500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147690000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115449 # number of replacements -system.iocache.tags.tagsinuse 10.422254 # Cycle average of tags in use +system.iocache.tags.replacements 115446 # number of replacements +system.iocache.tags.tagsinuse 10.422238 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103107121000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.543889 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878365 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429898 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651391 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103145499000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.543896 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.878342 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221494 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429896 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039569 # Number of tag accesses -system.iocache.tags.data_accesses 1039569 # Number of data accesses +system.iocache.tags.tag_accesses 1039542 # Number of tag accesses +system.iocache.tags.data_accesses 1039542 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8801 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8838 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 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miss cycles -system.iocache.ReadReq_miss_latency::total 1690545007 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8801 # number of overall misses +system.iocache.overall_misses::total 8841 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1693888006 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1698957506 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13827154026 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13827154026 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5457000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1685439007 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1690896007 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5457000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1685439007 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1690896007 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13866022593 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13866022593 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1693888006 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1699308506 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1693888006 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1699308506 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8804 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8841 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8801 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8838 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8804 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8844 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8801 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8841 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8804 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8844 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8801 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8841 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1717,55 +1719,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 138000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191440.141640 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191216.492139 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 192465.402341 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 192233.254809 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129632.809814 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129632.809814 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 136425 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191191.316938 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 136425 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191191.316938 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34672 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129997.211740 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129997.211740 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192465.402341 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192207.726049 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 192465.402341 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 192207.726049 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36226 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3621 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.923297 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.004419 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8804 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8841 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8801 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8838 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8804 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8844 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8801 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8841 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8804 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3256000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245239007 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1248495007 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8801 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8841 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1253838006 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1257057506 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8493954026 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8493954026 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3457000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1245239007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1248696007 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3457000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1245239007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1248696007 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8532822593 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8532822593 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1253838006 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1257258506 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1253838006 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1257258506 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1779,73 +1781,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141440.141640 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141216.492139 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142465.402341 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 142233.254809 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79632.809814 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79632.809814 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79997.211740 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79997.211740 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142465.402341 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142207.726049 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142465.402341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142207.726049 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54973 # Transaction distribution -system.membus.trans_dist::ReadResp 402008 # Transaction distribution +system.membus.trans_dist::ReadReq 54972 # Transaction distribution +system.membus.trans_dist::ReadResp 398274 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1052033 # Transaction distribution -system.membus.trans_dist::CleanEvict 186512 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34605 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1050292 # Transaction distribution +system.membus.trans_dist::CleanEvict 182485 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34687 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34608 # Transaction distribution -system.membus.trans_dist::ReadExReq 881317 # Transaction distribution -system.membus.trans_dist::ReadExResp 881317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 347035 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34690 # Transaction distribution +system.membus.trans_dist::ReadExReq 879035 # Transaction distribution +system.membus.trans_dist::ReadExResp 879035 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 343302 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3680509 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3810131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4152525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3662907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3792527 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4134863 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138873356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 139043342 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 146309390 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2606 # Total snoops (count) -system.membus.snoop_fanout::samples 2698981 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138377164 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138547134 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7264192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7264192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145811326 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2632 # Total snoops (count) +system.membus.snoop_fanout::samples 2687314 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2698981 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2687314 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2698981 # Request fanout histogram -system.membus.reqLayer0.occupancy 104149000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2687314 # Request fanout histogram +system.membus.reqLayer0.occupancy 103976500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5470500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5452000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7144084722 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7124848125 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6645299856 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6613283400 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228305891 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227684837 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index 7ab4128ed..62fa4c4f2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 549288 # Simulator instruction rate (inst/s) -host_op_rate 645503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28514691627 # Simulator tick rate (ticks/s) -host_mem_usage 672288 # Number of bytes of host memory used -host_seconds 1792.45 # Real time elapsed on the host +host_inst_rate 1110267 # Simulator instruction rate (inst/s) +host_op_rate 1304746 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57636324297 # Simulator tick rate (ticks/s) +host_mem_usage 725492 # Number of bytes of host memory used +host_seconds 886.79 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory +system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory +system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks -system.cpu.dcache.writebacks::total 8921279 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks +system.cpu.dcache.writebacks::total 8921277 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 14295641 # number of writebacks +system.cpu.icache.writebacks::total 14295641 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1722572 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1723188 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id @@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits -system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits +system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses @@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses -system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses +system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) @@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks -system.cpu.l2cache.writebacks::total 1503689 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks +system.cpu.l2cache.writebacks::total 1503967 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution @@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1954373 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1954989 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks 106631 # nu system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525878 # Transaction distribution +system.membus.trans_dist::ReadResp 525254 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610320 # Transaction distribution -system.membus.trans_dist::CleanEvict 225581 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution +system.membus.trans_dist::CleanEvict 224691 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3921686 # Request fanout histogram +system.membus.snoop_fanout::samples 3920464 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3921686 # Request fanout histogram +system.membus.snoop_fanout::total 3920464 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 3e7b5ca50..1811873d2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,74 +4,74 @@ sim_seconds 47.216814 # Nu sim_ticks 47216814145000 # Number of ticks simulated final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 645560 # Simulator instruction rate (inst/s) -host_op_rate 759443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31248192864 # Simulator tick rate (ticks/s) -host_mem_usage 683532 # Number of bytes of host memory used -host_seconds 1511.03 # Real time elapsed on the host +host_inst_rate 1058185 # Simulator instruction rate (inst/s) +host_op_rate 1244860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51221233754 # Simulator tick rate (ticks/s) +host_mem_usage 733588 # Number of bytes of host memory used +host_seconds 921.82 # Real time elapsed on the host sim_insts 975457230 # Number of instructions simulated sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 152640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 127168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3766772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 62976200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 221312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 220864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2509128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 46395632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419264 # Number of bytes read from this memory -system.physmem.bytes_read::total 116788980 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3766772 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2509128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6275900 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100984448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory +system.physmem.bytes_read::total 117007860 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101005032 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2385 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 99263 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 984016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3458 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 39312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 724948 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6551 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1865371 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1577882 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 100947560 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1580456 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3233 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 79776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1333766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 982608 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2473462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 79776 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53141 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 132917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2138739 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2139175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2138739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 79776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1334202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 982608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4612637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -321,36 +321,36 @@ system.cpu0.dcache.tags.tag_accesses 363162248 # Nu system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80919852 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80919852 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262009 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 262009 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036568 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2036568 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 167134763 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 167134763 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167350417 # number of overall hits -system.cpu0.dcache.overall_hits::total 167350417 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits +system.cpu0.dcache.overall_hits::total 167342863 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1475590 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1475590 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831711 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 831711 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158575 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158575 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4784972 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4784972 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5557111 # number of overall misses -system.cpu0.dcache.overall_misses::total 5557111 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses +system.cpu0.dcache.overall_misses::total 5564665 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) @@ -369,20 +369,20 @@ system.cpu0.dcache.overall_accesses::cpu0.data 172907528 system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760442 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760442 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072239 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072239 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,8 +391,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4465852 # number of writebacks -system.cpu0.dcache.writebacks::total 4465852 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks +system.cpu0.dcache.writebacks::total 6272771 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 5539081 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use @@ -443,6 +443,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks +system.cpu0.icache.writebacks::total 5539081 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -450,96 +452,96 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2711851 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16210.481258 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 18787660 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2727832 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.887396 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2670833 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5681.130997 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.077110 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.001745 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4560.666382 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5858.605025 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.346749 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003240 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003479 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278361 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357581 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989409 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15935 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1157 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4616 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5323 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4610 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.972595 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 396153496 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 396153496 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271024 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 142798 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 413822 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4465852 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4465852 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3520 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3520 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634528 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 634528 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4971317 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4971317 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2943098 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2943098 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222986 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 222986 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271024 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 142798 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4971317 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3577626 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8962765 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271024 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 142798 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4971317 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3577626 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8962765 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11253 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8486 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 19739 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128216 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 128216 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158575 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 158575 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709702 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 709702 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 568281 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 568281 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1258239 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 1258239 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608349 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 608349 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11253 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8486 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 568281 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1967941 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2555961 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11253 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8486 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 568281 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1967941 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2555961 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282277 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151284 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 433561 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4465852 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4465852 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131736 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 131736 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158575 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 158575 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9091243 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 298097 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 159313 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5035825 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3598008 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9091243 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11326 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8418 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 19744 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138515 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 138515 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158509 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158509 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 708286 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 708286 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 503773 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 503773 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1239273 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1239273 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607364 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 607364 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11326 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8418 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 503773 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1947559 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2471076 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11326 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8418 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 503773 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1947559 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2471076 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 309423 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 167731 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 477154 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4459579 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4459579 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7350874 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7350874 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139275 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 139275 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158509 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158509 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) @@ -548,41 +550,41 @@ system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282277 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151284 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11518726 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282277 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151284 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11518726 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056093 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973280 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973280 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527962 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527962 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102585 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102585 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.299485 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.299485 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731774 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731774 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056093 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102585 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354867 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.221896 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039865 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056093 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102585 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354867 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.221896 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,24 +593,24 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1571493 # number of writebacks -system.cpu0.l2cache.writebacks::total 1571493 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks +system.cpu0.l2cache.writebacks::total 1567377 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24275029 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12358536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 471082 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 471076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4465852 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 7344601 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 131736 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158575 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 290311 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution @@ -616,27 +618,27 @@ system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19736583 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37534931 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 640924169 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1000009861 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4846239 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 29334646 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.024894 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.155804 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6119333 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28604393 97.51% 97.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 730247 2.49% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 29334646 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -853,36 +855,36 @@ system.cpu1.dcache.tags.tag_accesses 348813711 # Nu system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 76990146 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 76990146 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63440 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 63440 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048851 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2048851 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 160687710 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 160687710 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 160875564 # number of overall hits -system.cpu1.dcache.overall_hits::total 160875564 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits +system.cpu1.dcache.overall_hits::total 160867239 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1453330 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1453330 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427059 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 427059 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158898 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 158898 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4811552 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4811552 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5603903 # number of overall misses -system.cpu1.dcache.overall_misses::total 5603903 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses +system.cpu1.dcache.overall_misses::total 5612228 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) @@ -901,20 +903,20 @@ system.cpu1.dcache.overall_accesses::cpu1.data 166479467 system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018527 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018527 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870662 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870662 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071973 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071973 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029073 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029073 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033661 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033661 # miss rate for overall accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -923,8 +925,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4029235 # number of writebacks -system.cpu1.dcache.writebacks::total 4029235 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks +system.cpu1.dcache.writebacks::total 5945049 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 4741297 # number of replacements system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use @@ -974,6 +976,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks +system.cpu1.icache.writebacks::total 4741297 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -981,98 +985,96 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2280083 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13449.950084 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 17410791 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2296131 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.582664 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5225.723861 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.459971 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.577044 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.184130 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5219.005079 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.318953 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004178 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005345 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173900 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.318543 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.820920 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15943 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1612 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5944 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4501 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3801 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973083 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 360471879 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 360471879 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324612 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 139654 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 464266 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4029235 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4029235 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3866 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3866 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614223 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614223 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4216163 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4216163 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3057520 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3057520 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161092 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 161092 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324612 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 139654 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4216163 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3671743 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8352172 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324612 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 139654 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4216163 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3671743 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8352172 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12357 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9710 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 22067 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133787 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133787 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158898 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 158898 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701667 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 701667 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 525646 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 525646 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1239873 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1239873 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265754 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 265754 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12357 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9710 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 525646 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1941540 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2489253 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12357 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9710 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 525646 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1941540 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2489253 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336969 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149364 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 486333 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4029235 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4029235 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137653 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137653 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158898 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 158898 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.tags.replacements 2235881 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13334.612647 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 14249550 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2251891 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8476643 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 346945 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153602 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4283593 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3692503 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8476643 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12460 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9763 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 22223 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144911 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 144911 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159147 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 159147 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 700907 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 700907 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 458216 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 458216 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1219873 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1219873 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 265383 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 265383 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12460 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9763 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 458216 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1920780 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2401219 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12460 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9763 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 458216 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1920780 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2401219 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 359405 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163365 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 522770 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4020160 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4020160 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6665818 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6665818 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145967 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 145967 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159147 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 159147 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4741809 # number of ReadCleanReq accesses(hits+misses) @@ -1081,41 +1083,41 @@ system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4297393 system.cpu1.l2cache.ReadSharedReq_accesses::total 4297393 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 426846 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 426846 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336969 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149364 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 359405 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163365 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10841425 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336969 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149364 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10841425 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065009 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.045374 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971915 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971915 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533226 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533226 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110853 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110853 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.288517 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.288517 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.622599 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.622599 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065009 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110853 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345883 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229606 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036671 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065009 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110853 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345883 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229606 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1124,24 +1126,24 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1182496 # number of writebacks -system.cpu1.l2cache.writebacks::total 1182496 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks +system.cpu1.l2cache.writebacks::total 1179503 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 22040452 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11258515 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 465210 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 465207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4029235 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 6656743 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137653 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158898 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 296551 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution @@ -1149,27 +1151,27 @@ system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18643588 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34068144 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617159548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 925433620 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4444908 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 26656221 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.027820 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.164457 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5690396 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 25914657 97.22% 97.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 741561 2.78% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 26656221 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram system.iobus.trans_dist::ReadReq 40295 # Transaction distribution system.iobus.trans_dist::ReadResp 40295 # Transaction distribution system.iobus.trans_dist::WriteReq 136634 # Transaction distribution @@ -1282,192 +1284,191 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1756378 # number of replacements -system.l2c.tags.tagsinuse 62298.874763 # Cycle average of tags in use -system.l2c.tags.total_refs 4716146 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1814465 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.599194 # Average number of references to valid blocks. +system.l2c.tags.replacements 1759418 # number of replacements +system.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use +system.l2c.tags.total_refs 4473392 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34280.883889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 45.238820 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 58.953050 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3333.891398 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6982.835280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.005625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 424.754545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2990.314104 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13873.998053 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.523085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000900 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106550 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004700 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045629 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.211700 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.950605 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 228 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 57859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 548 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5562 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.882858 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74820318 # Number of tag accesses -system.l2c.tags.data_accesses 74820318 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2753989 # number of Writeback hits -system.l2c.Writeback_hits::total 2753989 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13132 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10939 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24071 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1512 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1301 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2813 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 319600 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 264468 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 584068 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6283 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4584 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 512119 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 747634 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5445 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3568 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 486435 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 695595 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2461663 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4584 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 512119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 1067234 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5445 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 486435 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 960063 # number of demand (read+write) hits -system.l2c.demand_hits::total 3045731 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6283 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4584 # number of overall hits -system.l2c.overall_hits::cpu0.inst 512119 # number of overall hits -system.l2c.overall_hits::cpu0.data 1067234 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5445 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits -system.l2c.overall_hits::cpu1.inst 486435 # number of overall hits -system.l2c.overall_hits::cpu1.data 960063 # number of overall hits -system.l2c.overall_hits::total 3045731 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 58697 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 54120 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 112817 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7808 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7401 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 15209 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 816140 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 547219 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 1363359 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2385 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1987 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 56162 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 181808 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3458 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3451 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 39211 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 186749 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 475211 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2385 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1987 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 56162 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 997948 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3458 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3451 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39211 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 733968 # number of demand (read+write) misses -system.l2c.demand_misses::total 1838570 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2385 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1987 # number of overall misses -system.l2c.overall_misses::cpu0.inst 56162 # number of overall misses -system.l2c.overall_misses::cpu0.data 997948 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3458 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3451 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39211 # number of overall misses -system.l2c.overall_misses::cpu1.data 733968 # number of overall misses -system.l2c.overall_misses::total 1838570 # number of overall misses -system.l2c.Writeback_accesses::writebacks 2753989 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2753989 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71829 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 65059 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 136888 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9320 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8702 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18022 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1135740 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 811687 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1947427 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8668 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6571 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 568281 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 929442 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8903 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7019 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 525646 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 882344 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2936874 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8668 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6571 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 568281 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 2065182 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 8903 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7019 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 525646 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1694031 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4884301 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8668 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6571 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 568281 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 2065182 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8903 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7019 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 525646 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1694031 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4884301 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.817177 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831860 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.824156 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.837768 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850494 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.843913 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.718598 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.674175 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.700082 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.302389 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098828 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.195610 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.491665 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.074596 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.211651 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.161808 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.302389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.098828 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.483225 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.491665 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.074596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.433267 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.376424 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.302389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.098828 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.483225 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.388408 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.491665 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.074596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.433267 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.376424 # miss rate for overall accesses +system.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 73042126 # Number of tag accesses +system.l2c.tags.data_accesses 73042126 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits +system.l2c.demand_hits::total 2869216 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits +system.l2c.overall_hits::cpu0.inst 446108 # number of overall hits +system.l2c.overall_hits::cpu0.data 1047530 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits +system.l2c.overall_hits::cpu1.inst 416632 # number of overall hits +system.l2c.overall_hits::cpu1.data 938843 # number of overall hits +system.l2c.overall_hits::total 2869216 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses +system.l2c.demand_misses::total 1841838 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses +system.l2c.overall_misses::cpu0.inst 57665 # number of overall misses +system.l2c.overall_misses::cpu0.data 997176 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41584 # number of overall misses +system.l2c.overall_misses::cpu1.data 734147 # number of overall misses +system.l2c.overall_misses::total 1841838 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1672990 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4711054 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8724 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6543 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 503773 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 2044706 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7061 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 458216 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1672990 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4711054 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.822649 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831565 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.826923 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.841834 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.854889 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.848156 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.720649 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.675605 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.701866 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.303072 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.114466 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198813 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.487041 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090752 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.216806 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.173018 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.303072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.114466 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.487687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.487041 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.090752 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.438823 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.390961 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.272352 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.303072 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.114466 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.487687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.383586 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.487041 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.090752 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.438823 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.390961 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1476,51 +1477,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1471188 # number of writebacks -system.l2c.writebacks::total 1471188 # number of writebacks +system.l2c.writebacks::writebacks 1470290 # number of writebacks +system.l2c.writebacks::total 1470290 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 82131 # Transaction distribution -system.membus.trans_dist::ReadResp 566255 # Transaction distribution +system.membus.trans_dist::ReadResp 570231 # Transaction distribution system.membus.trans_dist::WriteReq 38802 # Transaction distribution system.membus.trans_dist::WriteResp 38802 # Transaction distribution -system.membus.trans_dist::Writeback 1577882 # Transaction distribution -system.membus.trans_dist::CleanEvict 244930 # Transaction distribution -system.membus.trans_dist::UpgradeReq 328773 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314660 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150374 # Transaction distribution -system.membus.trans_dist::ReadExReq 1610566 # Transaction distribution -system.membus.trans_dist::ReadExResp 1341014 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 484124 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution +system.membus.trans_dist::CleanEvict 244820 # Transaction distribution +system.membus.trans_dist::UpgradeReq 347427 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution +system.membus.trans_dist::UpgradeResp 168909 # Transaction distribution +system.membus.trans_dist::ReadExReq 1611622 # Transaction distribution +system.membus.trans_dist::ReadExResp 1340459 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6497230 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6647450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344319 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 344319 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6991769 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210588188 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 210799185 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 218198033 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4791150 # Request fanout histogram +system.membus.snoop_fanout::samples 4814081 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4791150 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4791150 # Request fanout histogram +system.membus.snoop_fanout::total 4814081 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1573,41 +1574,41 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11435399 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5875226 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1762842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 121928 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 112531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 9397 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3715978 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2753989 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1064741 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 330496 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317473 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 647969 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2216979 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2216979 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3633845 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9232436 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7825750 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17058186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301171869 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249940932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 551112801 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1989284 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13543939 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.291452 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.455956 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1992317 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9605923 70.92% 70.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3928619 29.01% 99.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 9397 0.07% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13543939 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 4a667c177..938cba50a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 625482 # Simulator instruction rate (inst/s) -host_op_rate 735044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32470102586 # Simulator tick rate (ticks/s) -host_mem_usage 669952 # Number of bytes of host memory used -host_seconds 1574.10 # Real time elapsed on the host +host_inst_rate 1109940 # Simulator instruction rate (inst/s) +host_op_rate 1304361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57619334274 # Simulator tick rate (ticks/s) +host_mem_usage 720500 # Number of bytes of host memory used +host_seconds 887.05 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory +system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory +system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks -system.cpu.dcache.writebacks::total 8921279 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks +system.cpu.dcache.writebacks::total 8921277 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 14295641 # number of writebacks +system.cpu.icache.writebacks::total 14295641 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1722572 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1723188 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id @@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits -system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits +system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses @@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses -system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses +system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) @@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks -system.cpu.l2cache.writebacks::total 1503689 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks +system.cpu.l2cache.writebacks::total 1503967 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution @@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1954373 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1954989 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram system.iobus.trans_dist::ReadReq 40246 # Transaction distribution system.iobus.trans_dist::ReadResp 40246 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks 106631 # nu system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525878 # Transaction distribution +system.membus.trans_dist::ReadResp 525254 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610320 # Transaction distribution -system.membus.trans_dist::CleanEvict 225581 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution +system.membus.trans_dist::CleanEvict 224691 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3921686 # Request fanout histogram +system.membus.snoop_fanout::samples 3920464 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3921686 # Request fanout histogram +system.membus.snoop_fanout::total 3920464 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 538ad9900..bc095ccdb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.474700 # Number of seconds simulated -sim_ticks 47474700369500 # Number of ticks simulated -final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.602568 # Number of seconds simulated +sim_ticks 47602567962500 # Number of ticks simulated +final_tick 47602567962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 794386 # Simulator instruction rate (inst/s) -host_op_rate 934446 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42775515400 # Simulator tick rate (ticks/s) -host_mem_usage 715280 # Number of bytes of host memory used -host_seconds 1109.86 # Real time elapsed on the host -sim_insts 881655060 # Number of instructions simulated -sim_ops 1037101350 # Number of ops (including micro ops) simulated +host_inst_rate 587112 # Simulator instruction rate (inst/s) +host_op_rate 690746 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32025707663 # Simulator tick rate (ticks/s) +host_mem_usage 784812 # Number of bytes of host memory used +host_seconds 1486.39 # Real time elapsed on the host +sim_insts 872675802 # Number of instructions simulated +sim_ops 1026715135 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 127360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 143744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3459124 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40376840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 12078528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 91584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 86464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2488056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17058000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14991744 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 410816 # Number of bytes read from this memory -system.physmem.bytes_read::total 91312260 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3459124 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2488056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5947180 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77042688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 97216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 105280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3176436 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39189384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13261312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 67968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2473528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13920528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 8902656 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 417088 # Number of bytes read from this memory +system.physmem.bytes_read::total 81676100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3176436 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2473528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5649964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69006208 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 77063272 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2246 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 94456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 630901 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 188727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1431 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38964 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 266544 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 234246 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6419 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1467275 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1203792 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69026792 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1645 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 90039 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 612347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 207208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 38737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 217521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 139104 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6517 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1316710 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1078222 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1206366 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 72862 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 850492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 254420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 359307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 315784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1923388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 72862 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 125271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1622816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1080796 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 66728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 823262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 278584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 187020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1715792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 66728 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 118690 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1449632 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1623249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1622816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 72862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 850925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 254420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 359307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 315784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3546637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1467275 # Number of read requests accepted -system.physmem.writeReqs 1206366 # Number of write requests accepted -system.physmem.readBursts 1467275 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1206366 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 93873920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31680 # Total number of bytes read from write queue -system.physmem.bytesWritten 77062336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 91312260 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 77063272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 495 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 220616 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 87562 # Per bank write bursts -system.physmem.perBankRdBursts::1 88840 # Per bank write bursts -system.physmem.perBankRdBursts::2 82797 # Per bank write bursts -system.physmem.perBankRdBursts::3 92927 # Per bank write bursts -system.physmem.perBankRdBursts::4 90148 # Per bank write bursts -system.physmem.perBankRdBursts::5 93986 # Per bank write bursts -system.physmem.perBankRdBursts::6 87799 # Per bank write bursts -system.physmem.perBankRdBursts::7 94269 # Per bank write bursts -system.physmem.perBankRdBursts::8 90753 # Per bank write bursts -system.physmem.perBankRdBursts::9 132105 # Per bank write bursts -system.physmem.perBankRdBursts::10 81290 # Per bank write bursts -system.physmem.perBankRdBursts::11 92144 # Per bank write bursts -system.physmem.perBankRdBursts::12 81361 # Per bank write bursts -system.physmem.perBankRdBursts::13 87555 # Per bank write bursts -system.physmem.perBankRdBursts::14 92182 # Per bank write bursts -system.physmem.perBankRdBursts::15 91062 # Per bank write bursts -system.physmem.perBankWrBursts::0 71771 # Per bank write bursts -system.physmem.perBankWrBursts::1 74672 # Per bank write bursts -system.physmem.perBankWrBursts::2 72652 # Per bank write bursts -system.physmem.perBankWrBursts::3 78055 # Per bank write bursts -system.physmem.perBankWrBursts::4 74620 # Per bank write bursts -system.physmem.perBankWrBursts::5 78875 # Per bank write bursts -system.physmem.perBankWrBursts::6 73591 # Per bank write bursts -system.physmem.perBankWrBursts::7 76891 # Per bank write bursts -system.physmem.perBankWrBursts::8 77107 # Per bank write bursts -system.physmem.perBankWrBursts::9 78277 # Per bank write bursts -system.physmem.perBankWrBursts::10 71128 # Per bank write bursts -system.physmem.perBankWrBursts::11 78119 # Per bank write bursts -system.physmem.perBankWrBursts::12 70456 # Per bank write bursts -system.physmem.perBankWrBursts::13 74533 # Per bank write bursts -system.physmem.perBankWrBursts::14 76600 # Per bank write bursts -system.physmem.perBankWrBursts::15 76752 # Per bank write bursts +system.physmem.bw_write::total 1450064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1449632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 66728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 823694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 278584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 187020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3165856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1316710 # Number of read requests accepted +system.physmem.writeReqs 1080796 # Number of write requests accepted +system.physmem.readBursts 1316710 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1080796 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 84239104 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30336 # Total number of bytes read from write queue +system.physmem.bytesWritten 69025088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81676100 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69026792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 474 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 461546 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74138 # Per bank write bursts +system.physmem.perBankRdBursts::1 82827 # Per bank write bursts +system.physmem.perBankRdBursts::2 74957 # Per bank write bursts +system.physmem.perBankRdBursts::3 82122 # Per bank write bursts +system.physmem.perBankRdBursts::4 83077 # Per bank write bursts +system.physmem.perBankRdBursts::5 87558 # Per bank write bursts +system.physmem.perBankRdBursts::6 81167 # Per bank write bursts +system.physmem.perBankRdBursts::7 84127 # Per bank write bursts +system.physmem.perBankRdBursts::8 76730 # Per bank write bursts +system.physmem.perBankRdBursts::9 122410 # Per bank write bursts +system.physmem.perBankRdBursts::10 70954 # Per bank write bursts +system.physmem.perBankRdBursts::11 80684 # Per bank write bursts +system.physmem.perBankRdBursts::12 75912 # Per bank write bursts +system.physmem.perBankRdBursts::13 81292 # Per bank write bursts +system.physmem.perBankRdBursts::14 78761 # Per bank write bursts +system.physmem.perBankRdBursts::15 79520 # Per bank write bursts +system.physmem.perBankWrBursts::0 61777 # Per bank write bursts +system.physmem.perBankWrBursts::1 69166 # Per bank write bursts +system.physmem.perBankWrBursts::2 64147 # Per bank write bursts +system.physmem.perBankWrBursts::3 68304 # Per bank write bursts +system.physmem.perBankWrBursts::4 69323 # Per bank write bursts +system.physmem.perBankWrBursts::5 73404 # Per bank write bursts +system.physmem.perBankWrBursts::6 67894 # Per bank write bursts +system.physmem.perBankWrBursts::7 70420 # Per bank write bursts +system.physmem.perBankWrBursts::8 65275 # Per bank write bursts +system.physmem.perBankWrBursts::9 69986 # Per bank write bursts +system.physmem.perBankWrBursts::10 62072 # Per bank write bursts +system.physmem.perBankWrBursts::11 68038 # Per bank write bursts +system.physmem.perBankWrBursts::12 64002 # Per bank write bursts +system.physmem.perBankWrBursts::13 68951 # Per bank write bursts +system.physmem.perBankWrBursts::14 67347 # Per bank write bursts +system.physmem.perBankWrBursts::15 68411 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 39 # Number of times write queue was full causing retry -system.physmem.totGap 47474697259000 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 47602564597000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1424050 # Read request sizes (log2) +system.physmem.readPktSize::6 1273485 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1203792 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1195881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 91231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 23675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 20974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2367 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1078222 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1098528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 69154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 26336 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 19787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 17170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 874 # What read queue length does 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an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -188,162 +188,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 58137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 63836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 67727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 73557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 81366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 78356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 81800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 76571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 72953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 940579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.734800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 113.091903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 237.596263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 569137 60.51% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185879 19.76% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 61156 6.50% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 31438 3.34% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21576 2.29% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13250 1.41% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9973 1.06% 94.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9805 1.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 38365 4.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 940579 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 68336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.464104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 309.922160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 68334 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20496 # What write queue length does an incoming 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 63773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 438 # What write queue length does an incoming req see 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an incoming req see +system.physmem.wrQLenPdf::52 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 845861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.192513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.718720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 240.356894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 524023 61.95% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 157589 18.63% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52244 6.18% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27763 3.28% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18582 2.20% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11693 1.38% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8942 1.06% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9176 1.08% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 35849 4.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 845861 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.786182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 329.918437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 60413 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 68336 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 68336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.620273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.104093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.841865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64690 94.66% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1540 2.25% 96.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 239 0.35% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 282 0.41% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 82 0.12% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 291 0.43% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 162 0.24% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 86 0.13% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 81 0.12% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 117 0.17% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 46 0.07% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 391 0.57% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 42 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 42 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 142 0.21% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 20 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 68336 # Writes before turning the bus around for reads -system.physmem.totQLat 37142962355 # Total ticks spent queuing -system.physmem.totMemAccLat 64645087355 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7333900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25322.79 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60416 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60416 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.851513 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.268088 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.277078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56734 93.91% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1553 2.57% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 255 0.42% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 285 0.47% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 70 0.12% 97.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 285 0.47% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 159 0.26% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 94 0.16% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 78 0.13% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 106 0.18% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 41 0.07% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 61 0.10% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 428 0.71% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 38 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 49 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 117 0.19% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60416 # Writes before turning the bus around for reads +system.physmem.totQLat 28673044871 # Total ticks spent queuing +system.physmem.totMemAccLat 53352469871 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6581180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21784.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44072.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40534.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing -system.physmem.readRowHits 1168360 # Number of row buffer hits during reads -system.physmem.writeRowHits 561939 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 46.67 # Row buffer hit rate for writes -system.physmem.avgGap 17756571.38 # Average gap between requests -system.physmem.pageHitRate 64.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3585949920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1956619500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5602958400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3895302960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1230768339570 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27405197149500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31751822762730 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.815694 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45589938065590 # Time in different power states -system.physmem_0.memoryStateTime::REF 1585284480000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 1054044 # Number of row buffer hits during reads +system.physmem.writeRowHits 494841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.88 # Row buffer hit rate for writes +system.physmem.avgGap 19855034.61 # Average gap between requests +system.physmem.pageHitRate 64.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3265088400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1781546250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5069789400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3527867520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1219382745750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27491903982750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31834099035270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.747581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45734675361714 # Time in different power states +system.physmem_0.memoryStateTime::REF 1589554200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 299474968160 # Time in different power states +system.physmem_0.memoryStateTime::ACT 278338023286 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3524827320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1923268875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5837886600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3907258560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3100816442880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1224297828675 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27410873036250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31751180549160 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.802167 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45599398366763 # Time in different power states -system.physmem_1.memoryStateTime::REF 1585284480000 # Time in different power states +system.physmem_1.actEnergy 3129537600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1707585000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5196804600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3460818960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1215349697925 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27495441752250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31833454211535 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.734035 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45740562014248 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589554200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 290016828237 # Time in different power states +system.physmem_1.memoryStateTime::ACT 272450963752 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -374,9 +375,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,66 +408,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 101051 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 101051 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8300 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 78014 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 101044 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 101044 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 101044 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 86321 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22610.900013 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 19675.452020 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 23315.454382 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 84871 98.32% 98.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 161 0.19% 98.51% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1103 1.28% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 57 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 86321 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1368339312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -0.519630 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2079369704 151.96% 151.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -711030392 -51.96% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1368339312 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 78015 90.38% 90.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8300 9.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 86315 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101051 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 111926 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 111926 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10169 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86471 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 18 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 111908 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.232334 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 77.721788 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 111907 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 111908 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 96658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 95612 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 152 0.16% 99.08% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 763 0.79% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 18 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 23 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 96658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 444719432 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -3.785405 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2128162704 478.54% 478.54% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -1683443272 -378.54% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 444719432 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 86471 89.48% 89.48% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10169 10.52% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 96640 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111926 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101051 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 86315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111926 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96640 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 86315 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 187366 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96640 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 208566 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83039604 # DTB read hits -system.cpu0.dtb.read_misses 74585 # DTB read misses -system.cpu0.dtb.write_hits 76137695 # DTB write hits -system.cpu0.dtb.write_misses 26466 # DTB write misses +system.cpu0.dtb.read_hits 87929647 # DTB read hits +system.cpu0.dtb.read_misses 85158 # DTB read misses +system.cpu0.dtb.write_hits 79744109 # DTB write hits +system.cpu0.dtb.write_misses 26768 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37690 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37859 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4076 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3884 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10173 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83114189 # DTB read accesses -system.cpu0.dtb.write_accesses 76164161 # DTB write accesses +system.cpu0.dtb.perms_faults 10087 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 88014805 # DTB read accesses +system.cpu0.dtb.write_accesses 79770877 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159177299 # DTB hits -system.cpu0.dtb.misses 101051 # DTB misses -system.cpu0.dtb.accesses 159278350 # DTB accesses +system.cpu0.dtb.hits 167673756 # DTB hits +system.cpu0.dtb.misses 111926 # DTB misses +system.cpu0.dtb.accesses 167785682 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -496,238 +500,237 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 61250 # Table walker walks requested -system.cpu0.itb.walker.walksLong 61250 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 499 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55525 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 61250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 61250 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 61250 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 56024 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26762.682065 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22405.547992 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 30987.782128 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 54387 97.08% 97.08% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.07% 97.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1384 2.47% 99.62% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 41 0.07% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 72 0.13% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 22 0.04% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 55 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 61252 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61252 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 842 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54849 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 61252 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61252 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61252 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 55691 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 54619 98.08% 98.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.08% 98.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 884 1.59% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 24 0.04% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 35 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 56024 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1978837204 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1978837204 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1978837204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55525 99.11% 99.11% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 499 0.89% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 56024 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 55691 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54849 98.49% 98.49% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 842 1.51% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55691 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61250 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61250 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61252 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61252 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56024 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56024 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 117274 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 441205116 # ITB inst hits -system.cpu0.itb.inst_misses 61250 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55691 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55691 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 116943 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 467202921 # ITB inst hits +system.cpu0.itb.inst_misses 61252 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26202 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27100 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 441266366 # ITB inst accesses -system.cpu0.itb.hits 441205116 # DTB hits -system.cpu0.itb.misses 61250 # DTB misses -system.cpu0.itb.accesses 441266366 # DTB accesses -system.cpu0.numCycles 94949400739 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 467264173 # ITB inst accesses +system.cpu0.itb.hits 467202921 # DTB hits +system.cpu0.itb.misses 61252 # DTB misses +system.cpu0.itb.accesses 467264173 # DTB accesses +system.cpu0.numCycles 95205135902 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5268 # number of quiesce instructions executed -system.cpu0.committedInsts 440958495 # Number of instructions committed -system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 531836 # Number of float alu accesses -system.cpu0.num_func_calls 26928397 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 66358328 # number of instructions that are conditional controls -system.cpu0.num_int_insts 478066113 # number of integer instructions -system.cpu0.num_fp_insts 531836 # number of float instructions -system.cpu0.num_int_register_reads 691558601 # number of times the integer registers were read -system.cpu0.num_int_register_writes 378884875 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 853461 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 460304 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 113354931 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 113143261 # number of times the CC registers were written -system.cpu0.num_mem_refs 159167445 # number of memory refs -system.cpu0.num_load_insts 83034076 # Number of load instructions -system.cpu0.num_store_insts 76133369 # Number of store instructions -system.cpu0.num_idle_cycles 93735186324.296036 # Number of idle cycles -system.cpu0.num_busy_cycles 1214214414.703974 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012788 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987212 # Percentage of idle cycles -system.cpu0.Branches 98314010 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 359396375 69.13% 69.13% # Class of executed instruction -system.cpu0.op_class::IntMult 1169846 0.23% 69.36% # Class of executed instruction -system.cpu0.op_class::IntDiv 59621 0.01% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 75402 0.01% 69.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.38% # Class of executed instruction -system.cpu0.op_class::MemRead 83034076 15.97% 85.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 76133369 14.64% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 5123 # number of quiesce instructions executed +system.cpu0.committedInsts 466948479 # Number of instructions committed +system.cpu0.committedOps 548389991 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 504092161 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 464416 # Number of float alu accesses +system.cpu0.num_func_calls 27983491 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 70438282 # number of instructions that are conditional controls +system.cpu0.num_int_insts 504092161 # number of integer instructions +system.cpu0.num_fp_insts 464416 # number of float instructions +system.cpu0.num_int_register_reads 728885661 # number of times the integer registers were read +system.cpu0.num_int_register_writes 399652952 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 772857 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 344936 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 120908457 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 120465396 # number of times the CC registers were written +system.cpu0.num_mem_refs 167663327 # number of memory refs +system.cpu0.num_load_insts 87924608 # Number of load instructions +system.cpu0.num_store_insts 79738719 # Number of store instructions +system.cpu0.num_idle_cycles 93943889977.646729 # Number of idle cycles +system.cpu0.num_busy_cycles 1261245924.353277 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013248 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986752 # Percentage of idle cycles +system.cpu0.Branches 104008564 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 379698158 69.20% 69.20% # Class of executed instruction +system.cpu0.op_class::IntMult 1212773 0.22% 69.42% # Class of executed instruction +system.cpu0.op_class::IntDiv 66852 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 46447 0.01% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu0.op_class::MemRead 87924608 16.02% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 79738719 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 519868732 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5565465 # number of replacements -system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5565977 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.554484 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 6293402000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.695844 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983781 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.983781 # Average percentage of cache occupancy +system.cpu0.op_class::total 548687557 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5767473 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.102777 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 161665939 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5767985 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.028148 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.102777 # Average occupied blocks per requestor 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323920102 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77284320 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77284320 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 71935312 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 71935312 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 189585 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 189585 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125588 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 125588 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1730584 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1730584 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1699772 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1699772 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149219632 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149219632 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149409217 # number of overall hits -system.cpu0.dcache.overall_hits::total 149409217 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3014242 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3014242 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1370827 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1370827 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635540 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 635540 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 782263 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 782263 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168057 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 168057 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197269 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197269 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4385069 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4385069 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5020609 # number of overall misses -system.cpu0.dcache.overall_misses::total 5020609 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52298763500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 52298763500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 33070874000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 33070874000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65701301500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 65701301500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2847254500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2847254500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4866222000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4866222000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3481500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3481500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 85369637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 85369637500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 85369637500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 85369637500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80298562 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80298562 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73306139 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73306139 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 825125 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 825125 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 907851 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 907851 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898641 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1898641 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897041 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1897041 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 153604701 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 153604701 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154429826 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154429826 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037538 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037538 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018700 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018700 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770235 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770235 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.861665 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.861665 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088514 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088514 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028548 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028548 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032511 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032511 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.552311 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17350.552311 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 24124.761184 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24124.761184 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83988.762731 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83988.762731 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16942.195208 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16942.195208 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24667.950869 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24667.950869 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 341141490 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 341141490 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 81909684 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 81909684 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75364450 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75364450 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195602 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 195602 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 139312 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 139312 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1827663 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1827663 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798607 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1798607 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 157274134 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 157274134 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 157469736 # number of overall hits +system.cpu0.dcache.overall_hits::total 157469736 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3156555 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3156555 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1440320 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1440320 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651795 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 651795 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 776738 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 776738 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172749 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172749 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200464 # number of 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 85066239 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 85066239 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76804770 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76804770 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847397 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 847397 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 916050 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 916050 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2000412 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2000412 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1999071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1999071 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 161871009 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 161871009 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162718406 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 162718406 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037107 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037107 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018753 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018753 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769173 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769173 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.847921 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.847921 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086357 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086357 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100279 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100279 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028398 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028398 # miss rate for demand accesses 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miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19468.254091 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19468.254091 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17003.841068 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17003.841068 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19314.754262 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16916.192293 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,157 +739,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3771246 # number of writebacks -system.cpu0.dcache.writebacks::total 3771246 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 38597 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 38597 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21414 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21414 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46766 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46766 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 60011 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 60011 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 60011 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 60011 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2975645 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2975645 # number of ReadReq MSHR misses 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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795061500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4668993000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4668993000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77530831000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 77530831000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 95402981500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 95402981500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2879350000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2879350000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3091479000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3091479000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5970829000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5970829000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037057 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037057 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018408 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018408 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763424 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763424 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.861665 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.861665 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063883 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063883 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028157 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028157 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032086 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032086 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15656.879937 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15656.879937 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22929.610505 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22929.610505 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 28372.095663 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 28372.095663 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82988.762731 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82988.762731 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14799.626518 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14799.626518 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23668.153638 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23668.153638 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5767473 # number of writebacks +system.cpu0.dcache.writebacks::total 5767473 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27282 # number of ReadReq MSHR hits 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miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2690935500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2690935500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2795849000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2795849000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5486784500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5486784500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036786 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018476 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767658 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767658 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.847921 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.847921 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064048 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064048 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100279 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100279 # mshr miss rate for StoreCondReq accesses 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24474.443937 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 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166248.893220 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 166248.893220 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537 # average WriteReq mshr uncacheable latency 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overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11188.865715 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11188.865715 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11188.865715 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 939581550 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 939581550 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 462027213 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 462027213 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 462027213 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 462027213 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 462027213 # number of overall hits +system.cpu0.icache.overall_hits::total 462027213 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5175708 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10688.865715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10688.865715 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138060.915942 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138060.915942 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138060.915942 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 54748691500 # number of ReadReq MSHR miss cycles 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cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011078 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011078 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011078 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7344223 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7344239 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7857654 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7857701 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 976449 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2329725 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16186.065873 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 18053337 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2345760 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.696157 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 55834398000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6981.301122 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.056568 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 81.620115 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4075.206909 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4054.876060 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 929.005098 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.426105 # Average percentage of cache occupancy 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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44836.358961 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56365.166062 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 36874.751360 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36874.751360 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19165.201377 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19165.201377 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 261708.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261708.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60947.703773 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60947.703773 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33423.617392 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38708.371824 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38708.371824 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107389.530158 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107389.530158 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40350.080612 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41647.820229 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 48495.747736 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33423.617392 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43246.250642 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56365.166062 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44631.000991 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158474.907493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138551.521822 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158538.938719 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 158538.938719 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130560.915942 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 158508.102464 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143259.843117 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226475 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 22509328 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11536373 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 848 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 485130 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 485124 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 537841 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9675681 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 18620 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 18619 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 5107009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 8757288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 798537 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 405076 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363715 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 481157 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 40 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1220841 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1155337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5319695 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4658319 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 788798 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 781028 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16044388 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17944373 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 336960 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 515556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34841277 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 340632980 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 559762054 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1230712 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1770072 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 903395818 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5410368 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 27976627 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.025738 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.158355 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 22685684 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11636633 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 725 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1868386 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1868205 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 181 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 566458 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9760546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16479 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5331858 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7134877 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2347214 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 886122 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 438453 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361903 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 524601 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1264261 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1203854 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5175708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4797612 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 779730 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 774618 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15612584 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18673898 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 348811 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 599734 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 35235027 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662612564 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 703409885 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328368 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2198296 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1369549113 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6346450 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 18158816 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.116500 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.320855 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 27256564 97.43% 97.43% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 720057 2.57% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 16043491 88.35% 88.35% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2115144 11.65% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 181 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 27976627 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 15196832497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 18158816 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 22462112497 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 183439903 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 223807892 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 8022667500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7806687000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7935130422 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8283648998 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 183121000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 182765499 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 294297000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 324947000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1395,69 +1396,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 111674 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 111674 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10360 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85053 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 111653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.241821 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 61.696123 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 111651 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 111653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 95434 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21055.163778 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19260.807562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16557.880011 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 94629 99.16% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 150 0.16% 99.31% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 551 0.58% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 92112 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 92112 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7185 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70441 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 92107 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.086856 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 26.359895 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 92106 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 92107 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 77631 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 76846 98.99% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 174 0.22% 99.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 527 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 95434 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 10744163364 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.061708 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -663005280 -6.17% -6.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 11407168644 106.17% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 10744163364 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85053 89.14% 89.14% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10360 10.86% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 95413 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 111674 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 77631 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -5456316576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.616394 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.486264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2093077220 38.36% 38.36% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3363239356 61.64% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -5456316576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 70442 90.74% 90.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7185 9.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 77627 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92112 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 111674 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 95413 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92112 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77627 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 95413 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 207087 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77627 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 169739 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82869257 # DTB read hits -system.cpu1.dtb.read_misses 83659 # DTB read misses -system.cpu1.dtb.write_hits 74681159 # DTB write hits -system.cpu1.dtb.write_misses 28015 # DTB write misses +system.cpu1.dtb.read_hits 76812549 # DTB read hits +system.cpu1.dtb.read_misses 67403 # DTB read misses +system.cpu1.dtb.write_hits 69811450 # DTB write hits +system.cpu1.dtb.write_misses 24709 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37721 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34729 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4459 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4304 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10437 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 82952916 # DTB read accesses -system.cpu1.dtb.write_accesses 74709174 # DTB write accesses +system.cpu1.dtb.perms_faults 9295 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 76879952 # DTB read accesses +system.cpu1.dtb.write_accesses 69836159 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 157550416 # DTB hits -system.cpu1.dtb.misses 111674 # DTB misses -system.cpu1.dtb.accesses 157662090 # DTB accesses +system.cpu1.dtb.hits 146623999 # DTB hits +system.cpu1.dtb.misses 92112 # DTB misses +system.cpu1.dtb.accesses 146716111 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1487,235 +1488,236 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 54727 # Table walker walks requested -system.cpu1.itb.walker.walksLong 54727 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 669 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48424 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 54727 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 54727 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 54727 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49093 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 23909.080724 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21093.336913 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23672.932713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 48315 98.42% 98.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 33 0.07% 98.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 627 1.28% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 24 0.05% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49093 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1309982220 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1309982220 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1309982220 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 48424 98.64% 98.64% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 669 1.36% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49093 # Table walker page sizes translated +system.cpu1.itb.walker.walks 54749 # Table walker walks requested +system.cpu1.itb.walker.walksLong 54749 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 360 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 54749 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 54749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 54749 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 48865 98.58% 98.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 34 0.07% 98.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 581 1.17% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 14 0.03% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 25 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49571 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 99.27% 99.27% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 360 0.73% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49571 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54727 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54727 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54749 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54749 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49093 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49093 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 103820 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 441006552 # ITB inst hits -system.cpu1.itb.inst_misses 54727 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49571 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49571 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 104320 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 406021553 # ITB inst hits +system.cpu1.itb.inst_misses 54749 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42668 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26047 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24319 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 441061279 # ITB inst accesses -system.cpu1.itb.hits 441006552 # DTB hits -system.cpu1.itb.misses 54727 # DTB misses -system.cpu1.itb.accesses 441061279 # DTB accesses -system.cpu1.numCycles 94949400719 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 406076302 # ITB inst accesses +system.cpu1.itb.hits 406021553 # DTB hits +system.cpu1.itb.misses 54749 # DTB misses +system.cpu1.itb.accesses 406076302 # DTB accesses +system.cpu1.numCycles 95205135925 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13508 # number of quiesce instructions executed -system.cpu1.committedInsts 440696565 # Number of instructions committed -system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 365483 # Number of float alu accesses -system.cpu1.num_func_calls 25816030 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67531060 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474820793 # number of integer instructions -system.cpu1.num_fp_insts 365483 # number of float instructions -system.cpu1.num_int_register_reads 694878928 # number of times the integer registers were read -system.cpu1.num_int_register_writes 377300064 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 605102 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 276864 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 116712375 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 116303175 # number of times the CC registers were written -system.cpu1.num_mem_refs 157542729 # number of memory refs -system.cpu1.num_load_insts 82867724 # Number of load instructions -system.cpu1.num_store_insts 74675005 # Number of store instructions -system.cpu1.num_idle_cycles 93871458813.181076 # Number of idle cycles -system.cpu1.num_busy_cycles 1077941905.818921 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011353 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988647 # Percentage of idle cycles -system.cpu1.Branches 98303933 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 359137164 69.35% 69.35% # Class of executed instruction -system.cpu1.op_class::IntMult 1056908 0.20% 69.56% # Class of executed instruction -system.cpu1.op_class::IntDiv 59454 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36204 0.01% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::MemRead 82867724 16.00% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 74675005 14.42% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 14029 # number of quiesce instructions executed +system.cpu1.committedInsts 405727323 # Number of instructions committed +system.cpu1.committedOps 478325144 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 439907771 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 446670 # Number of float alu accesses +system.cpu1.num_func_calls 24605699 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 61596178 # number of instructions that are conditional controls +system.cpu1.num_int_insts 439907771 # number of integer instructions +system.cpu1.num_fp_insts 446670 # number of float instructions +system.cpu1.num_int_register_reads 637924838 # number of times the integer registers were read +system.cpu1.num_int_register_writes 348926241 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 708486 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 403472 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 104772444 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 104573998 # number of times the CC registers were written +system.cpu1.num_mem_refs 146614371 # number of memory refs +system.cpu1.num_load_insts 76808885 # Number of load instructions +system.cpu1.num_store_insts 69805486 # Number of store instructions +system.cpu1.num_idle_cycles 94195407146.248016 # Number of idle cycles +system.cpu1.num_busy_cycles 1009728778.751979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010606 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989394 # Percentage of idle cycles +system.cpu1.Branches 90553045 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 330876771 69.13% 69.13% # Class of executed instruction +system.cpu1.op_class::IntMult 1002715 0.21% 69.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 57816 0.01% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 67767 0.01% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.37% # Class of executed instruction +system.cpu1.op_class::MemRead 76808885 16.05% 85.42% # Class of executed instruction +system.cpu1.op_class::MemWrite 69805486 14.58% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 517832459 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5147651 # number of replacements -system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5148159 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.564853 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8409197794000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 420.489425 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.821268 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.821268 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 443 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 320234661 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 320234661 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 77182580 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 77182580 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70763723 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70763723 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181716 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 181716 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 197136 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 197136 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768276 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1768276 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1725683 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1725683 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 147946303 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 147946303 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 148128019 # number of overall hits -system.cpu1.dcache.overall_hits::total 148128019 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2911211 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2911211 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1304261 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1304261 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 646630 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 646630 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 461157 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 461157 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158092 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 158092 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198973 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 198973 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4215472 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4215472 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4862102 # number of overall misses -system.cpu1.dcache.overall_misses::total 4862102 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46228111000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 46228111000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27445585000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 27445585000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 22477695000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 22477695000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2400515000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2400515000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4867748500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4867748500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2101500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2101500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 73673696000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 73673696000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 73673696000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 73673696000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80093791 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80093791 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72067984 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72067984 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828346 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 828346 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 658293 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 658293 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1926368 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1926368 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1924656 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1924656 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 152161775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 152161775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152990121 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152990121 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036348 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036348 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018098 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018098 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780628 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780628 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.700535 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.700535 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082067 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082067 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103381 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103381 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027704 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027704 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031780 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031780 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15879.340591 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15879.340591 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21043.015930 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21043.015930 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 48741.957728 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 48741.957728 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15184.291425 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15184.291425 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24464.367025 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24464.367025 # average StoreCondReq miss latency +system.cpu1.op_class::total 478619483 # Class of executed instruction +system.cpu1.dcache.tags.replacements 4731492 # number of replacements +system.cpu1.dcache.tags.tagsinuse 440.215275 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 141682703 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4732003 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.941381 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.215275 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.859795 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.859795 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 297963795 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 297963795 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 71617652 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 71617652 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66171444 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66171444 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174206 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 174206 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 185116 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 185116 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1590024 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1590024 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1548743 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1548743 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 137789096 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 137789096 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 137963302 # number of overall hits +system.cpu1.dcache.overall_hits::total 137963302 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2694357 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2694357 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1213090 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1213090 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 558664 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 558664 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466794 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 466794 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 154053 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 154053 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194127 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 194127 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3907447 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3907447 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4466111 # number of overall misses +system.cpu1.dcache.overall_misses::total 4466111 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40157954500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 40157954500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28157091500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 28157091500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20750751000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 20750751000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2380134500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2380134500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5345117000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5345117000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6929500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6929500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 68315046000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 68315046000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 68315046000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 68315046000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 74312009 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 74312009 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 67384534 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 67384534 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 732870 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 732870 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 651910 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 651910 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1744077 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1744077 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1742870 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1742870 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 141696543 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 141696543 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 142429413 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 142429413 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036257 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036257 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018002 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018002 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762296 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762296 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716041 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716041 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088329 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088329 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111384 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111384 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027576 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027576 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031357 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031357 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17476.974346 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17476.974346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15152.643034 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15152.643034 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17483.294335 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15296.316191 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1724,158 +1726,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3396408 # number of writebacks -system.cpu1.dcache.writebacks::total 3396408 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16912 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16912 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 462 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 462 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41725 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41725 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 17374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 17374 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 17374 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 17374 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2894299 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2894299 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1303799 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1303799 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 646630 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 646630 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 461157 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 461157 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116367 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116367 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198973 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 198973 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4198098 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4198098 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4844728 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4844728 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 20770 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 20770 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19330 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19330 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40100 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40100 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41851387000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41851387000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26109084500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26109084500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14515592000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14515592000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 22016538000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 22016538000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587242500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587242500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4668803500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4668803500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2073500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2073500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67960471500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 67960471500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 82476063500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 82476063500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3614060000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3614060000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3361466500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3361466500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975526500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6975526500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036136 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036136 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780628 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780628 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.700535 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.700535 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103381 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103381 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027590 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027590 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031667 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031667 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14459.939004 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14459.939004 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20025.390800 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20025.390800 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22448.064581 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22448.064581 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 47741.957728 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 47741.957728 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13639.970954 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13639.970954 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23464.507747 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23464.507747 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4731492 # number of writebacks +system.cpu1.dcache.writebacks::total 4731492 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13909 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 13909 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 323 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 323 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44168 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44168 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 14232 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 14232 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 14232 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 14232 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2680448 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2680448 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1212767 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1212767 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 558664 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 558664 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466794 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 466794 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109885 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109885 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194127 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 194127 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3893215 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3893215 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4451879 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4451879 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23611 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46231 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36382655000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36382655000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26928760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26928760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12609688500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12609688500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20283957000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20283957000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1540230500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1540230500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5151064000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5151064000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6855500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6855500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63311415500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 63311415500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75921104000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 75921104000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4287453000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4287453000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4160988000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4160988000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8448441000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8448441000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036070 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036070 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762296 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762296 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716041 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716041 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063005 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063005 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111384 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111384 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027476 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027476 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031257 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031257 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16188.395673 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16188.395673 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17023.879050 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17023.879050 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174003.851709 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174003.851709 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173898.939472 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173898.939472 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173953.279302 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173953.279302 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971 # average overall mshr miss latency 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-system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 886692857 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 886692857 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 436326798 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 436326798 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 436326798 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 436326798 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 436326798 # number of overall hits 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0.010612 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.010612 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010612 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.010612 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11314.949461 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11314.949461 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11314.949461 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11314.949461 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11314.949461 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 816875196 # Number of tag accesses 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406021553 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 406021553 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 406021553 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011901 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011901 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011901 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011901 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011901 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011901 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10845.895047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10845.895047 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1884,255 +1885,252 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4679754 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4679754 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4679754 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4679754 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4679754 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4679754 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 4831573 # number of writebacks +system.cpu1.icache.writebacks::total 4831573 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4832090 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4832090 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4832090 # number of demand (read+write) MSHR misses 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cycles -system.cpu1.icache.demand_mshr_miss_latency::total 50611303500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50611303500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 50611303500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14521500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14521500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14521500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 14521500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010612 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.010612 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010612 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.010612 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10814.949568 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10814.949568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10814.949568 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132013.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132013.636364 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132013.636364 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49992296000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49992296000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49992296000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49992296000 # number of demand (read+write) MSHR miss cycles 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prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 899040 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2034185 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13437.783654 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 16644740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2049737 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.120427 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9820320151000 # Cycle when the warmup percentage was hit. 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-system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578186 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578186 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167683 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038833 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.054473 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109572 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234407 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.228460 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.228460 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248162 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248162 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.568061 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.568061 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156949 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.237575 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38118.409294 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64334.141163 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 34097.356432 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34097.356432 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18821.101327 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18821.101327 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 232874.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 232874.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50420.822755 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50420.822755 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30619.744953 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32089.784038 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32089.784038 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69395.492181 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69395.492181 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34058.404080 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36311.034338 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40505.253698 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30619.744953 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35572.518637 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64334.141163 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42965.221788 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166003.851709 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165785.272989 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166398.939472 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166398.939472 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124513.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 166194.301746 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 166080.278538 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220047 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 20369965 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10454543 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 477453 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 477447 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 508237 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 8929000 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 19330 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 19330 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4444983 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 8042862 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 852297 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 366971 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 363003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 446864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1185291 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1125998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4679754 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4554667 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 467005 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 459760 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14038440 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16622497 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 296146 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 569967 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 31527050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 299504632 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 528992733 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1062248 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1967800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 831527413 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5090691 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25485456 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.028305 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.165844 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 19832170 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10173061 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1095 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1632026 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1631848 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 178 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 456067 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 8724452 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 22620 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 22620 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 3978006 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6573071 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2099842 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 741149 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 395876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358205 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 460652 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1084167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1021480 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4832090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4231593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 474723 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 464424 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14495311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15429373 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 311743 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 489874 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 30726301 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 618432504 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588237954 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1183896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1770272 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1209624626 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5375046 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 15685523 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.117781 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322383 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 24764094 97.17% 97.17% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 721356 2.83% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 13838252 88.22% 88.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1847093 11.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 178 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25485456 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 13733891999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15685523 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 19622729498 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 167318993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175341179 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7019739500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7248245000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7617418010 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7009474930 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 163365000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 163756499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 323992499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 268590000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40317 # Transaction distribution -system.iobus.trans_dist::ReadResp 40317 # Transaction distribution -system.iobus.trans_dist::WriteReq 136619 # Transaction distribution -system.iobus.trans_dist::WriteResp 136619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47666 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40469 # Transaction distribution +system.iobus.trans_dist::ReadResp 40469 # Transaction distribution +system.iobus.trans_dist::WriteReq 137017 # Transaction distribution +system.iobus.trans_dist::WriteResp 137017 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2378,18 +2369,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122600 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231764 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231764 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353872 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48006 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2399,110 +2390,110 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155707 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156143 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36194000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513637 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37181500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26640000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 37419000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565735913 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 566572505 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92712000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93098000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148204000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115577 # number of replacements -system.iocache.tags.tagsinuse 11.281807 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9206321837000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.831702 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.450105 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465632 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705113 # Average percentage of cache occupancy +system.iocache.tags.replacements 115869 # number of replacements +system.iocache.tags.tagsinuse 11.294988 # Cycle average of tags in use +system.iocache.tags.total_refs 4 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115885 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9206093766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.821408 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.473580 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.467099 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705937 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040721 # Number of tag accesses -system.iocache.tags.data_accesses 1040721 # Number of data accesses +system.iocache.tags.tag_accesses 1043293 # Number of tag accesses +system.iocache.tags.data_accesses 1043293 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses -system.iocache.demand_misses::total 8908 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses +system.iocache.demand_misses::total 8938 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8868 # number of overall misses -system.iocache.overall_misses::total 8908 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1668103306 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1673298306 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8898 # number of overall misses +system.iocache.overall_misses::total 8938 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1681517592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1686717092 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13929903607 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13929903607 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1668103306 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1673667306 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1668103306 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1673667306 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 14021691413 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 14021691413 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1681517592 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1687086092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1681517592 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1687086092 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2516,55 +2507,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188103.665539 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187905.480741 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188776.395299 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130517.798581 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130517.798581 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 187883.622137 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188103.665539 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 187883.622137 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33272 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188754.317744 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188754.317744 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36073 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3491 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3617 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.530793 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.973182 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106694 # number of writebacks -system.iocache.writebacks::total 106694 # number of writebacks +system.iocache.writebacks::writebacks 106957 # number of writebacks +system.iocache.writebacks::total 106957 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR 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number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236617592 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1239967092 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8593503607 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8593503607 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1224703306 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1228267306 # number of demand (read+write) MSHR miss cycles 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138103.665539 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137905.480741 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80517.798581 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80517.798581 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 138103.665539 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 137883.622137 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1400633 # number of replacements -system.l2c.tags.tagsinuse 63705.794368 # Cycle average of tags in use -system.l2c.tags.total_refs 5028924 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1460176 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.444053 # Average number of references to valid blocks. +system.l2c.tags.replacements 1210264 # number of replacements +system.l2c.tags.tagsinuse 62755.466878 # Cycle average of tags in use +system.l2c.tags.total_refs 5212344 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1269955 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.104353 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 18928.346727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 167.390384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 216.986390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4428.367994 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11717.643832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11340.141344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 156.822011 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 230.353384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2614.971757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4665.203250 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9239.567296 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.288824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002554 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003311 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.067572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.178797 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173037 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003515 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.039901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.071185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.972073 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10769 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 294 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48480 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 409 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 10095 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 294 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41942 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.164322 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004486 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.739746 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 64230359 # Number of tag accesses -system.l2c.tags.data_accesses 64230359 # Number of data accesses -system.l2c.Writeback_hits::writebacks 2314762 # number of Writeback hits -system.l2c.Writeback_hits::total 2314762 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 28623 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 30874 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 59497 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6079 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5789 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11868 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 160432 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 145801 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 306233 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5516 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4550 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 461560 # number of ReadSharedReq hits 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-system.l2c.demand_hits::cpu0.l2cache.prefetcher 265120 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 473807 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 670504 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 267683 # number of demand (read+write) hits -system.l2c.demand_hits::total 2838949 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5516 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4550 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461560 # number of overall hits -system.l2c.overall_hits::cpu0.data 682033 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 265120 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4769 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3407 # number of overall hits -system.l2c.overall_hits::cpu1.inst 473807 # number of overall hits -system.l2c.overall_hits::cpu1.data 670504 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 267683 # number of overall hits -system.l2c.overall_hits::total 2838949 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 45739 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 41402 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87141 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10551 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 10041 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 20592 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 478288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 167740 # number of ReadExReq misses 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# number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1990 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2246 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 51456 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 634336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 188933 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1431 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1351 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 38962 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 269765 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 234272 # number of demand (read+write) misses -system.l2c.demand_misses::total 1424742 # number of demand (read+write) misses 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 8916 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1774 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 10274 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 36522 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.161209 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.746078 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66950820 # Number of tag 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+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315848 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 81299 # Transaction distribution -system.membus.trans_dist::ReadResp 868698 # Transaction distribution -system.membus.trans_dist::WriteReq 37949 # Transaction distribution -system.membus.trans_dist::WriteResp 37949 # Transaction distribution -system.membus.trans_dist::Writeback 1203792 # Transaction distribution -system.membus.trans_dist::CleanEvict 220565 # Transaction distribution -system.membus.trans_dist::UpgradeReq 376258 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 321655 # Transaction distribution -system.membus.trans_dist::UpgradeResp 113911 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 660250 # Transaction distribution -system.membus.trans_dist::ReadExResp 639853 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 787399 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122600 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 82463 # Transaction distribution +system.membus.trans_dist::ReadResp 738269 # Transaction distribution +system.membus.trans_dist::WriteReq 39099 # Transaction distribution +system.membus.trans_dist::WriteResp 39099 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1078222 # Transaction distribution +system.membus.trans_dist::CleanEvict 196131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 410883 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321341 # Transaction distribution +system.membus.trans_dist::UpgradeResp 158448 # Transaction distribution +system.membus.trans_dist::ReadExReq 644070 # Transaction distribution +system.membus.trans_dist::ReadExResp 620815 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 655806 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106983 # Transaction distribution +system.membus.trans_dist::InvalidateResp 106983 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5071225 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5218123 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341689 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341689 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5559812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155707 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28306 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4701222 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4852748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5195460 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156143 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 161136300 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 161340623 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7239232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7239232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 168579855 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 607627 # Total snoops (count) -system.membus.snoop_fanout::samples 3798608 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56612 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143440556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 143653515 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7262336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 150915851 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 600183 # Total snoops (count) +system.membus.snoop_fanout::samples 3537604 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3798608 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3537604 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3798608 # Request fanout histogram -system.membus.reqLayer0.occupancy 101169498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3537604 # Request fanout histogram +system.membus.reqLayer0.occupancy 101645000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20972999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 23516499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8203462570 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7437675124 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7924808506 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7217345032 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 230064369 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 228825593 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3195,11 +3187,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3238,52 +3230,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 10304168 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5242935 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1823032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 155703 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 143721 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11982 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 81301 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4203748 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37949 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37949 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 3518592 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1268318 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 429580 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 333523 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 763103 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 68 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 68 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1086913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1086913 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4129694 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7476293 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6448186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 13924479 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230559242 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 190965829 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 421525071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3161630 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 12055300 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.328437 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.471756 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 10517449 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5725465 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1766756 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 114752 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 104186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 10566 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 82465 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3940978 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 39099 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 39099 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3582727 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1240251 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 683521 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 394463 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1077983 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 128 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1083401 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1083400 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3865739 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106983 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8168699 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6135080 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 14303779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 247232417 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 172105066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 419337483 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2918298 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7581961 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.362851 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483712 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8107870 67.26% 67.26% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3935448 32.64% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11982 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4841404 63.85% 63.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2729991 36.01% 99.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 10566 0.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 12055300 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 7945670452 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7581961 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8230397518 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2561165 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2646637 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4404072117 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4512530115 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3899520231 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3554923231 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index b90977aa0..414f238d4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811426 # Number of seconds simulated -sim_ticks 51811426272500 # Number of ticks simulated -final_tick 51811426272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811412 # Number of seconds simulated +sim_ticks 51811412441500 # Number of ticks simulated +final_tick 51811412441500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 429786 # Simulator instruction rate (inst/s) -host_op_rate 505081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26846252166 # Simulator tick rate (ticks/s) -host_mem_usage 669952 # Number of bytes of host memory used -host_seconds 1929.93 # Real time elapsed on the host -sim_insts 829457901 # Number of instructions simulated -sim_ops 974772546 # Number of ops (including micro ops) simulated +host_inst_rate 619887 # Simulator instruction rate (inst/s) +host_op_rate 728480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38746850862 # Simulator tick rate (ticks/s) +host_mem_usage 721116 # Number of bytes of host memory used +host_seconds 1337.18 # Real time elapsed on the host +sim_insts 828899207 # Number of instructions simulated +sim_ops 974107036 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 136896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 149440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4672052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65294216 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 405248 # Number of bytes read from this memory -system.physmem.bytes_read::total 70657852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4672052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4672052 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61426304 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 141632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4651380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65025608 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 401792 # Number of bytes read from this memory +system.physmem.bytes_read::total 70353980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4651380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4651380 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61199552 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61446884 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2139 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2335 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 113408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1020235 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6332 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1144449 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 959786 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61220132 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2213 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 113085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1016038 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6278 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1139701 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 956243 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 962359 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 90174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1260228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1363750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1185574 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 958816 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 2734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 89775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1255044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1357886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89775 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1181198 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1185972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1185574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1260625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7822 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2549722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1144449 # Number of read requests accepted -system.physmem.writeReqs 962359 # Number of write requests accepted -system.physmem.readBursts 1144449 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 962359 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 73193536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 51200 # Total number of bytes read from write queue -system.physmem.bytesWritten 61446016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70657852 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61446884 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 800 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 140011 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69107 # Per bank write bursts -system.physmem.perBankRdBursts::1 74090 # Per bank write bursts -system.physmem.perBankRdBursts::2 73242 # Per bank write bursts -system.physmem.perBankRdBursts::3 69271 # Per bank write bursts -system.physmem.perBankRdBursts::4 67156 # Per bank write bursts -system.physmem.perBankRdBursts::5 73972 # Per bank write bursts -system.physmem.perBankRdBursts::6 66324 # Per bank write bursts -system.physmem.perBankRdBursts::7 66322 # Per bank write bursts -system.physmem.perBankRdBursts::8 69640 # Per bank write bursts -system.physmem.perBankRdBursts::9 111279 # Per bank write bursts -system.physmem.perBankRdBursts::10 69249 # Per bank write bursts -system.physmem.perBankRdBursts::11 69472 # Per bank write bursts -system.physmem.perBankRdBursts::12 65127 # Per bank write bursts -system.physmem.perBankRdBursts::13 68635 # Per bank write bursts -system.physmem.perBankRdBursts::14 67352 # Per bank write bursts -system.physmem.perBankRdBursts::15 63411 # Per bank write bursts -system.physmem.perBankWrBursts::0 57809 # Per bank write bursts -system.physmem.perBankWrBursts::1 62464 # Per bank write bursts -system.physmem.perBankWrBursts::2 62675 # Per bank write bursts -system.physmem.perBankWrBursts::3 60788 # Per bank write bursts -system.physmem.perBankWrBursts::4 58616 # Per bank write bursts -system.physmem.perBankWrBursts::5 63580 # Per bank write bursts -system.physmem.perBankWrBursts::6 58138 # Per bank write bursts -system.physmem.perBankWrBursts::7 59016 # Per bank write bursts -system.physmem.perBankWrBursts::8 60306 # Per bank write bursts -system.physmem.perBankWrBursts::9 62192 # Per bank write bursts -system.physmem.perBankWrBursts::10 60798 # Per bank write bursts -system.physmem.perBankWrBursts::11 61491 # Per bank write bursts -system.physmem.perBankWrBursts::12 56659 # Per bank write bursts -system.physmem.perBankWrBursts::13 60390 # Per bank write bursts -system.physmem.perBankWrBursts::14 59031 # Per bank write bursts -system.physmem.perBankWrBursts::15 56141 # Per bank write bursts +system.physmem.bw_write::total 1181596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1181198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 2734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1255441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2539481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1139701 # Number of read requests accepted +system.physmem.writeReqs 958816 # Number of write requests accepted +system.physmem.readBursts 1139701 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 958816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72891072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 49792 # Total number of bytes read from write queue +system.physmem.bytesWritten 61218752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70353980 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 61220132 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 778 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 295779 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 70381 # Per bank write bursts +system.physmem.perBankRdBursts::1 75813 # Per bank write bursts +system.physmem.perBankRdBursts::2 71139 # Per bank write bursts +system.physmem.perBankRdBursts::3 67493 # Per bank write bursts +system.physmem.perBankRdBursts::4 63564 # Per bank write bursts +system.physmem.perBankRdBursts::5 70698 # Per bank write bursts +system.physmem.perBankRdBursts::6 65929 # Per bank write bursts +system.physmem.perBankRdBursts::7 63583 # Per bank write bursts +system.physmem.perBankRdBursts::8 66194 # Per bank write bursts +system.physmem.perBankRdBursts::9 109788 # Per bank write bursts +system.physmem.perBankRdBursts::10 68376 # Per bank write bursts +system.physmem.perBankRdBursts::11 70520 # Per bank write bursts +system.physmem.perBankRdBursts::12 68080 # Per bank write bursts +system.physmem.perBankRdBursts::13 71994 # Per bank write bursts +system.physmem.perBankRdBursts::14 69489 # Per bank write bursts +system.physmem.perBankRdBursts::15 65882 # Per bank write bursts +system.physmem.perBankWrBursts::0 58404 # Per bank write bursts +system.physmem.perBankWrBursts::1 62356 # Per bank write bursts +system.physmem.perBankWrBursts::2 60883 # Per bank write bursts +system.physmem.perBankWrBursts::3 59981 # Per bank write bursts +system.physmem.perBankWrBursts::4 56389 # Per bank write bursts +system.physmem.perBankWrBursts::5 60703 # Per bank write bursts +system.physmem.perBankWrBursts::6 57931 # Per bank write bursts +system.physmem.perBankWrBursts::7 57426 # Per bank write bursts +system.physmem.perBankWrBursts::8 58562 # Per bank write bursts +system.physmem.perBankWrBursts::9 60878 # Per bank write bursts +system.physmem.perBankWrBursts::10 59750 # Per bank write bursts +system.physmem.perBankWrBursts::11 62184 # Per bank write bursts +system.physmem.perBankWrBursts::12 59419 # Per bank write bursts +system.physmem.perBankWrBursts::13 62742 # Per bank write bursts +system.physmem.perBankWrBursts::14 60987 # Per bank write bursts +system.physmem.perBankWrBursts::15 57948 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 31 # Number of times write queue was full causing retry -system.physmem.totGap 51811423590500 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 51811409612500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1101333 # Read request sizes (log2) +system.physmem.readPktSize::6 1096585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 959786 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1115953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.writePktSize::6 956243 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1112094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,160 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 56683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 63120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 58229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 56389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 55725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 55034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 451899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.940982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.093990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.963355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 180364 39.91% 39.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 110273 24.40% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39544 8.75% 73.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23126 5.12% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15873 3.51% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11951 2.64% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9990 2.21% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8720 1.93% 88.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 52058 11.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 451899 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54067 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.152052 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.366692 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 54065 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 13699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 56677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 57597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 58593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 58374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 57736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 55140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 155 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 450541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.663263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.634069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.395643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 180604 40.09% 40.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 109821 24.38% 64.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39191 8.70% 73.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22619 5.02% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15643 3.47% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11800 2.62% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10101 2.24% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8767 1.95% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51995 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 450541 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 53849 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.149826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 337.005181 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 53847 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54067 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54067 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.757486 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.129918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.530147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51801 95.81% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 269 0.50% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 0.13% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 325 0.60% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.08% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 331 0.61% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 216 0.40% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 22 0.04% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 68 0.13% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 136 0.25% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 36 0.07% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 464 0.86% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 28 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 146 0.27% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 21 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54067 # Writes before turning the bus around for reads -system.physmem.totQLat 14370740504 # Total ticks spent queuing -system.physmem.totMemAccLat 35814159254 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5718245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12565.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 53849 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 53849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.763431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.132779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.573717 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51569 95.77% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 271 0.50% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 82 0.15% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 312 0.58% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 52 0.10% 97.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 350 0.65% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 234 0.43% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 17 0.03% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 58 0.11% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 145 0.27% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 23 0.04% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 22 0.04% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 441 0.82% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 31 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 53849 # Writes before turning the bus around for reads +system.physmem.totQLat 14314490470 # Total ticks spent queuing +system.physmem.totMemAccLat 35669296720 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5694615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12568.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31315.69 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31318.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.25 # Average write queue length when enqueuing -system.physmem.readRowHits 921781 # Number of row buffer hits during reads -system.physmem.writeRowHits 730062 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.04 # Row buffer hit rate for writes -system.physmem.avgGap 24592380.32 # Average gap between requests -system.physmem.pageHitRate 78.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1754978400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 957577500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4363975200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3130397280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1298615760765 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29947715800500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34640608612845 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.590209 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49820119093739 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730097200000 # Time in different power states +system.physmem.avgWrQLen 27.89 # Average write queue length when enqueuing +system.physmem.readRowHits 918030 # Number of row buffer hits during reads +system.physmem.writeRowHits 726894 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.99 # Row buffer hit rate for writes +system.physmem.avgGap 24689535.33 # Average gap between requests +system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1704243240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 929894625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4279041000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3071993040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1294968358125 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29950905933000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34639928569110 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.577285 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49825452803142 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730096680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 261204441261 # Time in different power states +system.physmem_0.memoryStateTime::ACT 255862301858 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1661378040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 906505875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4556448000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3091011840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1293042304755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29952604797000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34639932568710 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.577161 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49828251258491 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730097200000 # Time in different power states +system.physmem_1.actEnergy 1701846720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 928587000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4604519400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3126405600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1295387816850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29950537986750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34640356268400 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.585540 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49824790858475 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730096680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 253077157009 # Time in different power states +system.physmem_1.memoryStateTime::ACT 256517624025 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -366,69 +367,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 184770 # Table walker walks requested -system.cpu.dtb.walker.walksLong 184770 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12350 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144149 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 184753 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.216505 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.872440 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 184751 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 185269 # Table walker walks requested +system.cpu.dtb.walker.walksLong 185269 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12948 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144056 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 185250 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.215924 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.777306 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 185248 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 184753 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 156516 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24678.339595 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20707.909662 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17878.729982 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155309 99.23% 99.23% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1041 0.67% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 36 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 39 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 156516 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -8954848740 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.174586 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1563388704 -17.46% -17.46% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -10518237444 117.46% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -8954848740 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144150 92.11% 92.11% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12350 7.89% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 156500 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 184770 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 185250 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 157023 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24782.458621 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20866.161950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18013.175833 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 155872 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 991 0.63% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 17 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 22 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 157023 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 3934185148 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.600903 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489713 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1570120704 39.91% 39.91% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 2364064444 60.09% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 3934185148 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 144057 91.75% 91.75% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12948 8.25% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 157005 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185269 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 184770 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156500 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185269 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157005 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156500 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 341270 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157005 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 342274 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156218154 # DTB read hits -system.cpu.dtb.read_misses 137197 # DTB read misses -system.cpu.dtb.write_hits 141774250 # DTB write hits -system.cpu.dtb.write_misses 47573 # DTB write misses +system.cpu.dtb.read_hits 156094559 # DTB read hits +system.cpu.dtb.read_misses 137688 # DTB read misses +system.cpu.dtb.write_hits 141675607 # DTB write hits +system.cpu.dtb.write_misses 47581 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70344 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 70732 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7209 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6720 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18555 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156355351 # DTB read accesses -system.cpu.dtb.write_accesses 141821823 # DTB write accesses +system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 156232247 # DTB read accesses +system.cpu.dtb.write_accesses 141723188 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297992404 # DTB hits -system.cpu.dtb.misses 184770 # DTB misses -system.cpu.dtb.accesses 298177174 # DTB accesses +system.cpu.dtb.hits 297770166 # DTB hits +system.cpu.dtb.misses 185269 # DTB misses +system.cpu.dtb.accesses 297955435 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -458,95 +460,93 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 119016 # Table walker walks requested -system.cpu.itb.walker.walksLong 119016 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 118504 # Table walker walks requested +system.cpu.itb.walker.walksLong 118504 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107588 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 119016 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 119016 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 119016 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108698 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28702.878618 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24805.101383 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21517.827982 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107219 98.64% 98.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1293 1.19% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 35 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 66 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 38 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107076 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 118504 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 118504 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 118504 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108186 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28679.602721 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24825.752216 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21031.513378 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 106793 98.71% 98.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.71% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1215 1.12% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 67 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 12 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108698 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 1449242704 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 1449242704 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 1449242704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107588 98.98% 98.98% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1110 1.02% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108698 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108186 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 107076 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108186 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119016 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 119016 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118504 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 118504 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108698 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108698 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 227714 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829969192 # ITB inst hits -system.cpu.itb.inst_misses 119016 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108186 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108186 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 226690 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829409821 # ITB inst hits +system.cpu.itb.inst_misses 118504 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50385 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50494 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 830088208 # ITB inst accesses -system.cpu.itb.hits 829969192 # DTB hits -system.cpu.itb.misses 119016 # DTB misses -system.cpu.itb.accesses 830088208 # DTB accesses -system.cpu.numCycles 103622852545 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 829528325 # ITB inst accesses +system.cpu.itb.hits 829409821 # DTB hits +system.cpu.itb.misses 118504 # DTB misses +system.cpu.itb.accesses 829528325 # DTB accesses +system.cpu.numCycles 103622824883 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed -system.cpu.committedInsts 829457901 # Number of instructions committed -system.cpu.committedOps 974772546 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 896189211 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 901491 # Number of float alu accesses -system.cpu.num_func_calls 49868985 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125722281 # number of instructions that are conditional controls -system.cpu.num_int_insts 896189211 # number of integer instructions -system.cpu.num_fp_insts 901491 # number of float instructions -system.cpu.num_int_register_reads 1296374406 # number of times the integer registers were read -system.cpu.num_int_register_writes 710181687 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1455753 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759888 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214623564 # number of times the CC registers were read -system.cpu.num_cc_register_writes 214015228 # number of times the CC registers were written -system.cpu.num_mem_refs 297970911 # number of memory refs -system.cpu.num_load_insts 156208355 # Number of load instructions -system.cpu.num_store_insts 141762556 # Number of store instructions -system.cpu.num_idle_cycles 100538268245.312057 # Number of idle cycles -system.cpu.num_busy_cycles 3084584299.687941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029767 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970233 # Percentage of idle cycles -system.cpu.Branches 185080610 # Number of branches fetched +system.cpu.committedInsts 828899207 # Number of instructions committed +system.cpu.committedOps 974107036 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 895578515 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 899571 # Number of float alu accesses +system.cpu.num_func_calls 49817464 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 125652530 # number of instructions that are conditional controls +system.cpu.num_int_insts 895578515 # number of integer instructions +system.cpu.num_fp_insts 899571 # number of float instructions +system.cpu.num_int_register_reads 1295563811 # number of times the integer registers were read +system.cpu.num_int_register_writes 709708276 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1453001 # number of times the floating registers were read +system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written +system.cpu.num_cc_register_reads 214507812 # number of times the CC registers were read +system.cpu.num_cc_register_writes 213899539 # number of times the CC registers were written +system.cpu.num_mem_refs 297748170 # number of memory refs +system.cpu.num_load_insts 156084233 # Number of load instructions +system.cpu.num_store_insts 141663937 # Number of store instructions +system.cpu.num_idle_cycles 100539253419.334061 # Number of idle cycles +system.cpu.num_busy_cycles 3083571463.665941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029758 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970242 # Percentage of idle cycles +system.cpu.Branches 184944487 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 675027682 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2118642 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97301 0.01% 69.44% # Class of executed instruction +system.cpu.op_class::IntAlu 674583276 69.21% 69.21% # Class of executed instruction +system.cpu.op_class::IntMult 2119587 0.22% 69.43% # Class of executed instruction +system.cpu.op_class::IntDiv 97316 0.01% 69.44% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction @@ -573,120 +573,120 @@ system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156208355 16.02% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141762556 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 156084233 16.01% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 141663937 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 975326961 # Class of executed instruction -system.cpu.dcache.tags.replacements 9274254 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288519025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9274766 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.107957 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942797 # Average occupied blocks per requestor +system.cpu.op_class::total 974660774 # Class of executed instruction +system.cpu.dcache.tags.replacements 9257757 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288314388 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9258269 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.141284 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33970.100179 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 59971.235784 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 59971.235784 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15325.484229 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15325.484229 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82333.333333 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82333.333333 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22039.892706 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22039.892706 # average overall miss latency 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# average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60132.575478 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15318.532419 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15318.532419 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.088005 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22023.088005 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18937.991116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18937.991116 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,154 +695,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7273356 # number of writebacks -system.cpu.dcache.writebacks::total 7273356 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23715 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 23715 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21271 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21271 # number of WriteReq MSHR hits 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-system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72088738500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970895000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970895000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141075343000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 141075343000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162220170000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 162220170000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5832027500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5832027500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5823842500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5823842500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11655870000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11655870000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031889 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031889 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014275 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014275 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.748279 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.748279 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786652 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786652 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060501 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060501 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76766734500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76766734500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63925265000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 63925265000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20988734000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20988734000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72049377000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72049377000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989622500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989622500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140691999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 140691999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161680733500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161680733500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6200659500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6200659500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217612000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217612000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12418271500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12418271500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031852 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031852 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746972 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746972 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.784842 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.784842 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060939 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060939 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023527 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023527 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027239 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027239 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15983.005731 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15983.005731 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32844.948064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32844.948064 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19075.790463 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19075.790463 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 58971.235784 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 58971.235784 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13742.881990 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13742.881990 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81333.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81333.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20840.293204 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20840.293204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20592.015379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20592.015379 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173046.925998 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173046.925998 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172773.303073 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.303073 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172910.102359 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172910.102359 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023503 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023503 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027211 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027211 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15960.141920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15960.141920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32823.629115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32823.629115 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18971.460647 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18971.460647 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59132.575478 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59132.575478 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13738.505760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13738.505760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20820.307495 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20820.307495 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20560.198457 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20560.198457 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183984.911875 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.911875 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.084846 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.084846 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184220.019285 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184220.019285 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13424392 # number of replacements -system.cpu.icache.tags.tagsinuse 511.782428 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816544283 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13424904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.823100 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 61690343500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.782428 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 13402148 # number of replacements +system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 816007156 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13402660 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.883970 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 843394101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 843394101 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 816544283 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816544283 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816544283 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816544283 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816544283 # number of overall hits -system.cpu.icache.overall_hits::total 816544283 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13424909 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13424909 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13424909 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13424909 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13424909 # number of overall misses -system.cpu.icache.overall_misses::total 13424909 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 183122611500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 183122611500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 183122611500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 183122611500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 183122611500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 183122611500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 829969192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 829969192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 829969192 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 829969192 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 829969192 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 829969192 # number of overall (read+write) accesses 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latency -system.cpu.icache.overall_avg_miss_latency::total 13640.510450 # average overall miss latency +system.cpu.icache.tags.tag_accesses 842812486 # Number of tag accesses +system.cpu.icache.tags.data_accesses 842812486 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 816007156 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 816007156 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 816007156 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 816007156 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 816007156 # number of overall hits +system.cpu.icache.overall_hits::total 816007156 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13402665 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13402665 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13402665 # number of demand (read+write) misses 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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70659.111016 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70659.111016 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120988.049380 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120988.049380 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122155.290102 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122155.290102 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123117.622326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123117.622326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120223.655129 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120223.655129 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160546.925998 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134174.118474 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161273.303073 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161273.303073 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160910.146862 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 142438.101054 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166390 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166390 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005223 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.035964 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.035964 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393538 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393538 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.027822 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127216.395349 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70684.426230 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70684.426230 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120983.207732 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120983.207732 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122181.686358 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122181.686358 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123185.935765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123185.935765 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120266.161559 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120266.161559 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171461.070560 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138965.539459 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.758514 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.758514 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172207.981012 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149330.659972 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45918929 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23219248 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1752 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45838189 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23177247 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2695 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2695 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 973260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20543031 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 972617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20509993 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8233173 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15585132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41662 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1908339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1908339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13424909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6152877 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1329103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1222439 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40358865 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28042657 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 851524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69854144 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 859366676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 981090094 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1963488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2486024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1844906282 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1578062 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 47683915 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010174 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100353 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8211016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13400558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2162503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 41540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 41542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1906001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1906001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13402665 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6142720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1325102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1218438 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40292138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27992932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598317 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853478 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69736865 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715578772 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 979098990 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1953528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2494512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2699125802 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1572119 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 24940276 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019256 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137423 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 47198764 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 485151 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24460029 98.07% 98.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 480247 1.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 47683915 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 30513690500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 24940276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43858094500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1602380 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1606889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20180488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20147122500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12761129471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12740327469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 355662000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 354126000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 540771000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 541664000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 40324 # Transaction distribution system.iobus.trans_dist::ReadResp 40324 # Transaction distribution @@ -1309,37 +1312,37 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334456 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 42148000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25746500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 38603000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565894582 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565448922 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1348,16 +1351,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.446961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.446943 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183666451000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511449 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935511 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433469 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652935 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935476 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1376,19 +1379,19 @@ system.iocache.demand_misses::total 8879 # nu system.iocache.overall_misses::realview.ethernet 40 # number of overall misses system.iocache.overall_misses::realview.ide 8839 # number of overall misses system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1643284102 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1648353102 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1627645138 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1632715138 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13826197480 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13826197480 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1643284102 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1648704102 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1643284102 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1648704102 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13865007784 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13865007784 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1627645138 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1633066138 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1627645138 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1633066138 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) @@ -1415,24 +1418,24 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185912.897613 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185709.002028 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184143.583890 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183947.176431 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129623.841971 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129623.841971 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185685.786913 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185685.786913 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32536 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.697667 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129987.697667 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183924.556594 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183924.556594 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33671 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.637441 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.631293 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1451,19 +1454,19 @@ system.iocache.demand_mshr_misses::total 8879 # nu system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201334102 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1204553102 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185695138 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1188915138 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8492997480 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8492997480 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1201334102 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1204754102 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1201334102 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1204754102 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8531807784 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8531807784 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1185695138 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1189116138 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1185695138 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1189116138 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1477,73 +1480,73 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135912.897613 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135709.002028 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134143.583890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133947.176431 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79623.841971 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79623.841971 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.697667 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.697667 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 384060 # Transaction distribution +system.membus.trans_dist::ReadResp 380595 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::Writeback 959786 # Transaction distribution -system.membus.trans_dist::CleanEvict 158940 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33352 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33355 # Transaction distribution -system.membus.trans_dist::ReadExReq 797298 # Transaction distribution -system.membus.trans_dist::ReadExResp 797298 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 307233 # Transaction distribution +system.membus.trans_dist::WritebackDirty 956243 # Transaction distribution +system.membus.trans_dist::CleanEvict 155849 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33272 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33274 # Transaction distribution +system.membus.trans_dist::ReadExReq 796069 # Transaction distribution +system.membus.trans_dist::ReadExResp 796069 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 303768 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3354625 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3484317 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341373 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341373 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3825690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3338566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3468258 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341194 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341194 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3809452 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124875168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 125044994 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7229568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 132274562 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3206 # Total snoops (count) -system.membus.snoop_fanout::samples 2476492 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124348000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124517826 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7226112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131743938 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3260 # Total snoops (count) +system.membus.snoop_fanout::samples 2465217 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2476492 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2465217 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2476492 # Request fanout histogram -system.membus.reqLayer0.occupancy 107338500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2465217 # Request fanout histogram +system.membus.reqLayer0.occupancy 106924000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5425000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5793500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6302386470 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6289776705 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6068941451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6042674003 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228333558 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227496341 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 2bef0a385..efee64ea0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,71 +4,71 @@ sim_seconds 51.111153 # Nu sim_ticks 51111152682000 # Number of ticks simulated final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 564761 # Simulator instruction rate (inst/s) -host_op_rate 663687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29317960092 # Simulator tick rate (ticks/s) -host_mem_usage 669948 # Number of bytes of host memory used -host_seconds 1743.34 # Real time elapsed on the host +host_inst_rate 1108699 # Simulator instruction rate (inst/s) +host_op_rate 1302904 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57554949131 # Simulator tick rate (ticks/s) +host_mem_usage 721016 # Number of bytes of host memory used +host_seconds 888.04 # Real time elapsed on the host sim_insts 984570519 # Number of instructions simulated sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3317876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 64750152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3272948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 64755976 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 188480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2225152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 45360128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2212992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 45372224 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116883644 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3317876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2225152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103060608 # Number of bytes written to this memory +system.physmem.bytes_read::total 116844476 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3272948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2212992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103078400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103081188 # Number of bytes written to this memory +system.physmem.bytes_written::total 103098980 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 92249 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1011734 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91547 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1011825 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34768 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 708752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 708941 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866727 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610322 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1866115 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610600 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1612895 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1613173 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1266850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1266964 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 887480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 887717 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64915 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2286086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016750 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2016804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2017152 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016750 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64915 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1267252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1267366 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 887480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 887717 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4303238 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -410,8 +410,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8921279 # number of writebacks -system.cpu0.dcache.writebacks::total 8921279 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8921277 # number of writebacks +system.cpu0.dcache.writebacks::total 8921277 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 14295641 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -475,6 +475,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 14295641 # number of writebacks +system.cpu0.icache.writebacks::total 14295641 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -786,30 +788,30 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1722562 # number of replacements -system.l2c.tags.tagsinuse 65341.862549 # Cycle average of tags in use -system.l2c.tags.total_refs 47048799 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1785858 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.345207 # Average number of references to valid blocks. +system.l2c.tags.replacements 1723178 # number of replacements +system.l2c.tags.tagsinuse 65341.862566 # Cycle average of tags in use +system.l2c.tags.total_refs 47049406 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1786474 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.336463 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37097.979539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460552 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.494258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3630.477879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9618.607320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 37238.861730 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.459058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.477138 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3478.418369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9618.970377 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652979 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2660.497968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11581.451661 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.566070 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 2640.978192 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11611.804335 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.568220 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146768 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053076 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146774 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040596 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.176719 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040298 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.177182 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 63020 # Occupied blocks per task id @@ -821,48 +823,50 @@ system.l2c.tags.age_task_id_blocks_1024::3 4910 # system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426841717 # Number of tag accesses -system.l2c.tags.data_accesses 426841717 # Number of data accesses +system.l2c.tags.tag_accesses 426842331 # Number of tag accesses +system.l2c.tags.data_accesses 426842331 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 142757 # number of ReadReq hits system.l2c.ReadReq_hits::total 844303 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8921279 # number of Writeback hits -system.l2c.Writeback_hits::total 8921279 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 14294063 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 864866 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 827692 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1692558 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7107362 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7104867 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3754928 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3749182 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7504110 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 345122 # number of InvalidateReq hits +system.l2c.ReadExReq_hits::cpu0.data 864865 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 827683 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1692548 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7108064 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7105057 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3754840 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3749002 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7503842 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 345118 # number of InvalidateReq hits system.l2c.InvalidateReq_hits::cpu1.data 349199 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 694321 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 694317 # number of InvalidateReq hits system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7107362 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4619794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7108064 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4619705 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 142757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7104867 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4576874 # number of demand (read+write) hits -system.l2c.demand_hits::total 24253200 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7105057 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4576685 # number of demand (read+write) hits +system.l2c.demand_hits::total 24253814 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7107362 # number of overall hits -system.l2c.overall_hits::cpu0.data 4619794 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7108064 # number of overall hits +system.l2c.overall_hits::cpu0.data 4619705 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 142757 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7104867 # number of overall hits -system.l2c.overall_hits::cpu1.data 4576874 # number of overall hits -system.l2c.overall_hits::total 24253200 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7105057 # number of overall hits +system.l2c.overall_hits::cpu1.data 4576685 # number of overall hits +system.l2c.overall_hits::total 24253814 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses @@ -873,43 +877,45 @@ system.l2c.UpgradeReq_misses::cpu1.data 19925 # nu system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 415071 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 411488 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 826559 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 49148 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 34781 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 177103 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 166985 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 344088 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 420021 # number of InvalidateReq misses +system.l2c.ReadExReq_misses::cpu0.data 415072 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 411497 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 826569 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 48446 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 34591 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 177191 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 167165 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 344356 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 420025 # number of InvalidateReq misses system.l2c.InvalidateReq_misses::cpu1.data 131007 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 551028 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 551032 # number of InvalidateReq misses system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49148 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 592174 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 48446 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 592263 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 2945 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34781 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 578473 # number of demand (read+write) misses -system.l2c.demand_misses::total 1266892 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34591 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 578662 # number of demand (read+write) misses +system.l2c.demand_misses::total 1266278 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses -system.l2c.overall_misses::cpu0.inst 49148 # number of overall misses -system.l2c.overall_misses::cpu0.data 592174 # number of overall misses +system.l2c.overall_misses::cpu0.inst 48446 # number of overall misses +system.l2c.overall_misses::cpu0.data 592263 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 2945 # number of overall misses -system.l2c.overall_misses::cpu1.inst 34781 # number of overall misses -system.l2c.overall_misses::cpu1.data 578473 # number of overall misses -system.l2c.overall_misses::total 1266892 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34591 # number of overall misses +system.l2c.overall_misses::cpu1.data 578662 # number of overall misses +system.l2c.overall_misses::total 1266278 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 856619 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses) @@ -955,36 +961,36 @@ system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.324290 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.332065 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328115 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006868 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004872 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045041 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042640 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548944 # miss rate for InvalidateReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.324291 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332072 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328119 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006770 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004845 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045063 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042686 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548950 # miss rate for InvalidateReq accesses system.l2c.InvalidateReq_miss_rate::cpu1.data 0.272814 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.442469 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442472 # miss rate for InvalidateReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006868 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.113618 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113635 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.020212 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004872 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049643 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004845 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112245 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049619 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006868 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.113618 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113635 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.020212 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004872 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049643 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004845 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112245 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049619 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -993,51 +999,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1503691 # number of writebacks -system.l2c.writebacks::total 1503691 # number of writebacks +system.l2c.writebacks::writebacks 1503969 # number of writebacks +system.l2c.writebacks::total 1503969 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525866 # Transaction distribution +system.membus.trans_dist::ReadResp 525242 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::Writeback 1610322 # Transaction distribution -system.membus.trans_dist::CleanEvict 225569 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1610600 # Transaction distribution +system.membus.trans_dist::CleanEvict 224679 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40488 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377023 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377023 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 449187 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40489 # Transaction distribution +system.membus.trans_dist::ReadExReq 1377035 # Transaction distribution +system.membus.trans_dist::ReadExResp 1377035 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448563 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5529617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5658809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5527785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5656977 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6003183 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6001351 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212740128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 212909178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212718752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212887802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220300218 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220278842 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3921668 # Request fanout histogram +system.membus.snoop_fanout::samples 3920446 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3921668 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3920446 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3921668 # Request fanout histogram +system.membus.snoop_fanout::total 3920446 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1093,15 +1099,16 @@ system.realview.realview_io.osc_system_bus.clock 41667 system.toL2Bus.snoop_filter.tot_requests 52477792 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 26568978 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution @@ -1116,22 +1123,22 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 80533877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2159735666 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1954363 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 55175249 # Request fanout histogram +system.toL2Bus.pkt_size::total 3074555570 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1954979 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 55175865 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.011169 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.105093 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54558983 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 616266 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54559594 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 616271 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 55175249 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 55175865 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index e8e31dd45..929ad0607 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,192 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.397579 # Number of seconds simulated -sim_ticks 51397578885000 # Number of ticks simulated -final_tick 51397578885000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.278388 # Number of seconds simulated +sim_ticks 51278388278000 # Number of ticks simulated +final_tick 51278388278000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213094 # Simulator instruction rate (inst/s) -host_op_rate 250423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11187167929 # Simulator tick rate (ticks/s) -host_mem_usage 682236 # Number of bytes of host memory used -host_seconds 4594.33 # Real time elapsed on the host -sim_insts 979026656 # Number of instructions simulated -sim_ops 1150528336 # Number of ops (including micro ops) simulated +host_inst_rate 258575 # Simulator instruction rate (inst/s) +host_op_rate 303855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15635824114 # Simulator tick rate (ticks/s) +host_mem_usage 733268 # Number of bytes of host memory used +host_seconds 3279.55 # Real time elapsed on the host +sim_insts 848009832 # Number of instructions simulated +sim_ops 996505618 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 187840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 177856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2851188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 60331016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 46336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 415360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9688384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 76288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 60224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1747072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 13459648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 113856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 106880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1985280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 25411584 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 412224 # Number of bytes read from this memory -system.physmem.bytes_read::total 117115836 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2851188 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 415360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1747072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1985280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6998900 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101778880 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 80512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 85376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2480372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43948744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 23424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 20864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 458368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5839488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 24512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 21952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1437632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 8179392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 58944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1702784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 14408960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 423680 # Number of bytes read from this memory +system.physmem.bytes_read::total 79259836 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2480372 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 458368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1437632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1702784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6079156 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67469760 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 101799460 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 84957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 942685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 724 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 151381 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1192 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 941 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 27298 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 210307 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 1670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 31020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 397056 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6441 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1870355 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1590295 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67490340 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1258 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1334 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 79163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 686712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 366 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 91242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 22463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 127803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 26606 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 225140 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6620 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1278855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1054215 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1592868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 55473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1173810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 872 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 188499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 33991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 261873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 2215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 2079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 38626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 494412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2278626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 55473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 33991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 38626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 136172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1980227 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 400 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1980628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1980227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 55473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1174211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 188499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 33991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 261873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 2215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 2079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 38626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 494412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4259253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 833134 # Number of read requests accepted -system.physmem.writeReqs 737289 # Number of write requests accepted -system.physmem.readBursts 833134 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 737289 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 53302080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue -system.physmem.bytesWritten 47184896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 53320576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 47186496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 72650 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 50780 # Per bank write bursts -system.physmem.perBankRdBursts::1 53589 # Per bank write bursts -system.physmem.perBankRdBursts::2 52846 # Per bank write bursts -system.physmem.perBankRdBursts::3 50887 # Per bank write bursts -system.physmem.perBankRdBursts::4 54092 # Per bank write bursts -system.physmem.perBankRdBursts::5 57010 # Per bank write bursts -system.physmem.perBankRdBursts::6 51070 # Per bank write bursts -system.physmem.perBankRdBursts::7 50979 # Per bank write bursts -system.physmem.perBankRdBursts::8 47072 # Per bank write bursts -system.physmem.perBankRdBursts::9 53421 # Per bank write bursts -system.physmem.perBankRdBursts::10 50826 # Per bank write bursts -system.physmem.perBankRdBursts::11 55035 # Per bank write bursts -system.physmem.perBankRdBursts::12 52027 # Per bank write bursts -system.physmem.perBankRdBursts::13 53888 # Per bank write bursts -system.physmem.perBankRdBursts::14 49567 # Per bank write bursts -system.physmem.perBankRdBursts::15 49756 # Per bank write bursts -system.physmem.perBankWrBursts::0 44616 # Per bank write bursts -system.physmem.perBankWrBursts::1 46679 # Per bank write bursts -system.physmem.perBankWrBursts::2 46441 # Per bank write bursts -system.physmem.perBankWrBursts::3 46533 # Per bank write bursts -system.physmem.perBankWrBursts::4 48478 # Per bank write bursts -system.physmem.perBankWrBursts::5 49819 # Per bank write bursts -system.physmem.perBankWrBursts::6 45666 # Per bank write bursts -system.physmem.perBankWrBursts::7 46728 # Per bank write bursts -system.physmem.perBankWrBursts::8 42759 # Per bank write bursts -system.physmem.perBankWrBursts::9 46487 # Per bank write bursts -system.physmem.perBankWrBursts::10 43753 # Per bank write bursts -system.physmem.perBankWrBursts::11 47850 # Per bank write bursts -system.physmem.perBankWrBursts::12 45610 # Per bank write bursts -system.physmem.perBankWrBursts::13 46767 # Per bank write bursts -system.physmem.perBankWrBursts::14 44243 # Per bank write bursts -system.physmem.perBankWrBursts::15 44835 # Per bank write bursts +system.physmem.num_writes::total 1056788 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 48371 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 857062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 113878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 28036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 159510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 33207 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 280995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1545677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 48371 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8939 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 28036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 33207 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 118552 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1315754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1316156 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1315754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 48371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 857463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 113878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 28036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 159510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 33207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 280995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2861833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 508133 # Number of read requests accepted +system.physmem.writeReqs 442708 # Number of write requests accepted +system.physmem.readBursts 508133 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 442708 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 32496192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24320 # Total number of bytes read from write queue +system.physmem.bytesWritten 28331264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 32520512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28333312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 380 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 172464 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28425 # Per bank write bursts +system.physmem.perBankRdBursts::1 32222 # Per bank write bursts +system.physmem.perBankRdBursts::2 31678 # Per bank write bursts +system.physmem.perBankRdBursts::3 29785 # Per bank write bursts +system.physmem.perBankRdBursts::4 32093 # Per bank write bursts +system.physmem.perBankRdBursts::5 37258 # Per bank write bursts +system.physmem.perBankRdBursts::6 31249 # Per bank write bursts +system.physmem.perBankRdBursts::7 31793 # Per bank write bursts +system.physmem.perBankRdBursts::8 30380 # Per bank write bursts +system.physmem.perBankRdBursts::9 34315 # Per bank write bursts +system.physmem.perBankRdBursts::10 33552 # Per bank write bursts +system.physmem.perBankRdBursts::11 33985 # Per bank write bursts +system.physmem.perBankRdBursts::12 32112 # Per bank write bursts +system.physmem.perBankRdBursts::13 32580 # Per bank write bursts +system.physmem.perBankRdBursts::14 28200 # Per bank write bursts +system.physmem.perBankRdBursts::15 28126 # Per bank write bursts +system.physmem.perBankWrBursts::0 25043 # Per bank write bursts +system.physmem.perBankWrBursts::1 27380 # Per bank write bursts +system.physmem.perBankWrBursts::2 27369 # Per bank write bursts +system.physmem.perBankWrBursts::3 27020 # Per bank write bursts +system.physmem.perBankWrBursts::4 28395 # Per bank write bursts +system.physmem.perBankWrBursts::5 31777 # Per bank write bursts +system.physmem.perBankWrBursts::6 27205 # Per bank write bursts +system.physmem.perBankWrBursts::7 28447 # Per bank write bursts +system.physmem.perBankWrBursts::8 27006 # Per bank write bursts +system.physmem.perBankWrBursts::9 30006 # Per bank write bursts +system.physmem.perBankWrBursts::10 27888 # Per bank write bursts +system.physmem.perBankWrBursts::11 28964 # Per bank write bursts +system.physmem.perBankWrBursts::12 27392 # Per bank write bursts +system.physmem.perBankWrBursts::13 28158 # Per bank write bursts +system.physmem.perBankWrBursts::14 25051 # Per bank write bursts +system.physmem.perBankWrBursts::15 25575 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 51396578546000 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 51277388057000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 833134 # Read request sizes (log2) +system.physmem.readPktSize::6 508133 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 737289 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 571213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 169334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 442708 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 359636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 75 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -198,186 +198,193 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 10640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 28561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 34227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 40879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 43831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 46135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 46247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 46174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 47038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 46944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 49392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 44847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 45364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 43267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 393907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 255.102976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.689482 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.846029 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 173695 44.10% 44.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 94994 24.12% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 37135 9.43% 77.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19371 4.92% 82.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15343 3.90% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9742 2.47% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8567 2.17% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6531 1.66% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 28529 7.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 393907 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 42633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 19.534281 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9.731161 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 39808 93.37% 93.37% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 2621 6.15% 99.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 170 0.40% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 21 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 4 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::352-383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 42633 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 42633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.293270 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.880471 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 5.837851 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 31 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.02% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 18 0.04% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 54 0.13% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40522 95.05% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 728 1.71% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 202 0.47% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 312 0.73% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 57 0.13% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 185 0.43% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 71 0.17% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.09% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 54 0.13% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 19 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 210 0.49% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 44 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 42633 # Writes before turning the bus around for reads -system.physmem.totQLat 19475290366 # Total ticks spent queuing -system.physmem.totMemAccLat 35091134116 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4164225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23384.05 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7362 # What write queue length does an incoming req see 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an incoming req see +system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 256507 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.135361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.751053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.773032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 118370 46.15% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 63779 24.86% 71.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23560 9.18% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11879 4.63% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8772 3.42% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5502 2.14% 90.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4497 1.75% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3462 1.35% 93.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16686 6.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 256507 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 24650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.597972 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 13.431676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-31 22290 90.43% 90.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-63 2167 8.79% 99.22% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-95 156 0.63% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-127 17 0.07% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-159 6 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::160-191 3 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-223 1 0.00% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::224-255 2 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::320-351 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::416-447 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::448-479 1 0.00% 99.99% # Reads before turning the bus around for writes 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Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 29 0.12% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 72 0.29% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 15 0.06% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 17 0.07% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 194 0.79% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 14 0.06% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 52 0.21% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 24650 # Writes before turning the bus around for reads +system.physmem.totQLat 10544434255 # Total ticks spent queuing +system.physmem.totMemAccLat 20064803005 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2538765000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20766.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42134.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39516.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.53 # Average write queue length when enqueuing -system.physmem.readRowHits 652462 # Number of row buffer hits during reads -system.physmem.writeRowHits 523738 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.04 # Row buffer hit rate for writes -system.physmem.avgGap 32727856.47 # Average gap between requests -system.physmem.pageHitRate 74.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1529501400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 832833375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3285765600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2429740800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1212289072380 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29739570673500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34275922206015 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.648127 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48905170971226 # Time in different power states -system.physmem_0.memoryStateTime::REF 1695288660000 # Time in different power states +system.physmem.avgWrQLen 12.69 # Average write queue length when enqueuing +system.physmem.readRowHits 386701 # Number of row buffer hits during reads +system.physmem.writeRowHits 307219 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.40 # Row buffer hit rate for writes +system.physmem.avgGap 53928457.08 # Average gap between requests +system.physmem.pageHitRate 73.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 977757480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 531832125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1985068800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1442681280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3310425549600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1177046851320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30704731659000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35197141399605 # Total energy per rank (pJ) +system.physmem_0.averagePower 665.410484 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48872276305390 # Time in different power states +system.physmem_0.memoryStateTime::REF 1692446600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 169075280274 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119675759110 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1448412840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 788411250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3210347400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2347729920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1209778712865 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29729309949000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34262868182235 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.663987 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48908958102968 # Time in different power states -system.physmem_1.memoryStateTime::REF 1695288660000 # Time in different power states +system.physmem_1.actEnergy 961435440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 522856125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1975334400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1425859200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3310425549600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177208679735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29690763244500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34183282959000 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.568308 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48872046794911 # Time in different power states +system.physmem_1.memoryStateTime::REF 1692446600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 165299992532 # Time in different power states +system.physmem_1.memoryStateTime::ACT 119910447839 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -437,47 +444,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 119866 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 119866 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 119866 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 119866 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 119866 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.652647 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -247578241138 -65.26% -65.26% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 626923323250 165.26% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 379345082112 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88729 84.84% 84.84% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15861 15.16% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 104590 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 119866 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 90321 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90321 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90321 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90321 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 389002628992 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.524259 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -203938078758 -52.43% -52.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 592940707750 152.43% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 389002628992 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 65935 84.97% 84.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11661 15.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 77596 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90321 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 119866 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104590 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90321 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77596 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104590 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 224456 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77596 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 167917 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 75642766 # DTB read hits -system.cpu0.dtb.read_misses 89640 # DTB read misses -system.cpu0.dtb.write_hits 69609144 # DTB write hits -system.cpu0.dtb.write_misses 30226 # DTB write misses -system.cpu0.dtb.flush_tlb 1263 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64849168 # DTB read hits +system.cpu0.dtb.read_misses 68465 # DTB read misses +system.cpu0.dtb.write_hits 59113138 # DTB write hits +system.cpu0.dtb.write_misses 21856 # DTB write misses +system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 47006 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16233 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 380 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40748 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3911 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2820 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8593 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 75732406 # DTB read accesses -system.cpu0.dtb.write_accesses 69639370 # DTB write accesses +system.cpu0.dtb.perms_faults 7506 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64917633 # DTB read accesses +system.cpu0.dtb.write_accesses 59134994 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 145251910 # DTB hits -system.cpu0.dtb.misses 119866 # DTB misses -system.cpu0.dtb.accesses 145371776 # DTB accesses +system.cpu0.dtb.hits 123962306 # DTB hits +system.cpu0.dtb.misses 90321 # DTB misses +system.cpu0.dtb.accesses 124052627 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,697 +514,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 57950 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57950 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 57950 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57950 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57950 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.652788 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -247631753638 -65.28% -65.28% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 626976835750 165.28% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 379345082112 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 50452 94.94% 94.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2688 5.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 53140 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53302 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53302 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53302 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53302 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53302 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 389002628992 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.524352 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -203974223258 -52.44% -52.44% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 592976852250 152.44% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 389002628992 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46280 94.90% 94.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2485 5.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 48765 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57950 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57950 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53302 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53302 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53140 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53140 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111090 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 405381622 # ITB inst hits -system.cpu0.itb.inst_misses 57950 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48765 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48765 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 102067 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 346354960 # ITB inst hits +system.cpu0.itb.inst_misses 53302 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1263 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 33228 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16233 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 380 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28697 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 405439572 # ITB inst accesses -system.cpu0.itb.hits 405381622 # DTB hits -system.cpu0.itb.misses 57950 # DTB misses -system.cpu0.itb.accesses 405439572 # DTB accesses -system.cpu0.numCycles 487302102 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 346408262 # ITB inst accesses +system.cpu0.itb.hits 346354960 # DTB hits +system.cpu0.itb.misses 53302 # DTB misses +system.cpu0.itb.accesses 346408262 # DTB accesses +system.cpu0.numCycles 417857825 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 17144 # number of quiesce instructions executed -system.cpu0.committedInsts 405220560 # Number of instructions committed -system.cpu0.committedOps 476699664 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 436776878 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 371179 # Number of float alu accesses -system.cpu0.num_func_calls 23615839 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 62442452 # number of instructions that are conditional controls -system.cpu0.num_int_insts 436776878 # number of integer instructions -system.cpu0.num_fp_insts 371179 # number of float instructions -system.cpu0.num_int_register_reads 647764481 # number of times the integer registers were read -system.cpu0.num_int_register_writes 347118708 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 591811 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 329388 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 109017876 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 108807189 # number of times the CC registers were written -system.cpu0.num_mem_refs 145355316 # number of memory refs -system.cpu0.num_load_insts 75721514 # Number of load instructions -system.cpu0.num_store_insts 69633802 # Number of store instructions -system.cpu0.num_idle_cycles 473916691.596574 # Number of idle cycles -system.cpu0.num_busy_cycles 13385410.403426 # Number of busy cycles -system.cpu0.not_idle_fraction 0.027468 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.972532 # Percentage of idle cycles -system.cpu0.Branches 90584626 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16514 # number of quiesce instructions executed +system.cpu0.committedInsts 346212347 # Number of instructions committed +system.cpu0.committedOps 407289562 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 374196807 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 371114 # Number of float alu accesses +system.cpu0.num_func_calls 20959157 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 52529410 # number of instructions that are conditional controls +system.cpu0.num_int_insts 374196807 # number of integer instructions +system.cpu0.num_fp_insts 371114 # number of float instructions +system.cpu0.num_int_register_reads 546236459 # number of times the integer registers were read +system.cpu0.num_int_register_writes 297045333 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 596552 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 319604 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 90150585 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89913729 # number of times the CC registers were written +system.cpu0.num_mem_refs 124035099 # number of memory refs +system.cpu0.num_load_insts 64906131 # Number of load instructions +system.cpu0.num_store_insts 59128968 # Number of store instructions +system.cpu0.num_idle_cycles 408498118.041102 # Number of idle cycles +system.cpu0.num_busy_cycles 9359706.958898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.022399 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.977601 # Percentage of idle cycles +system.cpu0.Branches 77291806 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 330567149 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 941893 0.20% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 42225 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 50408 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::MemRead 75721514 15.88% 85.40% # Class of executed instruction -system.cpu0.op_class::MemWrite 69633802 14.60% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 282487625 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 909497 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 41524 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 50320 0.01% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu0.op_class::MemRead 64906131 15.93% 85.49% # Class of executed instruction +system.cpu0.op_class::MemWrite 59128968 14.51% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 476956991 # Class of executed instruction -system.cpu0.dcache.tags.replacements 11638567 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 335736078 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11639079 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.845588 # Average number of references to valid blocks. +system.cpu0.op_class::total 407524065 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9647883 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 292725890 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9648395 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.339335 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.702275 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.106923 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.404077 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.786443 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964262 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013881 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010555 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.011302 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.728369 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.127427 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.702216 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.441704 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972126 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010015 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009184 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008675 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1427343443 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1427343443 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 70546993 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 21833087 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 29621653 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 49726137 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171727870 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 65848513 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 20323574 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 26400594 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 41881288 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 154453969 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178125 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 52842 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 85285 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 124641 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 440893 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 129363 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44707 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 62671 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98791 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 335532 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1762005 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 548820 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 697386 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 1176730 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4184941 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1865727 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 590771 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 751156 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1333509 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4541163 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 136395506 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 42156661 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 56022247 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 91607425 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 326181839 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 136573631 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 42209503 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 56107532 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 91732066 # number of overall hits -system.cpu0.dcache.overall_hits::total 326622732 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2475648 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 760979 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 1254924 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3959185 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 8450736 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1073288 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 320657 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 740390 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 4437299 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 6571634 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 641779 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 196644 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 265541 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 463204 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1567168 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 696374 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 111936 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 158316 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 281973 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1248599 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104417 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 42188 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 54084 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 202888 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 403577 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3548936 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1081636 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1995314 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 8396484 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 15022370 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4190715 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1278280 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 2260855 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 8859688 # number of overall misses -system.cpu0.dcache.overall_misses::total 16589538 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 13138449000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 22320104000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 72359917000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 107818470000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 15766909000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 37704242500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 250636765802 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 304107917302 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 4487202500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 6834071500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 13735050622 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25056324622 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 652172000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 880917500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2926113500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4459203000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 97500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 97500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 28905358000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 60024346500 # number of demand (read+write) miss cycles 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accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2008061 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 825737 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 156643 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 220987 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 380764 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1584131 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866422 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 591008 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 751470 # number of LoadLockedReq accesses(hits+misses) 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# number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 100003909 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 341204209 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 140764346 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 43487783 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 58368387 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 100591754 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 343212270 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033902 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033680 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.040643 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.073748 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.046902 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016038 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015533 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027279 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.095800 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.040811 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782749 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.788197 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.756902 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.787970 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780438 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843336 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714593 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.716404 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.740545 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788192 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055945 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.071383 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.071971 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.147061 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087954 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.tags.tag_accesses 1240366941 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1240366941 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 60678163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 18920478 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 25986249 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 44943337 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 150528227 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55903260 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17361553 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23186798 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 37880903 # number of WriteReq hits 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49173047 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 82824240 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 284860741 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 116740529 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 36328998 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 49250009 # number of overall hits +system.cpu0.dcache.overall_hits::cpu3.data 82937162 # number of overall hits +system.cpu0.dcache.overall_hits::total 285256698 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2044900 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 654690 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 963514 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu3.data 3438861 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7101965 # number of ReadReq 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SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 814123 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 157067 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 209808 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 374141 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1555139 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1550233 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 467855 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 622012 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1105875 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3745975 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1549496 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 467643 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 621749 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1067527 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3706415 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 119471945 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 37187911 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 50741020 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 89705457 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 297106333 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 120094513 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 37379965 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 51027907 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 90169717 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 298672102 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032602 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033445 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035752 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071077 # miss rate for ReadReq accesses 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SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.844563 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.704298 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.715335 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.741215 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788098 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059326 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.080760 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.080900 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.159321 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095106 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025360 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025016 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.034392 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.083962 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044028 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029771 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029394 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.038734 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.088076 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17265.192601 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17786.020508 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 18276.467758 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12758.470978 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49170.637161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 50924.840287 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 56484.083178 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46275.845140 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40087.215016 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 43167.282524 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 48710.517042 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20067.551409 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15458.708638 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16287.950226 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14422.309353 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11049.200029 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 48750 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24375 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26723.738855 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30082.656915 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 38468.087690 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 27420.865503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22612.696749 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26549.401222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 36456.891349 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24830.491802 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 26241707 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 45127 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1118476 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 412 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.462021 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 109.531553 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024194 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024360 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030901 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076709 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041216 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027928 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028116 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034842 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080210 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.044917 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16389.983809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17142.751948 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17640.362754 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12378.320014 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36542.473825 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37655.726857 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33422.458350 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28577.586795 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 33609.336298 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35814.945730 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39930.978970 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16454.579592 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14179.493966 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14924.305956 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13292.645965 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10185.683049 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 84500 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 42250 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21978.035170 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25050.574532 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25535.418449 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19182.644868 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18943.946385 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22092.732260 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24294.976745 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17509.934292 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14425372 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 42395 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 882588 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 392 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.344401 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 108.150510 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8924778 # number of writebacks -system.cpu0.dcache.writebacks::total 8924778 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3070 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 177170 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 2166772 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2347012 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4945 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 329293 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 3711119 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 4045357 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 29 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2101 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2130 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8861 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 11403 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 125299 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145563 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8015 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 506463 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 5877891 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 6392369 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8015 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 506463 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 5877891 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 6392369 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 757909 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 1077754 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1792413 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3628076 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 315712 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 411097 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 726180 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1452989 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 196254 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 262805 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 454839 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 913898 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 111936 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 158287 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 279872 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 550095 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 33327 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 42681 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 77589 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 153597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1073621 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1488851 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2518593 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5081065 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1269875 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1751656 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2973432 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5994963 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 7202 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6366 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20143 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6701 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5973 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6301 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18975 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13903 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12339 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12876 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39118 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 12177566500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 17778974500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 32248588000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 62205129000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 15233797500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 19851845000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 42775170792 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 77860813292 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3503817000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 5256863500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 8318157000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17078837500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 4375266500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 6674550500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 13332028122 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24381845122 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 465254000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 623794000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 1175051500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2264099500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 95500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 95500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 27411364000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 37630819500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 75023758792 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 140065942292 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 30915181000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 42887683000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 83341915792 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 157144779792 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1347374000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1179541000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1196510000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3723425000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281429000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1132115000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1164905963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3578449963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2628803000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2311656000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2361415963 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7301874963 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033545 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.034905 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.033387 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015293 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015147 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.015678 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009023 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786633 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.749104 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.773740 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.455115 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714593 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716273 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.735027 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.347253 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056390 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056797 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.056239 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.033474 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.writebacks::writebacks 7475106 # number of writebacks +system.cpu0.dcache.writebacks::total 7475106 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3650 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 124312 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1904102 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2032064 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4908 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 268057 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2861568 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3134533 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 28 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2036 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 2064 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8313 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10472 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 108224 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 127009 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8558 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 392369 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 4765670 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5166597 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8558 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 392369 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 4765670 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5166597 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 651040 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 839202 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1534759 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3025001 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 246282 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 336402 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580788 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1163472 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 144706 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 207290 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 344141 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 696137 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 110622 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 150055 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 275283 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 535960 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29471 # number of LoadLockedReq MSHR misses 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StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 18561983000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25280515000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47621566160 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 91464064160 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 21588599000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29487823500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54341385160 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 105417807660 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1349798500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1371763500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1366987000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4088549000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281894000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1318427500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1339823955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3940145455 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2631692500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2690191000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2706810955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8028694455 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033258 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031139 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031722 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019190 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013983 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014140 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014055 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.753465 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.722549 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.741268 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.444598 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.704298 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.715202 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.735773 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.344638 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062992 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.064065 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061458 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036649 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024830 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025662 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.025185 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014892 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030010 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029559 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017467 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16067.320087 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16496.319661 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17991.717311 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17145.486754 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48252.196622 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48289.929141 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 58904.363645 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 53586.650203 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17853.480693 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20002.905196 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 18288.134922 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18687.903355 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39087.215016 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 42167.395301 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 47636.162682 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 44322.971709 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13960.272452 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14615.262060 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15144.563018 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14740.519021 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 47750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 47750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25531.695077 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25275.074202 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 29787.964467 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27566.256738 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24345.058372 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 24484.078495 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28028.862201 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26212.802280 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187083.310192 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 185287.621740 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 181978.707224 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184849.575535 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191229.517982 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 189538.757743 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 184876.362958 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188587.613333 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 189081.708984 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187345.489910 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 183396.704178 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186662.788563 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024129 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023169 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023583 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014098 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027877 # mshr miss rate for overall accesses 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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36319.732260 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36022.325127 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20915.622020 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20296.726808 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19526.354023 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20044.536492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 32609.336298 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34813.618340 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38782.876738 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36397.369500 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12984.561094 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13246.693769 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14257.073494 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13690.625341 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 83500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20685.977832 # average overall mshr miss latency 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latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191160.257307 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195204.058248 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203313.877875 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202523.425499 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 195167.364166 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200210.643039 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200326.748877 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199687.574228 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 193122.927725 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197629.401969 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16734603 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971494 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 650477960 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16735115 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 38.869046 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 11779377500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 475.687206 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.486973 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.054415 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.742900 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.929077 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010717 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.045028 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.015123 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 15696881 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971340 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 558297724 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15697393 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 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of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 684306607 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 684306607 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 399406332 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 123839702 # 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+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13505.176060 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8854.142441 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13534.524474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13730.909009 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13505.176060 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8854.142441 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 61485 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3838 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3700 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.238927 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.617568 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358390 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 358390 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu3.inst 358390 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 358390 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu3.inst 358390 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 358390 # number of overall MSHR hits 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MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 22495257500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 53372390500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 60789325843 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 136656973843 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052858 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.082047 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016038 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014395 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052858 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.082047 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016038 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014395 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052858 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.082047 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016038 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12763.688775 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12763.688775 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12763.688775 # average overall mshr miss latency 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# number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1686311 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3834374 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4581067 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10101752 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1686311 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3834374 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4581067 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10101752 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21137106500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48815066500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58829212841 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 128781385841 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21137106500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48815066500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58829212841 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 128781385841 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21137106500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48815066500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58829212841 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 128781385841 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015676 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.056533 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087184 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017588 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015676 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.056533 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087184 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017588 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015676 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.056533 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087184 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017588 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12534.524474 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12730.909009 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12841.814547 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.420852 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12534.524474 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12730.909009 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12841.814547 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.420852 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12534.524474 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12730.909009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12841.814547 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.420852 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1228,69 +1237,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 42213 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 42213 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6241 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 31075 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 42204 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.853000 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 141.748477 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 42202 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 31728 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31728 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4579 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23199 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31723 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.882640 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 157.206647 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 31722 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 42204 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 37325 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 26882.732753 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 23412.636165 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 18338.779624 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 37004 99.14% 99.14% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 275 0.74% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 19 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 31723 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27783 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25230.482669 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21865.634493 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16058.224156 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 27633 99.46% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 123 0.44% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 5 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 12 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 37325 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2908388356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.649897 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.477002 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1018236500 35.01% 35.01% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1890151856 64.99% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2908388356 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 31075 83.28% 83.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 6241 16.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 37316 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 42213 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 27783 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2741941428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.632141 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.482223 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1008648500 36.79% 36.79% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1733292928 63.21% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2741941428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23199 83.52% 83.52% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4579 16.48% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27778 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31728 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 42213 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 37316 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31728 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27778 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 37316 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 79529 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27778 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 59506 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 23441762 # DTB read hits -system.cpu1.dtb.read_misses 32033 # DTB read misses -system.cpu1.dtb.write_hits 21401339 # DTB write hits -system.cpu1.dtb.write_misses 10180 # DTB write misses -system.cpu1.dtb.flush_tlb 1255 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20241909 # DTB read hits +system.cpu1.dtb.read_misses 24578 # DTB read misses +system.cpu1.dtb.write_hits 18246308 # DTB write hits +system.cpu1.dtb.write_misses 7150 # DTB write misses +system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 20769 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17924 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1303 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 956 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2968 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 23473795 # DTB read accesses -system.cpu1.dtb.write_accesses 21411519 # DTB write accesses +system.cpu1.dtb.perms_faults 2537 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20266487 # DTB read accesses +system.cpu1.dtb.write_accesses 18253458 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 44843101 # DTB hits -system.cpu1.dtb.misses 42213 # DTB misses -system.cpu1.dtb.accesses 44885314 # DTB accesses +system.cpu1.dtb.hits 38488217 # DTB hits +system.cpu1.dtb.misses 31728 # DTB misses +system.cpu1.dtb.accesses 38519945 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1320,131 +1327,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 21791 # Table walker walks requested -system.cpu1.itb.walker.walksLong 21791 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1072 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 19067 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 21791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 21791 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 21791 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 20139 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29400.094344 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25404.974001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23277.059653 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 19797 98.30% 98.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 293 1.45% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 9 0.04% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.10% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.07% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 20139 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20290 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20290 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 971 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17908 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20290 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20290 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20290 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18879 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28298.930028 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25145.287562 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17574.390852 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 18719 99.15% 99.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 141 0.75% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 3 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 8 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 3 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18879 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 19067 94.68% 94.68% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1072 5.32% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 20139 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17908 94.86% 94.86% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 971 5.14% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18879 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 21791 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 21791 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20290 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20290 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 20139 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 20139 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 41930 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 125648425 # ITB inst hits -system.cpu1.itb.inst_misses 21791 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18879 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18879 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 39169 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 107574480 # ITB inst hits +system.cpu1.itb.inst_misses 20290 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1255 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 15047 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13368 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 125670216 # ITB inst accesses -system.cpu1.itb.hits 125648425 # DTB hits -system.cpu1.itb.misses 21791 # DTB misses -system.cpu1.itb.accesses 125670216 # DTB accesses -system.cpu1.numCycles 1254117353 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 107594770 # ITB inst accesses +system.cpu1.itb.hits 107574480 # DTB hits +system.cpu1.itb.misses 20290 # DTB misses +system.cpu1.itb.accesses 107594770 # DTB accesses +system.cpu1.numCycles 1186092617 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 125557631 # Number of instructions committed -system.cpu1.committedOps 147479999 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 135255426 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 113335 # Number of float alu accesses -system.cpu1.num_func_calls 7243553 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 19326205 # number of instructions that are conditional controls -system.cpu1.num_int_insts 135255426 # number of integer instructions -system.cpu1.num_fp_insts 113335 # number of float instructions -system.cpu1.num_int_register_reads 197658337 # number of times the integer registers were read -system.cpu1.num_int_register_writes 107430286 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 186014 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 88856 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 33354822 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 33290251 # number of times the CC registers were written -system.cpu1.num_mem_refs 44840861 # number of memory refs -system.cpu1.num_load_insts 23441337 # Number of load instructions -system.cpu1.num_store_insts 21399524 # Number of store instructions -system.cpu1.num_idle_cycles 1222996834.683689 # Number of idle cycles -system.cpu1.num_busy_cycles 31120518.316311 # Number of busy cycles -system.cpu1.not_idle_fraction 0.024815 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.975185 # Percentage of idle cycles -system.cpu1.Branches 28029112 # Number of branches fetched +system.cpu1.committedInsts 107495721 # Number of instructions committed +system.cpu1.committedOps 126075283 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 115907756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 113126 # Number of float alu accesses +system.cpu1.num_func_calls 6382091 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16276077 # number of instructions that are conditional controls +system.cpu1.num_int_insts 115907756 # number of integer instructions +system.cpu1.num_fp_insts 113126 # number of float instructions +system.cpu1.num_int_register_reads 166908100 # number of times the integer registers were read +system.cpu1.num_int_register_writes 91871167 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 184275 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91240 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 27698310 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27628060 # number of times the CC registers were written +system.cpu1.num_mem_refs 38485648 # number of memory refs +system.cpu1.num_load_insts 20241154 # Number of load instructions +system.cpu1.num_store_insts 18244494 # Number of store instructions +system.cpu1.num_idle_cycles 1161627733.273481 # Number of idle cycles +system.cpu1.num_busy_cycles 24464883.726519 # Number of busy cycles +system.cpu1.not_idle_fraction 0.020626 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.979374 # Percentage of idle cycles +system.cpu1.Branches 23916118 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 102409853 69.40% 69.40% # Class of executed instruction -system.cpu1.op_class::IntMult 296498 0.20% 69.60% # Class of executed instruction -system.cpu1.op_class::IntDiv 11247 0.01% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 12292 0.01% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu1.op_class::MemRead 23441337 15.88% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 21399524 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 87373708 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 271273 0.22% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 11107 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 12264 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::MemRead 20241154 16.04% 85.54% # Class of executed instruction +system.cpu1.op_class::MemWrite 18244494 14.46% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 147570793 # Class of executed instruction -system.cpu2.branchPred.lookups 45471146 # Number of BP lookups -system.cpu2.branchPred.condPredicted 31973875 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2129408 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 32992156 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 23695609 # Number of BTB hits +system.cpu1.op_class::total 126154042 # Class of executed instruction +system.cpu2.branchPred.lookups 39396533 # Number of BP lookups +system.cpu2.branchPred.condPredicted 27362101 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1971184 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 28599658 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20206635 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.821948 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 5443991 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 364384 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.653415 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4844874 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 318265 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1474,61 +1481,59 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 113177 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 113177 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 8706 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 39954 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 113177 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 113177 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 113177 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 48660 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 26968.937526 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 23542.983422 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 19014.556180 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 48252 99.16% 99.16% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 346 0.71% 99.87% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 19 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 17 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 48660 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000225500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000225500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000225500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 39954 82.11% 82.11% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 8706 17.89% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 48660 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 113177 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 92743 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 92743 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6709 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 28755 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 92743 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 92743 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 92743 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 35464 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 24952.261448 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 21836.970286 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 14872.403453 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 35314 99.58% 99.58% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 126 0.36% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 14 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 6 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 35464 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 28755 81.08% 81.08% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 6709 18.92% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 35464 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 92743 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 113177 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 48660 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 92743 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 35464 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 48660 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 161837 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 35464 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 128207 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 32304432 # DTB read hits -system.cpu2.dtb.read_misses 94453 # DTB read misses -system.cpu2.dtb.write_hits 28220489 # DTB write hits -system.cpu2.dtb.write_misses 18724 # DTB write misses -system.cpu2.dtb.flush_tlb 1254 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28135338 # DTB read hits +system.cpu2.dtb.read_misses 77405 # DTB read misses +system.cpu2.dtb.write_hits 24723604 # DTB write hits +system.cpu2.dtb.write_misses 15338 # DTB write misses +system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 6517 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 25531 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2547 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 22464 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 74 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 2032 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 4198 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 32398885 # DTB read accesses -system.cpu2.dtb.write_accesses 28239213 # DTB write accesses +system.cpu2.dtb.perms_faults 3778 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28212743 # DTB read accesses +system.cpu2.dtb.write_accesses 24738942 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 60524921 # DTB hits -system.cpu2.dtb.misses 113177 # DTB misses -system.cpu2.dtb.accesses 60638098 # DTB accesses +system.cpu2.dtb.hits 52858942 # DTB hits +system.cpu2.dtb.misses 92743 # DTB misses +system.cpu2.dtb.accesses 52951685 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1558,86 +1563,86 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 29761 # Table walker walks requested -system.cpu2.itb.walker.walksLong 29761 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1942 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 24191 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 29761 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 29761 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 29761 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 26133 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 29367.313359 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25512.670377 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 21362.014142 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 13922 53.27% 53.27% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11740 44.92% 98.20% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.20% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 361 1.38% 99.58% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.25% 99.84% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 6 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 20 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 6 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 26133 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 27058 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27058 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1852 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22698 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27058 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27058 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27058 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24550 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 28387.494908 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25558.389161 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 15951.956543 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12868 52.42% 52.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11496 46.83% 99.24% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 141 0.57% 99.82% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 26 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 5 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24550 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 24191 92.57% 92.57% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1942 7.43% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 26133 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22698 92.46% 92.46% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1852 7.54% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24550 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 29761 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 29761 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27058 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27058 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 26133 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 26133 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 55894 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 78881959 # ITB inst hits -system.cpu2.itb.inst_misses 29761 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24550 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24550 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51608 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 67882722 # ITB inst hits +system.cpu2.itb.inst_misses 27058 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1254 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 6517 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 18937 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 16669 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 67145 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 53735 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 78911720 # ITB inst accesses -system.cpu2.itb.hits 78881959 # DTB hits -system.cpu2.itb.misses 29761 # DTB misses -system.cpu2.itb.accesses 78911720 # DTB accesses -system.cpu2.numCycles 7033284242 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 67909780 # ITB inst accesses +system.cpu2.itb.hits 67882722 # DTB hits +system.cpu2.itb.misses 27058 # DTB misses +system.cpu2.itb.accesses 67909780 # DTB accesses +system.cpu2.numCycles 6659969764 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 166119965 # Number of instructions committed -system.cpu2.committedOps 194630787 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 16695727 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1592 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95760838731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 42.338585 # CPI: cycles per instruction -system.cpu2.ipc 0.023619 # IPC: instructions per cycle +system.cpu2.committedInsts 144540812 # Number of instructions committed +system.cpu2.committedOps 169698177 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 13684727 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1569 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95895764240 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 46.076742 # CPI: cycles per instruction +system.cpu2.ipc 0.021703 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 311878847 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6721405395 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 81889340 # Number of BP lookups -system.cpu3.branchPred.condPredicted 56169669 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3380866 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 55493963 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 40219158 # Number of BTB hits +system.cpu2.tickCycles 269319044 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6390650720 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 73106797 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49433479 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3258695 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 49334876 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 35656978 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 72.474835 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 10439836 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 109057 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 72.275398 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9555620 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 104634 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1667,90 +1672,88 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 587832 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 587832 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 11030 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 61410 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 367052 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 220780 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2589.344596 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 16088.611072 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 219110 99.24% 99.24% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 781 0.35% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 609 0.28% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 110 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-393215 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 220780 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 282413 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 23694.059764 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 19376.224176 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 20061.278653 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 276792 98.01% 98.01% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3971 1.41% 99.42% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 1088 0.39% 99.80% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 102 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 289 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 71 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 75 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 16 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 282413 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -34655191100 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean -0.302186 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -35339735100 101.98% 101.98% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 378573500 -1.09% 100.88% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 130659500 -0.38% 100.51% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 81429500 -0.23% 100.27% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 31558000 -0.09% 100.18% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 16139000 -0.05% 100.13% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 19404500 -0.06% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 22341500 -0.06% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 4213500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 186000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 24000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 5000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 6000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::52-55 2500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::56-59 1500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -34655191100 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 61410 84.77% 84.77% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 11030 15.23% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 72440 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 587832 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walks 494873 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 494873 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8038 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49628 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 307549 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 187324 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2356.267750 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 14281.156299 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 186079 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 697 0.37% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 387 0.21% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 69 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 51 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 14 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 187324 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 229131 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22686.146789 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18317.810397 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 18596.429018 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 224486 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3513 1.53% 99.51% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 846 0.37% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 43 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 153 0.07% 99.96% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 48 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 24 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 229131 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -24996742720 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean -0.101724 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -25553833720 102.23% 102.23% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 304691500 -1.22% 101.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 107266500 -0.43% 100.58% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 67844000 -0.27% 100.31% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 24788500 -0.10% 100.21% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 14749500 -0.06% 100.15% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 13689000 -0.05% 100.10% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 19439000 -0.08% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 4284000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 178500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 52500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::44-47 105500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::48-51 2500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -24996742720 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 49628 86.06% 86.06% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8038 13.94% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 57666 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 494873 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 587832 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 72440 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 494873 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57666 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 72440 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 660272 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57666 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 552539 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 65734744 # DTB read hits -system.cpu3.dtb.read_misses 407673 # DTB read misses -system.cpu3.dtb.write_hits 50830095 # DTB write hits -system.cpu3.dtb.write_misses 180159 # DTB write misses -system.cpu3.dtb.flush_tlb 1253 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 58275132 # DTB read hits +system.cpu3.dtb.read_misses 338945 # DTB read misses +system.cpu3.dtb.write_hits 45320334 # DTB write hits +system.cpu3.dtb.write_misses 155928 # DTB write misses +system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 34753 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 6443 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11379 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 30010 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 4724 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 35079 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 66142417 # DTB read accesses -system.cpu3.dtb.write_accesses 51010254 # DTB write accesses +system.cpu3.dtb.perms_faults 33145 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 58614077 # DTB read accesses +system.cpu3.dtb.write_accesses 45476262 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 116564839 # DTB hits -system.cpu3.dtb.misses 587832 # DTB misses -system.cpu3.dtb.accesses 117152671 # DTB accesses +system.cpu3.dtb.hits 103595466 # DTB hits +system.cpu3.dtb.misses 494873 # DTB misses +system.cpu3.dtb.accesses 104090339 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1780,391 +1783,387 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 63234 # Table walker walks requested -system.cpu3.itb.walker.walksLong 63234 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2096 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42908 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8590 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 54644 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 2021.164263 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 13009.185259 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 53981 98.79% 98.79% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 301 0.55% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 60 0.11% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 76 0.14% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 174 0.32% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 22 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 54644 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 53594 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 30266.951524 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 25142.604210 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 25912.141235 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 52174 97.35% 97.35% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 327 0.61% 97.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 902 1.68% 99.64% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 65 0.12% 99.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 86 0.16% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 19 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-458751 14 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 53594 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -34657916600 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.961535 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.183175 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1283225616 3.70% 3.70% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -33417551984 96.42% 100.12% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 37526500 -0.11% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 4293000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 605000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 220500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 216000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -34657916600 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 42908 95.34% 95.34% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 2096 4.66% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 45004 # Table walker page sizes translated +system.cpu3.itb.walker.walks 60079 # Table walker walks requested +system.cpu3.itb.walker.walksLong 60079 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1942 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41391 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8262 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1695.563232 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 10747.357060 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-65535 51612 99.60% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-131071 80 0.15% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-196607 107 0.21% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-262143 10 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 51817 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 51595 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 29163.077818 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 24579.723425 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 21924.280551 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 28123 54.51% 54.51% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 22407 43.43% 97.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 307 0.60% 98.53% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 32 0.06% 98.59% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 434 0.84% 99.43% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 175 0.34% 99.77% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 23 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 26 0.05% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 39 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-425983 9 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 51595 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -33589148812 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 1.086684 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 2957203824 -8.80% -8.80% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -36586535136 108.92% 100.12% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 35384500 -0.11% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 4248500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 527000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 22500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -33589148812 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 41391 95.52% 95.52% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1942 4.48% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 43333 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 63234 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 63234 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60079 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60079 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 45004 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 45004 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 108238 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 57820095 # ITB inst hits -system.cpu3.itb.inst_misses 63234 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43333 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43333 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 103412 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 52677682 # ITB inst hits +system.cpu3.itb.inst_misses 60079 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1253 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 26508 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11379 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 23578 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 125417 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 114813 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 57883329 # ITB inst accesses -system.cpu3.itb.hits 57820095 # DTB hits -system.cpu3.itb.misses 63234 # DTB misses -system.cpu3.itb.accesses 57883329 # DTB accesses -system.cpu3.numCycles 434126905 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 52737761 # ITB inst accesses +system.cpu3.itb.hits 52677682 # DTB hits +system.cpu3.itb.misses 60079 # DTB misses +system.cpu3.itb.accesses 52737761 # DTB accesses +system.cpu3.numCycles 367538464 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 146156253 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 363700570 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 81889340 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 50658994 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 264117346 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7731870 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1657260 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 10621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2103 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 3389024 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 101744 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 6028 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 57676698 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2068277 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 25207 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 419306139 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.016419 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.270112 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 137661230 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 325116146 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 73106797 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45212598 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 207107906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7385298 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1491112 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 7917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 2707 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2935817 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 92613 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 5851 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 52545073 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2005603 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 24026 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 352997650 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.078283 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.326168 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 329556532 78.60% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 11088732 2.64% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 11228658 2.68% 83.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 8092801 1.93% 85.85% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 18140495 4.33% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5492721 1.31% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 6039069 1.44% 92.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 5230958 1.25% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 24436173 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 272813729 77.28% 77.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10027908 2.84% 80.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10164479 2.88% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7468497 2.12% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15406630 4.36% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5031910 1.43% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5399943 1.53% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4793152 1.36% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 21891402 6.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 419306139 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.188630 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.837775 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 117967967 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 225080995 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 64189505 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 9003410 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 3062237 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11922856 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 815112 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 398264937 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2526332 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 3062237 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 122799246 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 19956782 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 172569750 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 68252780 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 32663221 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 389247398 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 82681 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1469691 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 1381042 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 19259922 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2209 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 374365889 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 605949673 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 460740509 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 465469 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 317859037 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 56506847 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 10256222 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 9051847 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 50890020 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 62384560 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 53396526 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 8272508 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8814741 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 368973435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 10287007 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 371458257 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 527403 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 47542551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 30606523 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 220793 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 419306139 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.885888 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.625743 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 352997650 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.198909 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.884577 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 112522162 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 171201406 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 59221662 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7151544 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2899090 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 10994019 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 804734 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 355281721 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2474096 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 2899090 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 116622448 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14081573 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 135939902 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 62181324 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 21271328 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 346993975 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 66296 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1234254 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 930282 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 10943562 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2087 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 331516858 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 531452942 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 410096361 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 485069 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 278766720 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 52750133 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7968822 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6860328 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39681669 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 56098818 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 47638464 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7335407 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 7944863 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 329650835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7964776 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 329496224 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 469719 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 44173010 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 28338373 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 197137 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 352997650 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.933423 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.659576 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 272370865 64.96% 64.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 63755387 15.20% 80.16% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 26527410 6.33% 86.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 18802792 4.48% 90.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 14265193 3.40% 94.38% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9871415 2.35% 96.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6899561 1.65% 98.38% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 4083667 0.97% 99.35% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2729849 0.65% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 224922038 63.72% 63.72% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 52868564 14.98% 78.69% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24171570 6.85% 85.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17197419 4.87% 90.41% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 12806059 3.63% 94.04% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9032778 2.56% 96.60% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6064654 1.72% 98.32% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3560331 1.01% 99.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2374237 0.67% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 419306139 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 352997650 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1874044 25.07% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 14207 0.19% 25.26% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1529 0.02% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 3115796 41.69% 66.97% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2468334 33.03% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1654999 25.37% 25.37% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 15899 0.24% 25.61% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1445 0.02% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.63% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2663997 40.83% 66.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2188300 33.54% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 252023231 67.85% 67.85% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 873366 0.24% 68.08% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 40952 0.01% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 37311 0.01% 68.10% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 67010678 18.04% 86.14% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 51472700 13.86% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 223294743 67.77% 67.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 773232 0.23% 68.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 39732 0.01% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.02% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 41118 0.01% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 59435929 18.04% 86.07% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 45911451 13.93% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 371458257 # Type of FU issued -system.cpu3.iq.rate 0.855644 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 7473910 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.020120 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1169596628 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 426913403 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 357682131 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 627338 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 312499 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 278370 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 378596824 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 335324 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2893628 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 329496224 # Type of FU issued +system.cpu3.iq.rate 0.896495 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6524640 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019802 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1018336747 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 381842202 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 317599035 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 647710 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 321899 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 289386 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 335674602 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 346243 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2638413 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9605329 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 12315 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 430621 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 5363996 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 8879523 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11866 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 381459 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4873286 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2422339 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 5589935 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2106312 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4209032 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 3062237 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 10687906 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 7763233 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 379342357 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1032736 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 62384560 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 53396526 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 8880600 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 160790 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 7539596 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 430621 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1536012 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1351234 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2887246 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 367483062 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 65729081 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3395466 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 2899090 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8833562 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 4011376 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 337691030 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 991613 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 56098818 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 47638464 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6709459 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 120203 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3844571 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 381459 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1469292 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1295892 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2765184 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 325759751 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 58266124 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3247625 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 81915 # number of nop insts executed -system.cpu3.iew.exec_refs 116559779 # number of memory reference insts executed -system.cpu3.iew.exec_branches 68181123 # Number of branches executed -system.cpu3.iew.exec_stores 50830698 # Number of stores executed -system.cpu3.iew.exec_rate 0.846488 # Inst execution rate -system.cpu3.iew.wb_sent 358682036 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 357960501 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 176824720 # num instructions producing a value -system.cpu3.iew.wb_consumers 308531947 # num instructions consuming a value +system.cpu3.iew.exec_nop 75419 # number of nop insts executed +system.cpu3.iew.exec_refs 103584875 # number of memory reference insts executed +system.cpu3.iew.exec_branches 60432321 # Number of branches executed +system.cpu3.iew.exec_stores 45318751 # Number of stores executed +system.cpu3.iew.exec_rate 0.886328 # Inst execution rate +system.cpu3.iew.wb_sent 318561323 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 317888421 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 157110188 # num instructions producing a value +system.cpu3.iew.wb_consumers 272714221 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.824553 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.573116 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.864912 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576098 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 47576745 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 10066214 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2576993 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 411229636 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.806649 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.806100 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 44200110 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7767639 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2464984 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 345475072 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.849389 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.847862 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 288483917 70.15% 70.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 61981955 15.07% 85.22% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 20267968 4.93% 90.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9217498 2.24% 92.39% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6652848 1.62% 94.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 4003479 0.97% 94.99% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3757671 0.91% 95.90% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2541712 0.62% 96.52% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 14322588 3.48% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 238897207 69.15% 69.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51619563 14.94% 84.09% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18609130 5.39% 89.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8398025 2.43% 91.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6043748 1.75% 93.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3655661 1.06% 94.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3455010 1.00% 95.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2146483 0.62% 96.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12650245 3.66% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 411229636 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 282128500 # Number of instructions committed -system.cpu3.commit.committedOps 331717886 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 345475072 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 249760952 # Number of instructions committed +system.cpu3.commit.committedOps 293442596 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 100811760 # Number of memory references committed -system.cpu3.commit.loads 52779230 # Number of loads committed -system.cpu3.commit.membars 2341382 # Number of memory barriers committed -system.cpu3.commit.branches 63187183 # Number of branches committed -system.cpu3.commit.fp_insts 266447 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 304028105 # Number of committed integer instructions. -system.cpu3.commit.function_calls 8134067 # Number of function calls committed. +system.cpu3.commit.refs 89984472 # Number of memory references committed +system.cpu3.commit.loads 47219294 # Number of loads committed +system.cpu3.commit.membars 1969895 # Number of memory barriers committed +system.cpu3.commit.branches 55759591 # Number of branches committed +system.cpu3.commit.fp_insts 278553 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 269644169 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7403511 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 230158153 69.38% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 685246 0.21% 69.59% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 30654 0.01% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.60% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 32073 0.01% 69.61% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 52779230 15.91% 85.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 48032530 14.48% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 202786729 69.11% 69.11% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 605783 0.21% 69.31% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 30019 0.01% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 35593 0.01% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 47219294 16.09% 85.43% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 42765178 14.57% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 331717886 # Class of committed instruction -system.cpu3.commit.bw_lim_events 14322588 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 773873016 # The number of ROB reads -system.cpu3.rob.rob_writes 766677768 # The number of ROB writes -system.cpu3.timesIdled 2386400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14820766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98598665590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 282128500 # Number of Instructions Simulated -system.cpu3.committedOps 331717886 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.538756 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.538756 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.649876 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.649876 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 433777374 # number of integer regfile reads -system.cpu3.int_regfile_writes 254753352 # number of integer regfile writes -system.cpu3.fp_regfile_reads 550692 # number of floating regfile reads -system.cpu3.fp_regfile_writes 344140 # number of floating regfile writes -system.cpu3.cc_regfile_reads 80727735 # number of cc regfile reads -system.cpu3.cc_regfile_writes 81413298 # number of cc regfile writes -system.cpu3.misc_regfile_reads 763399482 # number of misc regfile reads -system.cpu3.misc_regfile_writes 10252205 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40277 # Transaction distribution -system.iobus.trans_dist::ReadResp 40277 # Transaction distribution -system.iobus.trans_dist::WriteReq 136543 # Transaction distribution -system.iobus.trans_dist::WriteResp 136543 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47710 # Packet count per connected master and slave (bytes) +system.cpu3.commit.op_class_0::total 293442596 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12650245 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 668392773 # The number of ROB reads +system.cpu3.rob.rob_writes 682819370 # The number of ROB writes +system.cpu3.timesIdled 2353613 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 14540814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98630935405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249760952 # Number of Instructions Simulated +system.cpu3.committedOps 293442596 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.471561 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.471561 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.679551 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.679551 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 384013216 # number of integer regfile reads +system.cpu3.int_regfile_writes 227255326 # number of integer regfile writes +system.cpu3.fp_regfile_reads 562445 # number of floating regfile reads +system.cpu3.fp_regfile_writes 347476 # number of floating regfile writes +system.cpu3.cc_regfile_reads 69354543 # number of cc regfile reads +system.cpu3.cc_regfile_writes 70004499 # number of cc regfile writes +system.cpu3.misc_regfile_reads 654418825 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7814462 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40238 # Transaction distribution +system.iobus.trans_dist::ReadResp 40238 # Transaction distribution +system.iobus.trans_dist::WriteReq 136511 # Transaction distribution +system.iobus.trans_dist::WriteResp 136511 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2174,18 +2173,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29444 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122592 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353640 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47730 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2195,99 +2194,97 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155722 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492112 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27944000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7491974 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 34324500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 9762000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13360500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 141000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 21520500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 37000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 46500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 256543158 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 257733143 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 57567000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 59729000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 67102000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 75398000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.434887 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.420601 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089149976509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.535229 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.899658 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220952 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.431229 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652180 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089166487009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547306 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873295 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429581 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651288 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses -system.iocache.demand_misses::total 8860 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8820 # number of overall misses -system.iocache.overall_misses::total 8860 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 731246845 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 731246845 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6288189313 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6288189313 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 731246845 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 731246845 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 731246845 # number of overall miss cycles -system.iocache.overall_miss_latency::total 731246845 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1078707234 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1078707234 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 6251807909 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6251807909 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1078707234 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1078707234 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1078707234 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1078707234 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2301,503 +2298,506 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 82907.805556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 82561.459298 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58953.248641 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 58953.248641 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 82907.805556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 82533.503950 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 82907.805556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 82533.503950 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14483 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 122399.549983 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121887.823051 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58612.164451 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58612.164451 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 122399.549983 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121846.519146 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 122399.549983 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121846.519146 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22659 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1449 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2381 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.995169 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.516590 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 3943 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 48464 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 48464 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 3943 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 3943 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 3943 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 3943 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 534096845 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 534096845 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3864989313 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3864989313 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 534096845 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 534096845 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 534096845 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 534096845 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.445185 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.454361 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.454361 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.445034 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.447052 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.445034 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135454.436977 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135454.436977 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79749.696950 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79749.696950 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135454.436977 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135454.436977 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135454.436977 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135454.436977 # average overall mshr miss latency +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 5719 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5719 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 48024 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 48024 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 5719 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 5719 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 5719 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 792757234 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 792757234 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3850607909 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3850607909 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 792757234 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 792757234 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 792757234 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 792757234 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648928 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.646215 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.450236 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.450236 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.648928 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.645996 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.648928 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.645996 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138618.155971 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138618.155971 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80180.907650 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80180.907650 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138618.155971 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 138618.155971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138618.155971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 138618.155971 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1727571 # number of replacements -system.l2c.tags.tagsinuse 65366.434127 # Cycle average of tags in use -system.l2c.tags.total_refs 52377191 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1790828 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.247472 # Average number of references to valid blocks. +system.l2c.tags.replacements 1137204 # number of replacements +system.l2c.tags.tagsinuse 65362.357170 # Cycle average of tags in use +system.l2c.tags.total_refs 47194222 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1199974 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.329370 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35675.383365 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 150.314968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 221.842308 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3453.336849 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8628.573919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 25.870351 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 46.456847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 201.612441 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2287.318567 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 59.687727 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 74.075629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1384.134493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3678.892327 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.341060 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 136.749974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2263.424269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 6988.419034 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.544363 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002294 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003385 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052694 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.131662 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000395 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.034902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.001130 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.021120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.056135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002087 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.034537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.106635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997413 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62986 # Occupied blocks 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31.153423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 51.715903 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 455.445147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2127.472553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 35.646762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 56.154607 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1628.641788 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3512.634896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 79.313177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 110.411472 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2677.526600 # Average occupied blocks per requestor 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0.016353 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006415 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.068006 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.005986 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005859 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008416 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.070251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.016353 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 127917.362768 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.366071 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70768.055556 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70756.856540 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70743.204868 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 72000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121397.901159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122864.802280 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 144150.417161 # average ReadExReq mshr miss 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mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121341.477024 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 130927.512718 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 147640.760141 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 137669.293940 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124292.127072 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121453.775039 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122063.958913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819 # average overall mshr miss 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-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127647.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121453.775039 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122063.958913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 128700.922819 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 126037.194474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123730.722737 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123615.671363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128510.961214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 129663.173653 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126131.350741 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 140112.298070 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 131246.239664 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174583.310192 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 172786.914860 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 169478.707224 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172349.352132 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 179729.517982 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178025.447849 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173370.576099 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177081.501976 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177063.691290 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175322.757112 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171383.232370 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 174644.779897 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120893.938724 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122452.633676 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 136905.863566 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 128975.972340 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121591.873778 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123654.513889 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125823.742727 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124418.169352 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122981.007553 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125103.017341 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131054.734458 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127945.486183 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120472.951639 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 128899.178590 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 145632.611554 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135853.629765 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121591.873778 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121679.307110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123654.513889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123465.481419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125823.742727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134289.236907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 127978.300496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126609.289617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128636.503067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121591.873778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121679.307110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 126240.208877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 128790.087464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123654.513889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123465.481419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128703.356367 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 127690.553746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125823.742727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134289.236907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 127978.300496 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185061.255855 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184535.262856 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178655.153125 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182699.259967 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191813.877875 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 191010.983103 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183657.028114 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188702.921646 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188302.123773 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187664.489311 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 181105.058362 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 185607.618412 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76751 # Transaction distribution -system.membus.trans_dist::ReadResp 550767 # Transaction distribution -system.membus.trans_dist::WriteReq 33656 # Transaction distribution -system.membus.trans_dist::WriteResp 33656 # Transaction distribution -system.membus.trans_dist::Writeback 1590295 # Transaction distribution -system.membus.trans_dist::CleanEvict 250132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40589 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40592 # Transaction distribution -system.membus.trans_dist::ReadExReq 1356297 # Transaction distribution -system.membus.trans_dist::ReadExResp 1356297 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 474016 # Transaction distribution +system.membus.trans_dist::ReadReq 76702 # Transaction distribution +system.membus.trans_dist::ReadResp 438040 # Transaction distribution +system.membus.trans_dist::WriteReq 33616 # Transaction distribution +system.membus.trans_dist::WriteResp 33616 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1054215 # Transaction distribution +system.membus.trans_dist::CleanEvict 195061 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34374 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34376 # Transaction distribution +system.membus.trans_dist::ReadExReq 877287 # Transaction distribution +system.membus.trans_dist::ReadExResp 877287 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 361338 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122592 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122464 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5542839 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5672278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6014819 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155722 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3755613 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3884874 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 342734 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4227608 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211708448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 211877938 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7303680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7303680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219181618 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1560 # Total snoops (count) -system.membus.snoop_fanout::samples 3931023 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139526112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 139695420 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7304128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7304128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 146999548 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1634 # Total snoops (count) +system.membus.snoop_fanout::samples 2741682 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3931023 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2741682 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3931023 # Request fanout histogram -system.membus.reqLayer0.occupancy 67063498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2741682 # Request fanout histogram +system.membus.reqLayer0.occupancy 69473500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1838002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 4875978841 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 2993221129 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4492458378 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2766254947 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 103510165 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 111131085 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3148,11 +3148,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -3191,60 +3191,61 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 57525316 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 29151092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3060 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2399 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2399 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 51354926 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26009056 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2855 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2048 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2048 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1748199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 26397420 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33656 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33656 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 9662082 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 19582233 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51062 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51066 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2478951 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2478951 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16735129 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7917622 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1294933 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1246469 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 50288517 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35153401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 878892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2158697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 88479507 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1071219732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1236530654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3178896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7750232 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2318679514 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2264699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 60538896 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.012147 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109543 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1478127 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23632068 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33616 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33616 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 7917832 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15694537 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2278182 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 42970 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 42972 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1968733 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1968733 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15697459 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6461865 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1271562 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1223538 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47175640 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29164933 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 814493 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1705007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 78860073 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2009256084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1017810408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2934600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6010000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3036011092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1652274 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37979201 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016509 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127422 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 59803521 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 735375 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37352210 98.35% 98.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 626991 1.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 60538896 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 23067770487 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 767706 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 37979201 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 30549015491 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 656694 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16065319902 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15157992691 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 9498707196 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7808308250 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 310622695 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 290510210 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 847575032 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 695723441 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index b9366b9f7..79264f671 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.289289 # Number of seconds simulated -sim_ticks 51289289109000 # Number of ticks simulated -final_tick 51289289109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.329060 # Number of seconds simulated +sim_ticks 51329059921000 # Number of ticks simulated +final_tick 51329059921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116964 # Simulator instruction rate (inst/s) -host_op_rate 137448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6754182467 # Simulator tick rate (ticks/s) -host_mem_usage 688124 # Number of bytes of host memory used -host_seconds 7593.71 # Real time elapsed on the host -sim_insts 888194021 # Number of instructions simulated -sim_ops 1043742869 # Number of ops (including micro ops) simulated +host_inst_rate 121954 # Simulator instruction rate (inst/s) +host_op_rate 143308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7039149523 # Simulator tick rate (ticks/s) +host_mem_usage 740464 # Number of bytes of host memory used +host_seconds 7291.94 # Real time elapsed on the host +sim_insts 889279572 # Number of instructions simulated +sim_ops 1044993075 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 151872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 139200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4024896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41634016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 129408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3236928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 42391336 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 430592 # Number of bytes read from this memory -system.physmem.bytes_read::total 92275272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4024896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3236928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7261824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78300352 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 138560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 132032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3631936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41395808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 145856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 130368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3527872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 42283560 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 424576 # Number of bytes read from this memory +system.physmem.bytes_read::total 91810568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3631936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3527872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7159808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78035520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78320932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2373 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 62889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 650540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2022 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 50577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 662369 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6728 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1441814 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1223443 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78056100 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56749 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 646818 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2279 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2037 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 660685 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6634 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1434553 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1219305 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1226016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 78474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 811749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 826514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1799114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 78474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1526641 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1221878 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 70758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 806479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 68731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 823774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1788666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 68731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 139488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1520299 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1527043 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1526641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 78474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 811749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 826916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3326157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1441814 # Number of read requests accepted -system.physmem.writeReqs 1226016 # Number of write requests accepted -system.physmem.readBursts 1441814 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1226016 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 92235136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40960 # Total number of bytes read from write queue -system.physmem.bytesWritten 78321024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 92275272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78320932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 640 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1520700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1520299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 806479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 68731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 824175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3309366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1434553 # Number of read requests accepted +system.physmem.writeReqs 1221878 # Number of write requests accepted +system.physmem.readBursts 1434553 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1221878 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 91768384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43008 # Total number of bytes read from write queue +system.physmem.bytesWritten 78056128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 91810568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78056100 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 672 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 143274 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 85394 # Per bank write bursts -system.physmem.perBankRdBursts::1 90340 # Per bank write bursts -system.physmem.perBankRdBursts::2 85251 # Per bank write bursts -system.physmem.perBankRdBursts::3 84742 # Per bank write bursts -system.physmem.perBankRdBursts::4 87352 # Per bank write bursts -system.physmem.perBankRdBursts::5 95958 # Per bank write bursts -system.physmem.perBankRdBursts::6 87724 # Per bank write bursts -system.physmem.perBankRdBursts::7 87120 # Per bank write bursts -system.physmem.perBankRdBursts::8 85128 # Per bank write bursts -system.physmem.perBankRdBursts::9 115032 # Per bank write bursts -system.physmem.perBankRdBursts::10 93810 # Per bank write bursts -system.physmem.perBankRdBursts::11 94841 # Per bank write bursts -system.physmem.perBankRdBursts::12 83101 # Per bank write bursts -system.physmem.perBankRdBursts::13 88197 # Per bank write bursts -system.physmem.perBankRdBursts::14 87648 # Per bank write bursts -system.physmem.perBankRdBursts::15 89536 # Per bank write bursts -system.physmem.perBankWrBursts::0 72684 # Per bank write bursts -system.physmem.perBankWrBursts::1 76025 # Per bank write bursts -system.physmem.perBankWrBursts::2 73393 # Per bank write bursts -system.physmem.perBankWrBursts::3 74816 # Per bank write bursts -system.physmem.perBankWrBursts::4 75820 # Per bank write bursts -system.physmem.perBankWrBursts::5 81492 # Per bank write bursts -system.physmem.perBankWrBursts::6 75165 # Per bank write bursts -system.physmem.perBankWrBursts::7 76353 # Per bank write bursts -system.physmem.perBankWrBursts::8 74241 # Per bank write bursts -system.physmem.perBankWrBursts::9 82215 # Per bank write bursts -system.physmem.perBankWrBursts::10 79031 # Per bank write bursts -system.physmem.perBankWrBursts::11 79534 # Per bank write bursts -system.physmem.perBankWrBursts::12 72343 # Per bank write bursts -system.physmem.perBankWrBursts::13 77292 # Per bank write bursts -system.physmem.perBankWrBursts::14 76022 # Per bank write bursts -system.physmem.perBankWrBursts::15 77340 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 354445 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 86303 # Per bank write bursts +system.physmem.perBankRdBursts::1 88556 # Per bank write bursts +system.physmem.perBankRdBursts::2 87585 # Per bank write bursts +system.physmem.perBankRdBursts::3 86132 # Per bank write bursts +system.physmem.perBankRdBursts::4 85519 # Per bank write bursts +system.physmem.perBankRdBursts::5 93403 # Per bank write bursts +system.physmem.perBankRdBursts::6 87506 # Per bank write bursts +system.physmem.perBankRdBursts::7 86099 # Per bank write bursts +system.physmem.perBankRdBursts::8 84644 # Per bank write bursts +system.physmem.perBankRdBursts::9 113970 # Per bank write bursts +system.physmem.perBankRdBursts::10 93714 # Per bank write bursts +system.physmem.perBankRdBursts::11 93674 # Per bank write bursts +system.physmem.perBankRdBursts::12 83678 # Per bank write bursts +system.physmem.perBankRdBursts::13 89960 # Per bank write bursts +system.physmem.perBankRdBursts::14 85105 # Per bank write bursts +system.physmem.perBankRdBursts::15 88033 # Per bank write bursts +system.physmem.perBankWrBursts::0 73419 # Per bank write bursts +system.physmem.perBankWrBursts::1 74799 # Per bank write bursts +system.physmem.perBankWrBursts::2 75041 # Per bank write bursts +system.physmem.perBankWrBursts::3 76138 # Per bank write bursts +system.physmem.perBankWrBursts::4 74959 # Per bank write bursts +system.physmem.perBankWrBursts::5 79592 # Per bank write bursts +system.physmem.perBankWrBursts::6 75110 # Per bank write bursts +system.physmem.perBankWrBursts::7 75651 # Per bank write bursts +system.physmem.perBankWrBursts::8 74129 # Per bank write bursts +system.physmem.perBankWrBursts::9 81022 # Per bank write bursts +system.physmem.perBankWrBursts::10 78327 # Per bank write bursts +system.physmem.perBankWrBursts::11 79368 # Per bank write bursts +system.physmem.perBankWrBursts::12 72597 # Per bank write bursts +system.physmem.perBankWrBursts::13 77989 # Per bank write bursts +system.physmem.perBankWrBursts::14 74762 # Per bank write bursts +system.physmem.perBankWrBursts::15 76724 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 51289287954000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 51329058678000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1441799 # Read request sizes (log2) +system.physmem.readPktSize::6 1434538 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1223443 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 661868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 399209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 215391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 158760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1219305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 657679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 396498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 215329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 158489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -165,186 +165,185 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 755 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 29719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 73432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74626 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 75089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 77965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 79510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 90590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 97976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 76224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 79969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 72166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 562786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.056181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.751782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.834003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 224740 39.93% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 128751 22.88% 62.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55127 9.80% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26773 4.76% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23233 4.13% 81.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12910 2.29% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13583 2.41% 86.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9009 1.60% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68660 12.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 562786 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 70105 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.557036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 230.792990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 70100 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::10 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 42902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 73169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 74512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 75065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 77780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 77068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 77521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 84532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 78913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 91198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 97883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 80091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 71759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 561036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.697381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.440606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.820574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 224613 40.04% 40.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 128067 22.83% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 54948 9.79% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26347 4.70% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23416 4.17% 81.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12898 2.30% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13342 2.38% 86.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8863 1.58% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 68542 12.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 561036 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.526986 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 231.209031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 69847 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 70105 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 70105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.456187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.912950 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.915591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 54 0.08% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 21 0.03% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 10 0.01% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 61 0.09% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66123 94.32% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1498 2.14% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 202 0.29% 96.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 498 0.71% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 0.11% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 334 0.48% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 212 0.30% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 35 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 78 0.11% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 130 0.19% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.04% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 40 0.06% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 445 0.63% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 33 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 119 0.17% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 69852 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.460159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.920258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.852761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 44 0.06% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 27 0.04% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 11 0.02% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 61 0.09% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 65855 94.28% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1487 2.13% 96.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 231 0.33% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 500 0.72% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 71 0.10% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 334 0.48% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 206 0.29% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 35 0.05% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 69 0.10% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 137 0.20% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.04% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 32 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 488 0.70% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.05% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 34 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 111 0.16% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.03% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 70105 # Writes before turning the bus around for reads -system.physmem.totQLat 42013541205 # Total ticks spent queuing -system.physmem.totMemAccLat 69035553705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7205870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29152.30 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69852 # Writes before turning the bus around for reads +system.physmem.totQLat 41803653811 # Total ticks spent queuing +system.physmem.totMemAccLat 68688922561 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7169405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29154.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47902.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47904.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.35 # Average write queue length when enqueuing -system.physmem.readRowHits 1183295 # Number of row buffer hits during reads -system.physmem.writeRowHits 918857 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.08 # Row buffer hit rate for writes -system.physmem.avgGap 19225096.03 # Average gap between requests -system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2114615160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1153807875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5490264000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3925247040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349966598160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1237156507125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29688344543250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34288151582610 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.524687 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49388977684769 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712661860000 # Time in different power states +system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.57 # Average write queue length when enqueuing +system.physmem.readRowHits 1177173 # Number of row buffer hits during reads +system.physmem.writeRowHits 915297 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes +system.physmem.avgGap 19322564.25 # Average gap between requests +system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2106662040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1149468375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5468603400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3918514320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352564322640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1237967178795 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29711496726750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34314671476320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.523347 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49427496871292 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713989940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 187649331731 # Time in different power states +system.physmem_0.memoryStateTime::ACT 187567949958 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2140047000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1167684375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5750846400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4004756640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349966598160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240738244055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29685202677000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34288970853630 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.540660 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49383704909692 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712661860000 # Time in different power states +system.physmem_1.actEnergy 2134770120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1164805125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5715621600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3984668640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352564322640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1240798843035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29709012810750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34315375841910 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.537070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49423322508450 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713989940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192921720308 # Time in different power states +system.physmem_1.memoryStateTime::ACT 191746853550 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -374,15 +373,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131510280 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89076411 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5754624 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89205696 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 64088886 # Number of BTB hits +system.cpu0.branchPred.lookups 128171553 # Number of BP lookups +system.cpu0.branchPred.condPredicted 86901839 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5585684 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 86828453 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 62767092 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.843939 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17216191 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 189076 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.288622 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16853141 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186956 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -413,92 +412,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 879879 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 879879 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16451 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88924 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 539694 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 340185 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2660.496495 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15843.329302 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 337511 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1400 0.41% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 868 0.26% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 160 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 148 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 885239 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 885239 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16068 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88252 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 546727 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 338512 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2698.944203 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 16449.109677 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 335800 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1393 0.41% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 884 0.26% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 156 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 43 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::458752-524287 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 340185 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 407005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23314.236926 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18617.801732 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20825.488249 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 397459 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7042 1.73% 99.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1712 0.42% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 113 0.03% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 415 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 146 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 338512 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 409508 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23024.226633 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18496.792158 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19848.076678 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 400961 97.91% 97.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6256 1.53% 99.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1568 0.38% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 126 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 350 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 156 0.04% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 68 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 407005 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 376382023716 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.109107 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.663618 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 375374134216 99.73% 99.73% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 555470000 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 199772500 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 117350500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 45444000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 24549500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 26272500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 32439000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6175500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 322000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 376382023716 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 88924 84.39% 84.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16451 15.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 105375 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 879879 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 409508 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 369272261460 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.199871 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.721140 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 368268104460 99.73% 99.73% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 539578000 0.15% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 201182000 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 121167500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 48555500 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 26406000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26984000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 34302000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 5588500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 301000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 52000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 18000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 369272261460 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 88253 84.60% 84.60% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16068 15.40% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 104321 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 885239 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 879879 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 885239 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104321 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105375 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 985254 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104321 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 989560 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104450342 # DTB read hits -system.cpu0.dtb.read_misses 607388 # DTB read misses -system.cpu0.dtb.write_hits 80999803 # DTB write hits -system.cpu0.dtb.write_misses 272491 # DTB write misses -system.cpu0.dtb.flush_tlb 1103 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 102290715 # DTB read hits +system.cpu0.dtb.read_misses 610545 # DTB read misses +system.cpu0.dtb.write_hits 79331513 # DTB write hits +system.cpu0.dtb.write_misses 274694 # DTB write misses +system.cpu0.dtb.flush_tlb 1105 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21264 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 532 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 54933 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9612 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21571 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54684 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9578 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 55908 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105057730 # DTB read accesses -system.cpu0.dtb.write_accesses 81272294 # DTB write accesses +system.cpu0.dtb.perms_faults 56017 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 102901260 # DTB read accesses +system.cpu0.dtb.write_accesses 79606207 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 185450145 # DTB hits -system.cpu0.dtb.misses 879879 # DTB misses -system.cpu0.dtb.accesses 186330024 # DTB accesses +system.cpu0.dtb.hits 181622228 # DTB hits +system.cpu0.dtb.misses 885239 # DTB misses +system.cpu0.dtb.accesses 182507467 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -528,849 +524,848 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 105425 # Table walker walks requested -system.cpu0.itb.walker.walksLong 105425 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3033 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71538 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14522 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 90903 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1916.366897 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 12628.127488 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 89834 98.82% 98.82% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 539 0.59% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 99 0.11% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 130 0.14% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 200 0.22% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 51 0.06% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 18 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 102914 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102914 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2949 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69039 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14347 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88567 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1898.844942 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 12048.773919 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87489 98.78% 98.78% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 597 0.67% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 92 0.10% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 110 0.12% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 199 0.22% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 35 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 90903 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 89093 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29737.628096 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24673.282560 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 24049.122605 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 86936 97.58% 97.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 600 0.67% 98.25% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1294 1.45% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 93 0.10% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 133 0.15% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 89093 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 303340156184 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.819271 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -248434536268 -81.90% -81.90% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 551700406452 181.88% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 66884500 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6271500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 916000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 53500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 160500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 303340156184 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 71538 95.93% 95.93% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3033 4.07% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 74571 # Table walker page sizes translated +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88567 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86335 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29628.748480 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24429.301414 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 24451.958978 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84088 97.40% 97.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 706 0.82% 98.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1293 1.50% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 119 0.14% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 18 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 86335 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 279075367244 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.887042 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -247471426488 -88.68% -88.68% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 526476465732 188.65% 99.97% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 62141000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6800000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 1085000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 302000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 279075367244 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69039 95.90% 95.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2949 4.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 71988 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105425 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105425 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102914 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102914 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 179996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94464352 # ITB inst hits -system.cpu0.itb.inst_misses 105425 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71988 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71988 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 174902 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91881601 # ITB inst hits +system.cpu0.itb.inst_misses 102914 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1103 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1105 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21264 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 532 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41067 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21571 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40429 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204534 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 204535 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94569777 # ITB inst accesses -system.cpu0.itb.hits 94464352 # DTB hits -system.cpu0.itb.misses 105425 # DTB misses -system.cpu0.itb.accesses 94569777 # DTB accesses -system.cpu0.numCycles 693727147 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91984515 # ITB inst accesses +system.cpu0.itb.hits 91881601 # DTB hits +system.cpu0.itb.misses 102914 # DTB misses +system.cpu0.itb.accesses 91984515 # DTB accesses +system.cpu0.numCycles 691170563 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 245689923 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 583659918 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131510280 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81305077 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 403973689 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13146062 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2696063 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 24792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 6132 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5442737 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 182065 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 4382 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94242396 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3550844 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 42244 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 664592540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.028282 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.281038 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 239962884 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 570438077 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 128171553 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 79620233 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 407738854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 12781952 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2594971 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 25425 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5359 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5458708 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 162648 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 3329 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 91660544 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3463851 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41672 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 662342878 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.009072 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.262587 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 520383096 78.30% 78.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18093254 2.72% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18296207 2.75% 83.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13332643 2.01% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28010014 4.21% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9092439 1.37% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9727305 1.46% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8422108 1.27% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39235474 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 521294405 78.70% 78.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 17644727 2.66% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 17609553 2.66% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13023217 1.97% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28132742 4.25% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8705409 1.31% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9465006 1.43% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8172202 1.23% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 38295617 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 664592540 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189571 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.841339 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 199631749 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 341256701 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105213142 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13320667 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5167977 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19724467 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1425325 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 637042209 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4387868 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5167977 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 207139071 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 31235122 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 259336821 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 110889608 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 50821415 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 622130396 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 110301 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2210574 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1917918 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31535075 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3960 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 595274899 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 956990256 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 735490255 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 762145 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 501553477 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 93721422 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 14866567 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 12875390 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 74435077 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100241817 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85151630 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13697674 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14727627 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 590625310 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 14935431 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 591459977 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 828967 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 78563814 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 50313782 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 364460 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 664592540 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.889959 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.628761 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 662342878 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.185441 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.825322 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 194658503 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 347202119 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 101960102 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13505854 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5013938 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19069784 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1396202 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 622839427 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4306034 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5013938 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 202133183 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 32047845 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 264605257 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 107868981 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 50671063 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 608332366 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 94298 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2196276 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1835605 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31002598 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3774 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 582920651 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 941800609 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 719611293 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 780673 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 492512857 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 90407789 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15406324 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13476597 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 76098764 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 97666868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 83390194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13497619 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14417995 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 576927509 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15532510 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 579347297 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 823601 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 76188435 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 48806754 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 359672 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 662342878 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.874694 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.613558 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 433116455 65.17% 65.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 96939801 14.59% 79.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43307418 6.52% 86.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30869552 4.64% 90.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22882943 3.44% 94.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15965693 2.40% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10866497 1.64% 98.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6415983 0.97% 99.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4228198 0.64% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 433272632 65.42% 65.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 98115954 14.81% 80.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 42214584 6.37% 86.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 29957655 4.52% 91.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22351656 3.37% 94.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 15512359 2.34% 96.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10588779 1.60% 98.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6205955 0.94% 99.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4123304 0.62% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 664592540 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 662342878 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3016734 25.85% 25.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 25376 0.22% 26.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2604 0.02% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4797053 41.10% 67.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3830581 32.82% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2935970 25.32% 25.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 23101 0.20% 25.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2125 0.02% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4825862 41.62% 67.16% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3807172 32.84% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 401312314 67.85% 67.85% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1456904 0.25% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65858 0.01% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 165 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 393154923 67.86% 67.86% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1386126 0.24% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65806 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 67 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 4 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 60568 0.01% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58960 0.01% 68.12% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106521284 18.01% 86.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82042825 13.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 104322059 18.01% 86.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 80359344 13.87% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 591459977 # Type of FU issued -system.cpu0.iq.rate 0.852583 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11672350 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019735 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1858987169 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 684321714 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 570020326 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1026642 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 511393 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 456189 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 602584344 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 547979 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4688231 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 579347297 # Type of FU issued +system.cpu0.iq.rate 0.838212 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11594230 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.020013 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1832414752 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 668808824 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 557946251 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1040551 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 514226 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 463065 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 590385045 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 556471 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4593967 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15870823 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20812 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 719682 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8709865 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15457682 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 19886 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 685587 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8559329 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3916695 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7873559 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3807037 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8317580 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5167977 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 16609605 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 12703167 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 605694561 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1733726 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100241817 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85151630 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12585145 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 227737 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 12390007 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 719682 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2598504 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2279450 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4877954 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 584896168 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104440997 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5696378 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5013938 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 16283569 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 13949536 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 592593872 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1684559 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 97666868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 83390194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13181889 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 225552 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13639351 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 685587 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2515735 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2200394 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4716129 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 572987032 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 102282970 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5487366 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 133820 # number of nop insts executed -system.cpu0.iew.exec_refs 185440040 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108756194 # Number of branches executed -system.cpu0.iew.exec_stores 80999043 # Number of stores executed -system.cpu0.iew.exec_rate 0.843121 # Inst execution rate -system.cpu0.iew.wb_sent 571697028 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 570476515 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 281622326 # num instructions producing a value -system.cpu0.iew.wb_consumers 489116164 # num instructions consuming a value +system.cpu0.iew.exec_nop 133853 # number of nop insts executed +system.cpu0.iew.exec_refs 181615455 # number of memory reference insts executed +system.cpu0.iew.exec_branches 106143494 # Number of branches executed +system.cpu0.iew.exec_stores 79332485 # Number of stores executed +system.cpu0.iew.exec_rate 0.829010 # Inst execution rate +system.cpu0.iew.wb_sent 559590255 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 558409316 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 275573262 # num instructions producing a value +system.cpu0.iew.wb_consumers 478603193 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.822336 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575778 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.807918 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575787 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 78604829 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14570971 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4349296 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 651171717 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.809306 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.808418 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 76231429 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15172838 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4208370 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 649315784 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.795101 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.790427 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 458185820 70.36% 70.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 94765025 14.55% 84.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33137681 5.09% 90.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15077927 2.32% 92.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10931676 1.68% 94.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6537456 1.00% 95.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6054601 0.93% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3871079 0.59% 96.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22610452 3.47% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 458104846 70.55% 70.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 95694647 14.74% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32190614 4.96% 90.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 14675845 2.26% 92.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10626542 1.64% 94.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6339406 0.98% 95.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5863967 0.90% 96.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3778167 0.58% 96.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22041750 3.39% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 651171717 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448537783 # Number of instructions committed -system.cpu0.commit.committedOps 526996927 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 649315784 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 439229242 # Number of instructions committed +system.cpu0.commit.committedOps 516271579 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 160812759 # Number of memory references committed -system.cpu0.commit.loads 84370994 # Number of loads committed -system.cpu0.commit.membars 3712862 # Number of memory barriers committed -system.cpu0.commit.branches 100457713 # Number of branches committed -system.cpu0.commit.fp_insts 437537 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 483805259 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13348009 # Number of function calls committed. +system.cpu0.commit.refs 157040050 # Number of memory references committed +system.cpu0.commit.loads 82209185 # Number of loads committed +system.cpu0.commit.membars 3679399 # Number of memory barriers committed +system.cpu0.commit.branches 98142600 # Number of branches committed +system.cpu0.commit.fp_insts 444854 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 473776942 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13048594 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 364956602 69.25% 69.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1127311 0.21% 69.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 49300 0.01% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 50913 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84370994 16.01% 85.49% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 76441765 14.51% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 358050943 69.35% 69.35% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1081428 0.21% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48877 0.01% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 50281 0.01% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 82209185 15.92% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74830865 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 526996927 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22610452 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1230217301 # The number of ROB reads -system.cpu0.rob.rob_writes 1224645571 # The number of ROB writes -system.cpu0.timesIdled 4130146 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 29134607 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 48521219733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 448537783 # Number of Instructions Simulated -system.cpu0.committedOps 526996927 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.546641 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.546641 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.646562 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.646562 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 689663562 # number of integer regfile reads -system.cpu0.int_regfile_writes 407539482 # number of integer regfile writes -system.cpu0.fp_regfile_reads 822896 # number of floating regfile reads -system.cpu0.fp_regfile_writes 494260 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125263725 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126423537 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1208432146 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14685746 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10442064 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.972968 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 299912904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10442576 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.720203 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 516271579 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22041750 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1215785177 # The number of ROB reads +system.cpu0.rob.rob_writes 1198053925 # The number of ROB writes +system.cpu0.timesIdled 4064231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28827685 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 52470002692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 439229242 # Number of Instructions Simulated +system.cpu0.committedOps 516271579 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.573599 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.573599 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.635486 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.635486 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 676011417 # number of integer regfile reads +system.cpu0.int_regfile_writes 398349827 # number of integer regfile writes +system.cpu0.fp_regfile_reads 844800 # number of floating regfile reads +system.cpu0.fp_regfile_writes 475036 # number of floating regfile writes +system.cpu0.cc_regfile_reads 123341922 # number of cc regfile reads +system.cpu0.cc_regfile_writes 124453917 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1200774516 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15268687 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10441215 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.972989 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 300350847 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10441727 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.764480 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 306.410459 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 205.562509 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.598458 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.401489 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 278.618843 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 233.354146 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.544177 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.455770 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1323031608 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1323031608 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80041652 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78145564 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 158187216 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67282411 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 66174015 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 133456426 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208357 # number of SoftPFReq hits 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demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 144319579 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 291643642 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147532420 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 144513338 # number of overall hits -system.cpu0.dcache.overall_hits::total 292045758 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6276474 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6183597 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12460071 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6322158 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6339058 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 12661216 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 639187 # number of SoftPFReq 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 72513073 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 146117642 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847544 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 831802 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1679346 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 794967 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 767270 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1562237 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2097250 # number of LoadLockedReq accesses(hits+misses) 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overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 318444275 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.073327 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073017 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.085894 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087420 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.086651 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.754164 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.767061 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760552 # miss rate for SoftPFReq accesses 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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 17763.948937 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43520.903484 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44003.766581 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43762.657292 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72272.151908 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 75597.030357 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73944.116862 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14008.858705 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13525.591493 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13771.469294 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22312.500000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 25250 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23571.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30757.840266 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30977.601082 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30867.388351 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29272.700482 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29475.777886 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29373.942548 # average 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0.079509 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.082724 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17538.430448 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17929.520574 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17732.740165 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.894210 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44192.139148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43673.334678 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71524.555272 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76123.351151 # average WriteLineReq miss latency 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MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 145500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 316000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99178693698 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97876740702 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197055434400 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111492939198 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110320915202 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 221813854400 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2819562500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3022126000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841688500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2713847000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3108432498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5822279498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5533409500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6130558498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11663967998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032742 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033133 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032935 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014552 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014695 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014623 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.739237 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752954 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746031 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.769397 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.807021 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787875 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059891 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059967 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 8016148 # number of writebacks +system.cpu0.dcache.writebacks::total 8016148 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3459904 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3385993 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6845897 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5454136 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5045051 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10499187 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3486 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3453 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 6939 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 195002 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 204372 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 399374 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8914040 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8431044 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17345084 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8914040 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8431044 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17345084 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2814678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2809808 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5624486 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1096874 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1034159 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2131033 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 658655 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 593550 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1252205 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 604108 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 626071 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1230179 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121886 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 127690 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 249576 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3911552 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3843967 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7755519 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4570207 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4437517 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9007724 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15990 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17689 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33679 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 14658 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 19039 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30648 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 36728 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67376 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48435084000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49650597000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98085681000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 50577189739 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 47912432297 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 98489622036 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13555749500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11111774000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24667523500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 42652248636 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 47094090510 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89746339146 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1696955500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1893897000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3590852500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 144500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 202500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 347000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99012273739 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97563029297 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 196575303036 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112568023239 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 108674803297 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 221242826536 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2881077500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3350690000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6231767500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2752373000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3455424991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207797991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5633450500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6806114991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12439565491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033522 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032338 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032920 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015228 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013919 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014563 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750935 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.740958 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746172 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.773625 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.801266 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787450 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062038 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060430 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024370 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024609 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024488 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028139 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028451 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028293 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17578.727024 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17374.959781 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17477.425579 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46211.698061 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46292.882603 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46252.185674 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19654.489926 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19869.065429 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19761.758238 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71328.176650 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74729.598277 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73039.330648 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14694.357754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14164.366600 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14433.272472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21312.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 24250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22571.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25448.019516 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25358.764287 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25403.608360 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24645.636130 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24592.323033 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24619.091568 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171256.225705 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175572.300006 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173462.259109 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177468.414857 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168899.831450 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172788.446641 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174247.685477 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172124.505096 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173125.257863 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025075 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023848 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024451 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029133 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027394 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028250 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17208.037296 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17670.458978 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17439.047941 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46110.300489 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46329.850919 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46216.845087 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20580.955887 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18720.872715 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19699.269289 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70603.681189 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75221.645005 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 72953.886504 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13922.480843 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14831.991542 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14387.811729 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24083.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 40500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 31545.454545 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25312.784731 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25380.818643 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25346.505248 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24630.836905 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24490.002697 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24561.457093 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180179.956223 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189422.239810 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185034.220137 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187772.752081 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181491.937129 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184224.055287 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183811.358001 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185311.342600 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184629.029491 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15993913 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921230 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 168728933 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15994425 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.549234 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 23717372500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.340793 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.580437 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.545587 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.454259 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16004570 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921303 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 169009090 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16005082 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.559714 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 23708267500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 282.699542 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 229.221761 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.552148 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.447699 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 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miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 101752782407 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103549068385 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 205301850792 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101752782407 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103549068385 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 205301850792 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101752782407 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103549068385 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 205301850792 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086748 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085934 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086748 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085146 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085934 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086748 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085146 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085934 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12798.691262 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.328688 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12827.195233 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12798.691262 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.328688 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12827.195233 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12798.691262 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.328688 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12827.195233 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 128002334 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87000769 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5591841 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87469952 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 62728816 # Number of BTB hits +system.cpu1.branchPred.lookups 131672686 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89355343 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5781214 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89724326 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 64173033 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.714703 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16690428 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 184044 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.522446 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17121716 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 186515 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1400,91 +1395,94 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 888625 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 888625 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16515 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89516 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 551182 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 337443 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2618.907490 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15834.815336 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 334927 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1259 0.37% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 844 0.25% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 153 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 151 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 337443 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 414261 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23202.362762 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18749.985984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 19280.784036 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 405371 97.85% 97.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6574 1.59% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1705 0.41% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 91 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 347 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 109 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 414261 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 346681338644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.164180 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.727467 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 345667955144 99.71% 99.71% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 547148000 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 197378500 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 124829500 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 46718000 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26902000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 29536000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 34566500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 5689000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 518500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 43000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 346681338644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 89517 84.42% 84.42% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16515 15.58% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 106032 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 888625 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 890074 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 890074 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16464 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90676 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 549449 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 340625 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2662.717064 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 16656.719504 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 337983 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1343 0.39% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 873 0.26% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 159 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 157 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 28 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 31 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::851968-917503 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::917504-983039 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::983040-1.04858e+06 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 340625 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 415755 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23534.974925 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18938.344998 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20176.522890 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 406038 97.66% 97.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7288 1.75% 99.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1678 0.40% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 118 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 407 0.10% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 121 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 66 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 415755 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 351694007776 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.068501 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.668276 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 350661865276 99.71% 99.71% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 565026500 0.16% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 204421500 0.06% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 121176000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 47649500 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 25922000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 25482500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 35190500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6889500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 280500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 36000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 351694007776 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 90676 84.63% 84.63% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16464 15.37% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 107140 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 890074 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 888625 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106032 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 890074 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107140 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106032 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 994657 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107140 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 997214 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 102078491 # DTB read hits -system.cpu1.dtb.read_misses 609526 # DTB read misses -system.cpu1.dtb.write_hits 79752942 # DTB write hits -system.cpu1.dtb.write_misses 279099 # DTB write misses -system.cpu1.dtb.flush_tlb 1097 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 104588302 # DTB read hits +system.cpu1.dtb.read_misses 610979 # DTB read misses +system.cpu1.dtb.write_hits 81672452 # DTB write hits +system.cpu1.dtb.write_misses 279095 # DTB write misses +system.cpu1.dtb.flush_tlb 1101 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21138 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 525 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 54374 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9195 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 20830 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 55425 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 192 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9142 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 57003 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 102688017 # DTB read accesses -system.cpu1.dtb.write_accesses 80032041 # DTB write accesses +system.cpu1.dtb.perms_faults 57336 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 105199281 # DTB read accesses +system.cpu1.dtb.write_accesses 81951547 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 181831433 # DTB hits -system.cpu1.dtb.misses 888625 # DTB misses -system.cpu1.dtb.accesses 182720058 # DTB accesses +system.cpu1.dtb.hits 186260754 # DTB hits +system.cpu1.dtb.misses 890074 # DTB misses +system.cpu1.dtb.accesses 187150828 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1514,381 +1512,388 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 103286 # Table walker walks requested -system.cpu1.itb.walker.walksLong 103286 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2985 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70650 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14185 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 89101 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1880.887981 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12259.575091 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 88607 99.45% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 208 0.23% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 245 0.27% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 23 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 89101 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 87820 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29448.206559 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24574.367788 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23374.084602 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 85760 97.65% 97.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 575 0.65% 98.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1268 1.44% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 74 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 108 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 87820 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 303729046684 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.808269 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -245416179168 -80.80% -80.80% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 549075630852 180.78% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 61607500 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 7072500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 899500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 15500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 303729046684 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 70650 95.95% 95.95% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2985 4.05% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 73635 # Table walker page sizes translated +system.cpu1.itb.walker.walks 107237 # Table walker walks requested +system.cpu1.itb.walker.walksLong 107237 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3106 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 74018 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14783 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 92454 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1914.233024 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12442.896364 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 91334 98.79% 98.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 604 0.65% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 90 0.10% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 135 0.15% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 192 0.21% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 45 0.05% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 20 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 92454 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 91907 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29826.585570 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25014.091101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 23207.372292 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 89740 97.64% 97.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 728 0.79% 98.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1203 1.31% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.10% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 102 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 20 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 91907 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 308743335316 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.811344 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -250411422516 -81.11% -81.11% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 559080989832 181.08% 99.98% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 64275500 0.02% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 7864000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 1253500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 141000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 234000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 308743335316 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 74018 95.97% 95.97% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3106 4.03% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 77124 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 103286 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 103286 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 107237 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 107237 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73635 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73635 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 176921 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 91956391 # ITB inst hits -system.cpu1.itb.inst_misses 103286 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 77124 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 77124 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 184361 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 94835234 # ITB inst hits +system.cpu1.itb.inst_misses 107237 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1097 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1101 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21138 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 525 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40049 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20830 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 41604 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202974 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202082 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 92059677 # ITB inst accesses -system.cpu1.itb.hits 91956391 # DTB hits -system.cpu1.itb.misses 103286 # DTB misses -system.cpu1.itb.accesses 92059677 # DTB accesses -system.cpu1.numCycles 683589124 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 94942471 # ITB inst accesses +system.cpu1.itb.hits 94835234 # DTB hits +system.cpu1.itb.misses 107237 # DTB misses +system.cpu1.itb.accesses 94942471 # DTB accesses +system.cpu1.numCycles 690312922 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 238009169 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 571176057 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 128002334 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 79419244 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 404719127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12774600 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2616585 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 24222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 5589 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5368087 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 160870 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2610 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 91730802 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3443412 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 41301 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 657293286 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.017856 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.272002 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 244529898 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 585856252 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 131672686 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81294749 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 402345645 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13192141 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2778573 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 21795 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 5943 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5312997 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 174263 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 3566 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 94609332 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3554739 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 42315 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 661768476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.036278 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.289766 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 516237120 78.54% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 17632958 2.68% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 17654036 2.69% 83.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13091323 1.99% 85.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27900711 4.24% 90.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8639588 1.31% 91.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9467175 1.44% 92.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8151646 1.24% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 38518729 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 517207044 78.16% 78.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18129888 2.74% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18375332 2.78% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13432056 2.03% 85.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 27838578 4.21% 89.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9027951 1.36% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9770345 1.48% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8415200 1.27% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39572082 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 657293286 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.187250 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.835555 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 193664291 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 342800105 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 102542010 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13254966 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5029491 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18937376 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1377136 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 623890493 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4237673 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5029491 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 201058836 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31048942 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 259190035 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 108261392 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 52701935 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 609359225 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 108791 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2049420 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1849812 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 33430397 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3628 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 583294874 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 940667365 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 720819975 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 791427 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 492359028 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 90935841 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15032233 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13124059 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74465076 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 97949385 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 83816258 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13144575 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14065563 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 578164482 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15125943 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 579632592 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 823862 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 76544478 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 48922532 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 353577 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 657293286 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.881848 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.622601 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 661768476 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.190743 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.848682 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 199426637 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 337927065 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 106132516 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13075533 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5204264 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19655517 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1411698 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 639761275 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4339654 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5204264 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 206862514 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 30693400 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 255298873 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111614723 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 52092053 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 624767105 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 119693 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2051470 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1928200 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 33207471 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3875 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 596912920 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 957883599 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 738584518 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 769692 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 502441681 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 94471239 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14502575 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12526593 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 72768072 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 100816739 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 85870948 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13475308 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14310498 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 593385744 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14541945 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 593302844 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 834025 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 79206193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 50535241 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 362086 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 661768476 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.896541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.637280 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 429426254 65.33% 65.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 96715112 14.71% 80.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42097823 6.40% 86.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 29977053 4.56% 91.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22357761 3.40% 94.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15606240 2.37% 96.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10657458 1.62% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6260997 0.95% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4194588 0.64% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 430990787 65.13% 65.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 95612119 14.45% 79.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43322710 6.55% 86.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31009109 4.69% 90.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 22951412 3.47% 94.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16184580 2.45% 96.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10912216 1.65% 98.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6468210 0.98% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4317333 0.65% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 657293286 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 661768476 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2920465 25.31% 25.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 23164 0.20% 25.51% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2858 0.02% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4710924 40.83% 66.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3880904 33.63% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3013963 25.80% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 25479 0.22% 26.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 3319 0.03% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4708735 40.30% 66.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3932373 33.66% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 393199833 67.84% 67.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1396367 0.24% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66291 0.01% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 69 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 68890 0.01% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 104108183 17.96% 86.06% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 80792947 13.94% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 402293875 67.81% 67.81% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1465613 0.25% 68.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66790 0.01% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 152 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 70080 0.01% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 106673645 17.98% 86.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82732640 13.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 579632592 # Type of FU issued -system.cpu1.iq.rate 0.847925 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11538316 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019906 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1827853747 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 669983955 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 558625373 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1066901 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 527037 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 476493 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 590600685 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 570212 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4591636 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 593302844 # Type of FU issued +system.cpu1.iq.rate 0.859469 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11683870 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019693 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1859837992 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 687326005 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 572108496 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1054067 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 524138 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 469445 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 604424270 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 562442 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4728038 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15509069 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 19434 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 687053 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8553480 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15991835 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20369 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 727913 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8786210 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3778771 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7833875 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3909440 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7480668 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5029491 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16246993 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12738129 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 593422501 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1696916 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 97949385 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 83816258 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12835084 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 232041 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 12419302 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 687053 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2537334 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2208748 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4746082 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 573207937 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 102068127 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5548487 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5204264 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16486033 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12035619 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 608060202 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1765454 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 100816739 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 85870948 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12241352 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 233009 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 11715765 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 727913 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2628157 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2293591 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4921748 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 586639297 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 104576028 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5786024 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 132076 # number of nop insts executed -system.cpu1.iew.exec_refs 181824390 # number of memory reference insts executed -system.cpu1.iew.exec_branches 105934255 # Number of branches executed -system.cpu1.iew.exec_stores 79756263 # Number of stores executed -system.cpu1.iew.exec_rate 0.838527 # Inst execution rate -system.cpu1.iew.wb_sent 560287134 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 559101866 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 276158020 # num instructions producing a value -system.cpu1.iew.wb_consumers 479351020 # num instructions consuming a value +system.cpu1.iew.exec_nop 132513 # number of nop insts executed +system.cpu1.iew.exec_refs 186249978 # number of memory reference insts executed +system.cpu1.iew.exec_branches 108834662 # Number of branches executed +system.cpu1.iew.exec_stores 81673950 # Number of stores executed +system.cpu1.iew.exec_rate 0.849816 # Inst execution rate +system.cpu1.iew.wb_sent 573803675 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 572577941 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 282811002 # num instructions producing a value +system.cpu1.iew.wb_consumers 490863765 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.817892 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.576108 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.829447 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.576150 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 76588811 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14772366 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4233759 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 644213743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.802134 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.802116 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 79254249 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14179859 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4389133 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 648242205 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.815623 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.819454 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 454416895 70.54% 70.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 94019038 14.59% 85.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32034419 4.97% 90.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14900535 2.31% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10532700 1.63% 94.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6339894 0.98% 95.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5911008 0.92% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3813889 0.59% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22245365 3.45% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 456295445 70.39% 70.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 93190134 14.38% 84.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33049230 5.10% 89.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15421896 2.38% 92.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10834364 1.67% 93.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6534810 1.01% 94.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6130401 0.95% 95.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3914098 0.60% 96.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22871827 3.53% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 644213743 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 439656238 # Number of instructions committed -system.cpu1.commit.committedOps 516745942 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 648242205 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 450050330 # Number of instructions committed +system.cpu1.commit.committedOps 528721496 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 157703093 # Number of memory references committed -system.cpu1.commit.loads 82440315 # Number of loads committed -system.cpu1.commit.membars 3590265 # Number of memory barriers committed -system.cpu1.commit.branches 97880986 # Number of branches committed -system.cpu1.commit.fp_insts 458119 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 474489741 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12901444 # Number of function calls committed. +system.cpu1.commit.refs 161909642 # Number of memory references committed +system.cpu1.commit.loads 84824904 # Number of loads committed +system.cpu1.commit.membars 3632926 # Number of memory barriers committed +system.cpu1.commit.branches 100459992 # Number of branches committed +system.cpu1.commit.fp_insts 451058 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 485698001 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13255700 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 357849627 69.25% 69.25% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1084383 0.21% 69.46% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49292 0.01% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 59547 0.01% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82440315 15.95% 85.44% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75262778 14.56% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 365572080 69.14% 69.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1129275 0.21% 69.36% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50278 0.01% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60179 0.01% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84824904 16.04% 85.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77084738 14.58% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 516745942 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22245365 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1211389031 # The number of ROB reads -system.cpu1.rob.rob_writes 1199768965 # The number of ROB writes -system.cpu1.timesIdled 3993228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 26295838 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52679663676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 439656238 # Number of Instructions Simulated -system.cpu1.committedOps 516745942 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.554826 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.554826 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.643159 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.643159 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 676354635 # number of integer regfile reads -system.cpu1.int_regfile_writes 399072274 # number of integer regfile writes -system.cpu1.fp_regfile_reads 856252 # number of floating regfile reads -system.cpu1.fp_regfile_writes 508516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 122966367 # number of cc regfile reads -system.cpu1.cc_regfile_writes 124089822 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1193194921 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14876268 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.cpu1.commit.op_class_0::total 528721496 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22871827 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1229476063 # The number of ROB reads +system.cpu1.rob.rob_writes 1229500763 # The number of ROB writes +system.cpu1.timesIdled 4141402 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 28544446 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48806249668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 450050330 # Number of Instructions Simulated +system.cpu1.committedOps 528721496 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.533857 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.533857 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.651951 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.651951 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 691759463 # number of integer regfile reads +system.cpu1.int_regfile_writes 409243112 # number of integer regfile writes +system.cpu1.fp_regfile_reads 834045 # number of floating regfile reads +system.cpu1.fp_regfile_writes 529652 # number of floating regfile writes +system.cpu1.cc_regfile_reads 125054676 # number of cc regfile reads +system.cpu1.cc_regfile_writes 126221670 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1204731271 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14298109 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1907,11 +1912,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1928,104 +1933,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47821000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25458500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 172500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 40147500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 566083715 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565671459 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147714000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.418427 # Cycle average of tags in use +system.iocache.tags.replacements 115458 # number of replacements +system.iocache.tags.tagsinuse 10.422741 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13100950746000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.907029 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.511398 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369189 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281962 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651152 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13100980146000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.902457 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.520285 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.368904 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.282518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651421 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8810 # number of demand (read+write) misses -system.iocache.demand_misses::total 8850 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8810 # number of overall misses -system.iocache.overall_misses::total 8850 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1682627953 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1687696953 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1698093507 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1703163007 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13827060762 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13827060762 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) 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number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2039,55 +2044,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190990.687060 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190764.886741 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency 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-system.iocache.overall_avg_miss_latency::realview.ide 190990.687060 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190739.881695 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34328 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.778932 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129987.778932 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 192680.529559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 192422.230543 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 192680.529559 # average overall miss latency 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system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8810 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8813 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8850 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8810 # 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of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1245547953 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1242127953 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1245547953 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8531816452 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8531816452 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1257443507 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1260864007 # number of demand (read+write) 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+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 142680.529559 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 142422.230543 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 142680.529559 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 142422.230543 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1323890 # number of replacements -system.l2c.tags.tagsinuse 65259.173207 # Cycle average of tags in use -system.l2c.tags.total_refs 49503955 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1386900 # Sample count of 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# Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.540913 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.177982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004087 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055898 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.150407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995776 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 340 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62670 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.l2c.tags.replacements 1318326 # number of replacements +system.l2c.tags.tagsinuse 65288.938042 # Cycle average of tags in use +system.l2c.tags.total_refs 49534529 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1380698 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 35.876440 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 22398666000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35503.403742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 177.290447 # Average occupied blocks per requestor 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percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.164447 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002726 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.055807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.165192 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996230 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 345 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 344 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5058 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54162 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.956268 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 439519380 # Number of tag accesses -system.l2c.tags.data_accesses 439519380 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 521678 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 191582 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 519241 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 187306 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1419807 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8003050 # number of Writeback hits -system.l2c.Writeback_hits::total 8003050 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 4987 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4929 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9916 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 801026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 796134 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1597160 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 8079380 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7822011 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15901391 # number of ReadCleanReq hits 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# number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2157 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2046 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8797 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17872 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35739 # number of UpgradeReq misses +system.l2c.tags.age_task_id_blocks_1024::2 2801 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5049 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53552 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005264 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 439709140 # Number of tag accesses +system.l2c.tags.data_accesses 439709140 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 516692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 183733 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 528381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 196932 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1425738 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8016148 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8016148 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 16001128 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 16001128 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4984 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4868 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9852 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 820290 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 772489 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1592779 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7906464 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 8007151 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 15913615 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3440520 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3376951 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6817471 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 364532 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 357882 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 722414 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 516692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 183733 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7906464 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4260810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 528381 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 196932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 8007151 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4149440 # number of demand (read+write) hits +system.l2c.demand_hits::total 25749603 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 516692 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 183733 # number of overall hits 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number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 244980 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 263543 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 508523 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2385 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2209 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49787 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 406268 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2157 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2046 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 43083 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 399644 # number of demand (read+write) misses -system.l2c.demand_misses::total 907579 # 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for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006124 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.087810 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004106 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010679 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005477 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.087158 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034071 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006124 # mshr miss rate for overall accesses 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latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 128099.012743 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70750.643465 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70745.928248 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70748.286186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.784708 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784554 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.784632 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.239872 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.240940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.240390 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005492 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005911 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005703 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041580 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.041976 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.041776 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.396578 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.428367 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.412756 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.087412 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004295 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005911 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.086550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033812 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.087412 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005911 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.086550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033812 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 128493.328652 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70758.532423 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70750.324364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70754.478589 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139645.561265 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139628.885690 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 139637.238009 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125322.326553 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130392.772127 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130944.173004 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130663.179511 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145654.928974 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145047.531143 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145340.143907 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136172.442949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136439.783200 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 135102.313801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136172.442949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136439.783200 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135102.313801 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158756.104227 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163072.300006 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142422.758279 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165967.041590 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157314.632689 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161241.289767 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162228.507998 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160097.200775 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149626.989605 # average overall mshr uncacheable latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139289.246572 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139817.768615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 139546.348741 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125283.634906 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 126096.832756 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125707.843481 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131146.367199 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130252.654380 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130701.468233 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.642301 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145253.910518 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145250.009355 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125283.634906 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136311.100602 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126096.832756 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136218.050946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135122.369891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128100.923788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128334.222007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125283.634906 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136311.100602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129083.808688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128410.898380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126096.832756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136218.050946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135122.369891 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167674.077548 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176916.614845 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149596.631348 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176268.761086 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169907.768160 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172674.763273 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171784.651527 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173283.380473 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 158431.511395 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54323 # Transaction distribution -system.membus.trans_dist::ReadResp 463989 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::Writeback 1223443 # Transaction distribution -system.membus.trans_dist::CleanEvict 213592 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36616 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36618 # Transaction distribution -system.membus.trans_dist::ReadExReq 1014298 # Transaction distribution -system.membus.trans_dist::ReadExResp 1014298 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 409666 # Transaction distribution +system.membus.trans_dist::ReadReq 54325 # Transaction distribution +system.membus.trans_dist::ReadResp 460220 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1219305 # Transaction distribution +system.membus.trans_dist::CleanEvict 210974 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36812 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36815 # Transaction distribution +system.membus.trans_dist::ReadExReq 1010906 # Transaction distribution +system.membus.trans_dist::ReadExResp 1010906 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 405895 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4273089 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4402725 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4744779 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6862 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4252499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4382141 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 341858 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4723999 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163341292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 163512986 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7254912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7254912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 170767898 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2786 # Total snoops (count) -system.membus.snoop_fanout::samples 3094626 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162617772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 162789478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7248896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7248896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 170038374 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2884 # Total snoops (count) +system.membus.snoop_fanout::samples 3081006 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3094626 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3081006 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3094626 # Request fanout histogram -system.membus.reqLayer0.occupancy 113794499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3081006 # Request fanout histogram +system.membus.reqLayer0.occupancy 113865000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5590500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5486002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8281023093 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8251811507 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7728395442 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7689965068 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228381503 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227507173 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2756,60 +2765,61 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 53734904 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27297777 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4493 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2110 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2110 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 53750764 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27303829 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4497 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2153 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2021207 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25124422 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 9226509 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 18644458 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45658 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45672 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2103809 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2103809 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15994542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7116774 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1337512 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1230848 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48020569 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31553133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 908522 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2486966 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 82969190 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1024954048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1101984346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3065144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8363688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2138367226 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2094185 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 56528569 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.014634 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.120081 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2028554 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25149235 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9235460 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16001128 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2638618 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45748 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45759 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2096838 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2096838 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16005202 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7123570 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1336841 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1230177 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48052512 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31550783 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 914007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2494586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 83011888 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049706496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1102812070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3078592 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8396320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3163993478 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2090247 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30104268 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027207 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.162685 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 55701347 98.54% 98.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 827222 1.46% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29285228 97.28% 97.28% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 819040 2.72% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 56528569 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 35506762964 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30104268 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51537960463 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1418902 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1443392 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24036893583 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24054534227 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14511308139 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14512097283 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 525798129 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 529644514 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1444244841 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1447978944 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16329 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 8b7b1b258..42f464c4a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811486 # Number of seconds simulated -sim_ticks 51811486345500 # Number of ticks simulated -final_tick 51811486345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.771790 # Number of seconds simulated +sim_ticks 51771790334500 # Number of ticks simulated +final_tick 51771790334500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 353733 # Simulator instruction rate (inst/s) -host_op_rate 415699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22175355428 # Simulator tick rate (ticks/s) -host_mem_usage 671232 # Number of bytes of host memory used -host_seconds 2336.44 # Real time elapsed on the host -sim_insts 826478524 # Number of instructions simulated -sim_ops 971257944 # Number of ops (including micro ops) simulated +host_inst_rate 615158 # Simulator instruction rate (inst/s) +host_op_rate 722932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38549866178 # Simulator tick rate (ticks/s) +host_mem_usage 721636 # Number of bytes of host memory used +host_seconds 1342.98 # Real time elapsed on the host +sim_insts 826146401 # Number of instructions simulated +sim_ops 970885096 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 67136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 69696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2388444 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 32434992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 59968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 68096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2361560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 31996376 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 390912 # Number of bytes read from this memory -system.physmem.bytes_read::total 69837180 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2388444 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2361560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4750004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 60588032 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 15876 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 4704 # Number of bytes written to this memory -system.physmem.bytes_written::total 60608612 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 506800 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56645 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 499953 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6108 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1131626 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 946688 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1985 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 588 # Number of write requests responded to by this memory -system.physmem.num_writes::total 949261 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 46099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 626019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 617554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1347909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 46099 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45580 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1169394 # Write bandwidth from this memory (bytes/s) +system.physmem.bytes_read::cpu0.dtb.walker 64192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 68416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2225432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 31926704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 62336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 66048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2388572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 32205016 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 391616 # Number of bytes read from this memory +system.physmem.bytes_read::total 69398332 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2225432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2388572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4614004 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 60462464 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory +system.physmem.bytes_written::total 60483044 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 55433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 498858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 974 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 503213 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6119 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1124769 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 944726 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory +system.physmem.num_writes::total 947299 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 42985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 616681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 622057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1340466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 42985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1167865 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1169791 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1169394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 46099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 626326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 617645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2517700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1131626 # Number of read requests accepted -system.physmem.writeReqs 949261 # Number of write requests accepted -system.physmem.readBursts 1131626 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 949261 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72380992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43072 # Total number of bytes read from write queue -system.physmem.bytesWritten 60608832 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69837180 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 60608612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 673 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 139894 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 75334 # Per bank write bursts -system.physmem.perBankRdBursts::1 78749 # Per bank write bursts -system.physmem.perBankRdBursts::2 69239 # Per bank write bursts -system.physmem.perBankRdBursts::3 66964 # Per bank write bursts -system.physmem.perBankRdBursts::4 64795 # Per bank write bursts -system.physmem.perBankRdBursts::5 72549 # Per bank write bursts -system.physmem.perBankRdBursts::6 64584 # Per bank write bursts -system.physmem.perBankRdBursts::7 63831 # Per bank write bursts -system.physmem.perBankRdBursts::8 65287 # Per bank write bursts -system.physmem.perBankRdBursts::9 109012 # Per bank write bursts -system.physmem.perBankRdBursts::10 67637 # Per bank write bursts -system.physmem.perBankRdBursts::11 66460 # Per bank write bursts -system.physmem.perBankRdBursts::12 64061 # Per bank write bursts -system.physmem.perBankRdBursts::13 68282 # Per bank write bursts -system.physmem.perBankRdBursts::14 66426 # Per bank write bursts -system.physmem.perBankRdBursts::15 67743 # Per bank write bursts -system.physmem.perBankWrBursts::0 61340 # Per bank write bursts -system.physmem.perBankWrBursts::1 64755 # Per bank write bursts -system.physmem.perBankWrBursts::2 59195 # Per bank write bursts -system.physmem.perBankWrBursts::3 59472 # Per bank write bursts -system.physmem.perBankWrBursts::4 56881 # Per bank write bursts -system.physmem.perBankWrBursts::5 61983 # Per bank write bursts -system.physmem.perBankWrBursts::6 56876 # Per bank write bursts -system.physmem.perBankWrBursts::7 57630 # Per bank write bursts -system.physmem.perBankWrBursts::8 57576 # Per bank write bursts -system.physmem.perBankWrBursts::9 59174 # Per bank write bursts -system.physmem.perBankWrBursts::10 59811 # Per bank write bursts -system.physmem.perBankWrBursts::11 59738 # Per bank write bursts -system.physmem.perBankWrBursts::12 56644 # Per bank write bursts -system.physmem.perBankWrBursts::13 59454 # Per bank write bursts -system.physmem.perBankWrBursts::14 57794 # Per bank write bursts -system.physmem.perBankWrBursts::15 58690 # Per bank write bursts +system.physmem.bw_write::total 1168263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1167865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 42985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 616988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 622148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2508729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1124769 # Number of read requests accepted +system.physmem.writeReqs 947299 # Number of write requests accepted +system.physmem.readBursts 1124769 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 947299 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 71946624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 38592 # Total number of bytes read from write queue +system.physmem.bytesWritten 60482240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69398332 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 60483044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 603 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 292556 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71523 # Per bank write bursts +system.physmem.perBankRdBursts::1 69926 # Per bank write bursts +system.physmem.perBankRdBursts::2 70289 # Per bank write bursts +system.physmem.perBankRdBursts::3 64893 # Per bank write bursts +system.physmem.perBankRdBursts::4 64804 # Per bank write bursts +system.physmem.perBankRdBursts::5 73543 # Per bank write bursts +system.physmem.perBankRdBursts::6 62283 # Per bank write bursts +system.physmem.perBankRdBursts::7 61053 # Per bank write bursts +system.physmem.perBankRdBursts::8 62184 # Per bank write bursts +system.physmem.perBankRdBursts::9 109202 # Per bank write bursts +system.physmem.perBankRdBursts::10 70171 # Per bank write bursts +system.physmem.perBankRdBursts::11 67486 # Per bank write bursts +system.physmem.perBankRdBursts::12 64856 # Per bank write bursts +system.physmem.perBankRdBursts::13 71148 # Per bank write bursts +system.physmem.perBankRdBursts::14 68907 # Per bank write bursts +system.physmem.perBankRdBursts::15 71898 # Per bank write bursts +system.physmem.perBankWrBursts::0 59424 # Per bank write bursts +system.physmem.perBankWrBursts::1 59953 # Per bank write bursts +system.physmem.perBankWrBursts::2 60707 # Per bank write bursts +system.physmem.perBankWrBursts::3 57771 # Per bank write bursts +system.physmem.perBankWrBursts::4 56630 # Per bank write bursts +system.physmem.perBankWrBursts::5 62461 # Per bank write bursts +system.physmem.perBankWrBursts::6 55190 # Per bank write bursts +system.physmem.perBankWrBursts::7 55103 # Per bank write bursts +system.physmem.perBankWrBursts::8 55968 # Per bank write bursts +system.physmem.perBankWrBursts::9 60498 # Per bank write bursts +system.physmem.perBankWrBursts::10 60512 # Per bank write bursts +system.physmem.perBankWrBursts::11 59733 # Per bank write bursts +system.physmem.perBankWrBursts::12 57588 # Per bank write bursts +system.physmem.perBankWrBursts::13 61842 # Per bank write bursts +system.physmem.perBankWrBursts::14 59660 # Per bank write bursts +system.physmem.perBankWrBursts::15 61995 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 24 # Number of times write queue was full causing retry -system.physmem.totGap 51811483663500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 51771787505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1088510 # Read request sizes (log2) +system.physmem.readPktSize::6 1081653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 946688 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1104614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does 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req see +system.physmem.rdQLenPdf::11 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,181 +165,180 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1432 # What write queue length does an incoming req see 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length does an incoming req see -system.physmem.wrQLenPdf::42 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 441668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.107402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.680008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.161317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 174892 39.60% 39.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 107627 24.37% 63.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38708 8.76% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22457 5.08% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15602 3.53% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11601 2.63% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10181 2.31% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8589 1.94% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 52011 11.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 441668 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52978 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.347484 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 294.800530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 52971 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 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queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 441395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 300.022755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.726713 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.159215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 176110 39.90% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107371 24.33% 64.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38199 8.65% 72.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22075 5.00% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15487 3.51% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11537 2.61% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10154 2.30% 86.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8595 1.95% 88.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51867 11.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 441395 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52856 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.268333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 295.103325 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 52849 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52978 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.875590 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.137628 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.848761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 99 0.19% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 70 0.13% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 74 0.14% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 116 0.22% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49442 93.33% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 558 1.05% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 385 0.73% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 568 1.07% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 120 0.23% 97.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 330 0.62% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 204 0.39% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.05% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 95 0.18% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 130 0.25% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 30 0.06% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 454 0.86% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 21 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 141 0.27% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 29 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 8 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 52856 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52856 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.879427 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.143276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.780491 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 105 0.20% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 78 0.15% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 62 0.12% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 98 0.19% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49304 93.28% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 574 1.09% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 365 0.69% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 594 1.12% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 149 0.28% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 324 0.61% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 209 0.40% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.05% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 84 0.16% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 140 0.26% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 28 0.05% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 39 0.07% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 454 0.86% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 24 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 18 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 112 0.21% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 11 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 24 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52978 # Writes before turning the bus around for reads -system.physmem.totQLat 13921987827 # Total ticks spent queuing -system.physmem.totMemAccLat 35127356577 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5654765000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12309.96 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 52856 # Writes before turning the bus around for reads +system.physmem.totQLat 13880638873 # Total ticks spent queuing +system.physmem.totMemAccLat 34958751373 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5620830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12347.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31059.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31097.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.63 # Average write queue length when enqueuing -system.physmem.readRowHits 914287 # Number of row buffer hits during reads -system.physmem.writeRowHits 722010 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.24 # Row buffer hit rate for writes -system.physmem.avgGap 24898749.27 # Average gap between requests -system.physmem.pageHitRate 78.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1737469440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 948024000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4337112000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3098295360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1302776002665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29944103839500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34641074934645 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.598406 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49814086335255 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730099280000 # Time in different power states +system.physmem.avgWrQLen 9.36 # Average write queue length when enqueuing +system.physmem.readRowHits 908414 # Number of row buffer hits during reads +system.physmem.writeRowHits 719391 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.12 # Row buffer hit rate for writes +system.physmem.avgGap 24985563.94 # Average gap between requests +system.physmem.pageHitRate 78.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1674025920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 913407000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4198810200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3027708720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3381481552800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1295576085285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29926602975000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34613474564925 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.577915 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49785017997770 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728773800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 267300073745 # Time in different power states +system.physmem_0.memoryStateTime::ACT 257997880230 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1601540640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 873856500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4484282400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3038348880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384074191680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1289689159770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29955583526250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34639344906120 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.565015 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49833230042430 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730099280000 # Time in different power states +system.physmem_1.actEnergy 1662920280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 907347375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4569645600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3096118080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3381481552800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1293349218120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29928556367250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34613623169505 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.580786 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49788229996275 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728773800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 248153702570 # Time in different power states +system.physmem_1.memoryStateTime::ACT 254784926225 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -393,70 +392,68 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 116564 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 116564 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17888 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84633 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 116551 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.308878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 85.298018 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 116549 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 116551 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 102534 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24964.241130 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21649.871180 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15929.030690 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 101954 99.43% 99.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 9 0.01% 99.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 497 0.48% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 10 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 115431 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 115431 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17925 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83577 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 115422 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.155949 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 52.981983 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 115421 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 115422 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101511 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24872.984209 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21671.671712 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15716.369374 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100971 99.47% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 465 0.46% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 29 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 102534 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -4616128984 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.375220 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1732065704 -37.52% -37.52% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -6348194688 137.52% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -4616128984 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 84634 82.55% 82.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17888 17.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 102522 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 116564 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 101511 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 118356120 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -14.037796 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1779815204 1503.78% 1503.78% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -1661459084 -1403.78% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 118356120 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83577 82.34% 82.34% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17925 17.66% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101502 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115431 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 116564 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 102522 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115431 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101502 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 102522 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 219086 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101502 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 216933 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 77762076 # DTB read hits -system.cpu0.dtb.read_misses 89597 # DTB read misses -system.cpu0.dtb.write_hits 70744341 # DTB write hits -system.cpu0.dtb.write_misses 26967 # DTB write misses -system.cpu0.dtb.flush_tlb 51819 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 77847569 # DTB read hits +system.cpu0.dtb.read_misses 88672 # DTB read misses +system.cpu0.dtb.write_hits 70757652 # DTB write hits +system.cpu0.dtb.write_misses 26759 # DTB write misses +system.cpu0.dtb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 68559 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 18503 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 67979 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3939 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3908 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9342 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 77851673 # DTB read accesses -system.cpu0.dtb.write_accesses 70771308 # DTB write accesses +system.cpu0.dtb.perms_faults 9235 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 77936241 # DTB read accesses +system.cpu0.dtb.write_accesses 70784411 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 148506417 # DTB hits -system.cpu0.dtb.misses 116564 # DTB misses -system.cpu0.dtb.accesses 148622981 # DTB accesses +system.cpu0.dtb.hits 148605221 # DTB hits +system.cpu0.dtb.misses 115431 # DTB misses +system.cpu0.dtb.accesses 148720652 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -486,278 +483,277 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 74612 # Table walker walks requested -system.cpu0.itb.walker.walksLong 74612 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4209 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 65365 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 74612 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 74612 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74612 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69574 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28527.819300 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25311.121928 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18888.333067 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 68887 99.01% 99.01% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 590 0.85% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 39 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 74042 # Table walker walks requested +system.cpu0.itb.walker.walksLong 74042 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4197 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64819 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 74042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 74042 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69016 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28471.542831 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25336.788819 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18532.815053 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68368 99.06% 99.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 559 0.81% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 14 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69574 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 69016 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 65365 93.95% 93.95% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4209 6.05% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 69574 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 64819 93.92% 93.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4197 6.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 69016 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74612 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74612 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74042 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74042 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69574 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69574 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 144186 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 414226266 # ITB inst hits -system.cpu0.itb.inst_misses 74612 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69016 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69016 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 143058 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 414105554 # ITB inst hits +system.cpu0.itb.inst_misses 74042 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51819 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 18784 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 50668 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 18503 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 514 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 50190 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 414300878 # ITB inst accesses -system.cpu0.itb.hits 414226266 # DTB hits -system.cpu0.itb.misses 74612 # DTB misses -system.cpu0.itb.accesses 414300878 # DTB accesses -system.cpu0.numCycles 51812404725 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 414179596 # ITB inst accesses +system.cpu0.itb.hits 414105554 # DTB hits +system.cpu0.itb.misses 74042 # DTB misses +system.cpu0.itb.accesses 414179596 # DTB accesses +system.cpu0.numCycles 51772404432 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15960 # number of quiesce instructions executed -system.cpu0.committedInsts 413973920 # Number of instructions committed -system.cpu0.committedOps 486522682 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 447282441 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 436837 # Number of float alu accesses -system.cpu0.num_func_calls 24924968 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 62713258 # number of instructions that are conditional controls -system.cpu0.num_int_insts 447282441 # number of integer instructions -system.cpu0.num_fp_insts 436837 # number of float instructions -system.cpu0.num_int_register_reads 647714944 # number of times the integer registers were read -system.cpu0.num_int_register_writes 354553253 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 705988 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 367364 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 107220558 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 106909360 # number of times the CC registers were written -system.cpu0.num_mem_refs 148497129 # number of memory refs -system.cpu0.num_load_insts 77758052 # Number of load instructions -system.cpu0.num_store_insts 70739077 # Number of store instructions -system.cpu0.num_idle_cycles 50264604442.745827 # Number of idle cycles -system.cpu0.num_busy_cycles 1547800282.254174 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029873 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970127 # Percentage of idle cycles -system.cpu0.Branches 92346942 # Number of branches fetched +system.cpu0.kern.inst.quiesce 15961 # number of quiesce instructions executed +system.cpu0.committedInsts 413854142 # Number of instructions committed +system.cpu0.committedOps 486394511 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 447175967 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 436796 # Number of float alu accesses +system.cpu0.num_func_calls 24852805 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 62753360 # number of instructions that are conditional controls +system.cpu0.num_int_insts 447175967 # number of integer instructions +system.cpu0.num_fp_insts 436796 # number of float instructions +system.cpu0.num_int_register_reads 647088270 # number of times the integer registers were read +system.cpu0.num_int_register_writes 354432965 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 705701 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 368548 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 107266365 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 106966753 # number of times the CC registers were written +system.cpu0.num_mem_refs 148595341 # number of memory refs +system.cpu0.num_load_insts 77843031 # Number of load instructions +system.cpu0.num_store_insts 70752310 # Number of store instructions +system.cpu0.num_idle_cycles 50229100240.489449 # Number of idle cycles +system.cpu0.num_busy_cycles 1543304191.510550 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029809 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970191 # Percentage of idle cycles +system.cpu0.Branches 92298416 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 337152189 69.26% 69.26% # Class of executed instruction -system.cpu0.op_class::IntMult 1046864 0.22% 69.47% # Class of executed instruction -system.cpu0.op_class::IntDiv 47543 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53325 0.01% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::MemRead 77758052 15.97% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 70739077 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 336911536 69.23% 69.23% # Class of executed instruction +system.cpu0.op_class::IntMult 1057551 0.22% 69.45% # Class of executed instruction +system.cpu0.op_class::IntDiv 48617 0.01% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 54899 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::MemRead 77843031 16.00% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 70752310 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 486797091 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9220536 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 287472122 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9221048 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.175645 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 266.571154 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 245.371643 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 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was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,216 +762,216 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7220092 # number of writebacks -system.cpu0.dcache.writebacks::total 7220092 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 12855 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 9702 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 22557 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 11438 # number of WriteReq MSHR hits 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MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5831863000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2838720500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2985129500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5823850000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5676327000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5979386000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11655713000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031802 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031771 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031787 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013987 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014234 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753260 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.741379 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747479 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789636 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.785046 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787337 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061369 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059813 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060593 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69573227500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69250476000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 138823703500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80018740000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 79382490500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 159401230500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3026868000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3173397500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6200265500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3017135500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3200441000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217576500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6044003500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6373838500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12417842000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031694 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031855 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031774 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014373 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014107 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014241 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749819 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.742596 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746262 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.786659 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.784202 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785425 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061723 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059977 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060855 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023567 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023342 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023454 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027399 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026919 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027159 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16029.617735 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15793.441421 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15911.450213 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32325.256008 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32762.607437 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32539.753872 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19164.128330 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18309.025558 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18751.442008 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58232.368399 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59533.259672 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58881.993489 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13700.364440 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13691.766169 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13696.132545 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023464 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023438 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023451 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027233 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027069 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027151 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15877.639730 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15922.927190 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15900.330526 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32334.670436 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32482.814834 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32407.878251 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18614.640601 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18792.744994 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18701.912223 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58492.480374 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59440.322338 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58967.709653 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13590.714396 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13848.196100 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.849827 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20789.914265 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20612.826334 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20701.815274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20555.184655 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20296.786877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20427.176154 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171177.324003 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174857.305536 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.179609 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167703.698234 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177887.462011 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.525573 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 169422.367479 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176357.056481 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172910.338382 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20668.020359 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20649.827258 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20658.940952 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20374.632292 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20392.618941 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20383.585752 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182561.399276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185362.003505 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.139466 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179058.486647 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189858.278460 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.503961 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180795.797188 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187592.739206 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184221.846396 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13375087 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.782407 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 813613327 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13375599 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 60.828179 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 61699422500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 237.356539 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 274.425868 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.463587 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.535988 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13381945 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.782255 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 813274304 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13382457 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 60.771673 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 61705740500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.029971 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.752284 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541074 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.458501 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 840364535 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 840364535 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 407513323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 406100004 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 813613327 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 407513323 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 406100004 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 813613327 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 407513323 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 406100004 # number of overall hits -system.cpu0.icache.overall_hits::total 813613327 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6712943 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6662661 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13375604 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6712943 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6662661 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13375604 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6712943 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6662661 # number of overall misses -system.cpu0.icache.overall_misses::total 13375604 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91656187500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 90957016000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 182613203500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 91656187500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 90957016000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 182613203500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 91656187500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 90957016000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 182613203500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 414226266 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 412762665 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 826988931 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 414226266 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 412762665 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 826988931 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 414226266 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 412762665 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 826988931 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016206 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016142 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016174 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016206 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016142 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016174 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016206 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016142 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016174 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13653.651982 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13651.755057 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13652.707085 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13653.651982 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13651.755057 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13652.707085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13653.651982 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13651.755057 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13652.707085 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 840039228 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 840039228 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 407397826 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 405876478 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 813274304 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 407397826 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 405876478 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 813274304 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 407397826 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 405876478 # number of overall hits +system.cpu0.icache.overall_hits::total 813274304 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6707728 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6674734 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13382462 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6707728 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6674734 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13382462 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6707728 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6674734 # number of overall misses +system.cpu0.icache.overall_misses::total 13382462 # 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miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13675.090947 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13650.375843 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13625.782307 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13675.090947 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13650.375843 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -984,60 +980,62 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed 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-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780495500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656027000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436522500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780495500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656027000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436522500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016174 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016174 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016206 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016142 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016174 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12652.707085 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12652.707085 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12653.651982 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12651.755057 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12652.707085 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126064.289855 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126025.268549 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126105.165701 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126064.289855 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84690313500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84602860500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 169293174000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84690313500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84602860500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 169293174000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84690313500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84602860500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 169293174000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016189 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016189 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016198 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016179 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016189 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12650.375843 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12650.375843 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12625.782307 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12675.090947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12650.375843 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1068,68 +1066,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 117457 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 117457 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17877 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85465 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 117442 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.102178 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 35.016241 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 117441 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 118026 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 118026 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17902 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85905 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 118017 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.101680 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 34.930834 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 118016 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 117442 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 103357 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25041.496947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21746.242782 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15395.142756 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 102794 99.46% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 506 0.49% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 24 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 103357 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 3996353148 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.606452 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.488536 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1572755204 39.35% 39.35% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 2423597944 60.65% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 3996353148 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 85465 82.70% 82.70% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17877 17.30% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 103342 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117457 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 118017 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 103816 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25027.404254 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21748.751472 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15644.616464 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 103269 99.47% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 471 0.45% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 35 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 103816 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2951550812 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.475602 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.499404 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1547787704 52.44% 52.44% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1403763108 47.56% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2951550812 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85906 82.75% 82.75% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17902 17.25% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 103808 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 118026 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117457 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103342 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 118026 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103808 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103342 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 220799 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103808 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 221834 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 77889145 # DTB read hits -system.cpu1.dtb.read_misses 90593 # DTB read misses -system.cpu1.dtb.write_hits 70493756 # DTB write hits -system.cpu1.dtb.write_misses 26864 # DTB write misses -system.cpu1.dtb.flush_tlb 51813 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 77737807 # DTB read hits +system.cpu1.dtb.read_misses 91072 # DTB read misses +system.cpu1.dtb.write_hits 70427017 # DTB write hits +system.cpu1.dtb.write_misses 26954 # DTB write misses +system.cpu1.dtb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67533 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 19160 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 483 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 67493 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3800 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3798 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9179 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 77979738 # DTB read accesses -system.cpu1.dtb.write_accesses 70520620 # DTB write accesses +system.cpu1.dtb.perms_faults 9286 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 77828879 # DTB read accesses +system.cpu1.dtb.write_accesses 70453971 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148382901 # DTB hits -system.cpu1.dtb.misses 117457 # DTB misses -system.cpu1.dtb.accesses 148500358 # DTB accesses +system.cpu1.dtb.hits 148164824 # DTB hits +system.cpu1.dtb.misses 118026 # DTB misses +system.cpu1.dtb.accesses 148282850 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1159,126 +1158,125 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 75165 # Table walker walks requested -system.cpu1.itb.walker.walksLong 75165 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4147 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 65764 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 75165 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 75165 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75165 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 69911 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28585.308464 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25361.717379 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18567.806598 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 69206 98.99% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 3 0.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 615 0.88% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 20 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 75801 # Table walker walks requested +system.cpu1.itb.walker.walksLong 75801 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4159 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66376 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 75801 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 75801 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75801 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70535 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28466.739916 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25302.677208 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18338.850484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69863 99.05% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 592 0.84% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 11 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 25 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 69911 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1449365704 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1449365704 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1449365704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 65764 94.07% 94.07% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4147 5.93% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 69911 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 70535 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 66376 94.10% 94.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4159 5.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 70535 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75801 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75801 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69911 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69911 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 145076 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 412762665 # ITB inst hits -system.cpu1.itb.inst_misses 75165 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70535 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70535 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 146336 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 412551212 # ITB inst hits +system.cpu1.itb.inst_misses 75801 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51813 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 18879 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 486 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 50171 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 19160 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 483 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 50654 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 412837830 # ITB inst accesses -system.cpu1.itb.hits 412762665 # DTB hits -system.cpu1.itb.misses 75165 # DTB misses -system.cpu1.itb.accesses 412837830 # DTB accesses -system.cpu1.numCycles 51810567966 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 412627013 # ITB inst accesses +system.cpu1.itb.hits 412551212 # DTB hits +system.cpu1.itb.misses 75801 # DTB misses +system.cpu1.itb.accesses 412627013 # DTB accesses +system.cpu1.numCycles 51771176237 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 412504604 # Number of instructions committed -system.cpu1.committedOps 484735262 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 445679810 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 461935 # Number of float alu accesses -system.cpu1.num_func_calls 24743870 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 62553122 # number of instructions that are conditional controls -system.cpu1.num_int_insts 445679810 # number of integer instructions -system.cpu1.num_fp_insts 461935 # number of float instructions -system.cpu1.num_int_register_reads 643867148 # number of times the integer registers were read -system.cpu1.num_int_register_writes 353090786 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 745900 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 389388 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 106633710 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 106335348 # number of times the CC registers were written -system.cpu1.num_mem_refs 148371142 # number of memory refs -system.cpu1.num_load_insts 77883866 # Number of load instructions -system.cpu1.num_store_insts 70487276 # Number of store instructions -system.cpu1.num_idle_cycles 50277800640.138901 # Number of idle cycles -system.cpu1.num_busy_cycles 1532767325.861101 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029584 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970416 # Percentage of idle cycles -system.cpu1.Branches 92048959 # Number of branches fetched +system.cpu1.committedInsts 412292259 # Number of instructions committed +system.cpu1.committedOps 484490585 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 445445369 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 462328 # Number of float alu accesses +system.cpu1.num_func_calls 24787523 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 62474042 # number of instructions that are conditional controls +system.cpu1.num_int_insts 445445369 # number of integer instructions +system.cpu1.num_fp_insts 462328 # number of float instructions +system.cpu1.num_int_register_reads 644065931 # number of times the integer registers were read +system.cpu1.num_int_register_writes 352949314 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 746699 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 388588 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 106522074 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 106212078 # number of times the CC registers were written +system.cpu1.num_mem_refs 148153513 # number of memory refs +system.cpu1.num_load_insts 77732872 # Number of load instructions +system.cpu1.num_store_insts 70420641 # Number of store instructions +system.cpu1.num_idle_cycles 50233711408.448738 # Number of idle cycles +system.cpu1.num_busy_cycles 1537464828.551259 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029697 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970303 # Percentage of idle cycles +system.cpu1.Branches 92021257 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 335465896 69.17% 69.17% # Class of executed instruction -system.cpu1.op_class::IntMult 1068730 0.22% 69.39% # Class of executed instruction -system.cpu1.op_class::IntDiv 49540 0.01% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 59074 0.01% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 77883866 16.06% 85.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 70487276 14.53% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 335453186 69.20% 69.20% # Class of executed instruction +system.cpu1.op_class::IntMult 1057928 0.22% 69.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 48471 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 57500 0.01% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction +system.cpu1.op_class::MemRead 77732872 16.03% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 70420641 14.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 485014384 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40322 # Transaction distribution -system.iobus.trans_dist::ReadResp 40322 # Transaction distribution +system.cpu1.op_class::total 484770600 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40328 # Transaction distribution +system.iobus.trans_dist::ReadResp 40328 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1297,11 +1295,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231014 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353798 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1318,104 +1316,104 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334488 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334488 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 171000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 38601000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 121500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 565848755 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 565515993 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147774000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115483 # number of replacements -system.iocache.tags.tagsinuse 10.447157 # Cycle average of tags in use +system.iocache.tags.replacements 115489 # number of replacements +system.iocache.tags.tagsinuse 10.442885 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115505 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183753622000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511463 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935694 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652947 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183784929000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.514154 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928730 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219635 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433046 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652680 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039866 # Number of tag accesses -system.iocache.tags.data_accesses 1039866 # Number of data accesses +system.iocache.tags.tag_accesses 1039920 # Number of tag accesses +system.iocache.tags.data_accesses 1039920 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8843 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8880 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8843 # number of demand (read+write) misses +system.iocache.demand_misses::total 8883 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1638182519 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1643251519 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8843 # number of overall misses +system.iocache.overall_misses::total 8883 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1656329126 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1661399626 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13826239236 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13826239236 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1638182519 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1643602519 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1638182519 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1643602519 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13864058367 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13864058367 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1656329126 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1661750626 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1656329126 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1661750626 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8843 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8880 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8843 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8883 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8843 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8883 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1429,55 +1427,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185377.675569 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185175.965630 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 187303.983490 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 187094.552477 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129624.233443 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129624.233443 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185152.925425 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185377.675569 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185152.925425 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32900 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.796661 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129978.796661 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 187303.983490 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 187070.879883 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 187303.983490 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 187070.879883 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34559 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3381 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3493 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.730849 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.893788 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8843 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8880 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8837 # 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occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9675.154455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 97.159223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 145.757666 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4633.882908 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 8714.539154 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575999 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001586 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059951 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.147631 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001483 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.070707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.132973 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995012 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 334 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61470 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 334 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2426 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5561 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53526 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004623 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.945297 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 371969368 # Number of tag accesses -system.l2c.tags.data_accesses 371969368 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 206753 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 156932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 209510 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 158543 # number of ReadReq hits -system.l2c.ReadReq_hits::total 731738 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7220092 # number of Writeback hits -system.l2c.Writeback_hits::total 7220092 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 4469 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4434 # number of UpgradeReq hits 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number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 209510 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 158543 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6627078 # number of overall hits -system.l2c.overall_hits::cpu1.data 3703989 # number of overall hits -system.l2c.overall_hits::total 21506100 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1049 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1089 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 937 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1064 # number of ReadReq misses -system.l2c.ReadReq_misses::total 4139 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 16379 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16291 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32670 # number of UpgradeReq misses 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# number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 974 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1032 # number of ReadReq misses +system.l2c.ReadReq_misses::total 4078 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 16194 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16399 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 32593 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 157417 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 154689 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 312106 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 35955 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 35583 # number of ReadCleanReq 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for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005187 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.035065 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035573 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.035318 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.388570 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.396361 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.392476 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004914 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006842 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.004981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.065570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006454 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.065761 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.027072 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004914 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006842 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.004981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.065570 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006454 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.065761 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.027072 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 126667.729279 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70680.375448 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70685.072261 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70682.738625 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120635.414218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120617.257853 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 120626.415385 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121926.451676 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122801.012242 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122530.554911 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122672.201444 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120149.774227 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120106.268356 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120127.742975 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125274.070543 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129184.113866 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121926.616604 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121543.651452 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124607.257204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127070.958647 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121926.285024 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121383.813199 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121555.417056 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158677.324003 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162357.305536 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 134174.114232 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156203.698234 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166387.462011 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161273.525573 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113525.268549 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157427.590735 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113605.165701 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164351.998230 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 142438.240722 # average overall mshr uncacheable latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120643.039166 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120656.223109 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120649.571835 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122090.292885 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122703.908531 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122702.842091 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122703.372915 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120150.186998 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120189.809882 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120170.249757 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121481.969037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121502.712249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121596.923925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125941.176471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128141.253508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122185.509459 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121481.969037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125810.061602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126656.976744 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122001.944174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121502.712249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121596.923925 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170038.721351 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172838.872664 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138964.926782 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167558.189911 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178357.952186 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.192453 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168788.438528 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175577.052123 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149331.560091 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76826 # Transaction distribution -system.membus.trans_dist::ReadResp 378489 # Transaction distribution -system.membus.trans_dist::WriteReq 33708 # Transaction distribution -system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::Writeback 946688 # Transaction distribution -system.membus.trans_dist::CleanEvict 157044 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33236 # Transaction distribution +system.membus.trans_dist::ReadReq 76825 # Transaction distribution +system.membus.trans_dist::ReadResp 374618 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::WritebackDirty 944726 # Transaction distribution +system.membus.trans_dist::CleanEvict 152734 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33164 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33237 # Transaction distribution -system.membus.trans_dist::ReadExReq 790266 # Transaction distribution -system.membus.trans_dist::ReadExResp 790266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 301663 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33165 # Transaction distribution +system.membus.trans_dist::ReadExReq 787274 # Transaction distribution +system.membus.trans_dist::ReadExResp 787274 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 297793 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3314453 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3444143 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340891 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340891 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3785034 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3294284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3423970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 340925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3764895 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123230496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 123400318 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7215296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7215296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 130615614 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3426 # Total snoops (count) -system.membus.snoop_fanout::samples 2449027 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 122665376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 122835190 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 130051190 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3421 # Total snoops (count) +system.membus.snoop_fanout::samples 2435800 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2449027 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2435800 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2449027 # Request fanout histogram -system.membus.reqLayer0.occupancy 107350000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2435800 # Request fanout histogram +system.membus.reqLayer0.occupancy 106891000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5290500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5617000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6222696821 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6213973567 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6001448560 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5964440131 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228378003 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 227489060 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2104,60 +2102,61 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45764335 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23167677 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2649 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 45763569 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 23167437 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2234 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2234 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1182601 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20663192 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8166804 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 15533735 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 41576 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1181074 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 20663813 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8157694 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13380350 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2156668 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 41465 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 41577 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1895383 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1895383 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13375604 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6113005 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1328211 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1221547 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40210956 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27881321 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 758327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1083325 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 69933929 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 856211156 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 974300010 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2541024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3345992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 1836398182 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1592965 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 47672379 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011257 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105498 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 41466 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1895643 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1895643 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13382462 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6108330 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1325248 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1218584 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40231524 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27858913 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 757060 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1077336 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 69924833 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1712992468 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 973558114 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2529304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3311872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2692391758 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1591852 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 25069303 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021336 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144501 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 47135748 98.87% 98.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 536631 1.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 24534434 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 534869 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 47672379 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 30462031500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 25069303 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 43835486500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1592884 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1550881 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20106531000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20116818000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12681402468 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12673228476 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 440699000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 440897000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 665076000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 663352000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index d26a43093..370583b3e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144266 # Number of seconds simulated -sim_ticks 5144265998000 # Number of ticks simulated -final_tick 5144265998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.152315 # Number of seconds simulated +sim_ticks 5152314519000 # Number of ticks simulated +final_tick 5152314519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171354 # Simulator instruction rate (inst/s) -host_op_rate 338701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2161855241 # Simulator tick rate (ticks/s) -host_mem_usage 817304 # Number of bytes of host memory used -host_seconds 2379.56 # Real time elapsed on the host -sim_insts 407746267 # Number of instructions simulated -sim_ops 805959101 # Number of ops (including micro ops) simulated +host_inst_rate 171705 # Simulator instruction rate (inst/s) +host_op_rate 339400 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2173929918 # Simulator tick rate (ticks/s) +host_mem_usage 815744 # Number of bytes of host memory used +host_seconds 2370.05 # Real time elapsed on the host +sim_insts 406948645 # Number of instructions simulated +sim_ops 804394656 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1040896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10728128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1035840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10724032 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11801664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1040896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1040896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9535488 # Number of bytes written to this memory -system.physmem.bytes_written::total 9535488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11792640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9542144 # Number of bytes written to this memory +system.physmem.bytes_written::total 9542144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16264 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167563 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 184401 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148992 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148992 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 184260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149096 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149096 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 202341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2085454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2294140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 202341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 202341 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1853615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1853615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1853615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2081401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2288804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 202341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2085454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4147754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184401 # Number of read requests accepted -system.physmem.writeReqs 148992 # Number of write requests accepted -system.physmem.readBursts 184401 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 148992 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11790400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11264 # Total number of bytes read from write queue -system.physmem.bytesWritten 9534208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11801664 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9535488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 201044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2081401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4140816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184260 # Number of read requests accepted +system.physmem.writeReqs 149096 # Number of write requests accepted +system.physmem.readBursts 184260 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149096 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11779776 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12864 # Total number of bytes read from write queue +system.physmem.bytesWritten 9541120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11792640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9542144 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 201 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48430 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11512 # Per bank write bursts -system.physmem.perBankRdBursts::1 10865 # Per bank write bursts -system.physmem.perBankRdBursts::2 12624 # Per bank write bursts -system.physmem.perBankRdBursts::3 11646 # Per bank write bursts -system.physmem.perBankRdBursts::4 11360 # Per bank write bursts -system.physmem.perBankRdBursts::5 11063 # Per bank write bursts -system.physmem.perBankRdBursts::6 11424 # Per bank write bursts -system.physmem.perBankRdBursts::7 11380 # Per bank write bursts -system.physmem.perBankRdBursts::8 11354 # Per bank write bursts -system.physmem.perBankRdBursts::9 10854 # Per bank write bursts -system.physmem.perBankRdBursts::10 10623 # Per bank write bursts -system.physmem.perBankRdBursts::11 11335 # Per bank write bursts -system.physmem.perBankRdBursts::12 12163 # Per bank write bursts -system.physmem.perBankRdBursts::13 12460 # Per bank write bursts -system.physmem.perBankRdBursts::14 11874 # Per bank write bursts -system.physmem.perBankRdBursts::15 11688 # Per bank write bursts -system.physmem.perBankWrBursts::0 9762 # Per bank write bursts -system.physmem.perBankWrBursts::1 9087 # Per bank write bursts -system.physmem.perBankWrBursts::2 9770 # Per bank write bursts -system.physmem.perBankWrBursts::3 9357 # Per bank write bursts -system.physmem.perBankWrBursts::4 9485 # Per bank write bursts -system.physmem.perBankWrBursts::5 8994 # Per bank write bursts -system.physmem.perBankWrBursts::6 9154 # Per bank write bursts -system.physmem.perBankWrBursts::7 8718 # Per bank write bursts -system.physmem.perBankWrBursts::8 8812 # Per bank write bursts -system.physmem.perBankWrBursts::9 9056 # Per bank write bursts -system.physmem.perBankWrBursts::10 8954 # Per bank write bursts -system.physmem.perBankWrBursts::11 9300 # Per bank write bursts -system.physmem.perBankWrBursts::12 9801 # Per bank write bursts -system.physmem.perBankWrBursts::13 9709 # Per bank write bursts -system.physmem.perBankWrBursts::14 9528 # Per bank write bursts -system.physmem.perBankWrBursts::15 9485 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 58140 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11261 # Per bank write bursts +system.physmem.perBankRdBursts::1 10600 # Per bank write bursts +system.physmem.perBankRdBursts::2 12322 # Per bank write bursts +system.physmem.perBankRdBursts::3 11592 # Per bank write bursts +system.physmem.perBankRdBursts::4 11482 # Per bank write bursts +system.physmem.perBankRdBursts::5 10950 # Per bank write bursts +system.physmem.perBankRdBursts::6 11082 # Per bank write bursts +system.physmem.perBankRdBursts::7 11124 # Per bank write bursts +system.physmem.perBankRdBursts::8 10622 # Per bank write bursts +system.physmem.perBankRdBursts::9 11032 # Per bank write bursts +system.physmem.perBankRdBursts::10 11540 # Per bank write bursts +system.physmem.perBankRdBursts::11 11373 # Per bank write bursts +system.physmem.perBankRdBursts::12 12384 # Per bank write bursts +system.physmem.perBankRdBursts::13 12480 # Per bank write bursts +system.physmem.perBankRdBursts::14 11990 # Per bank write bursts +system.physmem.perBankRdBursts::15 12225 # Per bank write bursts +system.physmem.perBankWrBursts::0 9586 # Per bank write bursts +system.physmem.perBankWrBursts::1 9015 # Per bank write bursts +system.physmem.perBankWrBursts::2 9694 # Per bank write bursts +system.physmem.perBankWrBursts::3 9483 # Per bank write bursts +system.physmem.perBankWrBursts::4 9592 # Per bank write bursts +system.physmem.perBankWrBursts::5 9320 # Per bank write bursts +system.physmem.perBankWrBursts::6 9057 # Per bank write bursts +system.physmem.perBankWrBursts::7 9053 # Per bank write bursts +system.physmem.perBankWrBursts::8 8752 # Per bank write bursts +system.physmem.perBankWrBursts::9 9410 # Per bank write bursts +system.physmem.perBankWrBursts::10 9210 # Per bank write bursts +system.physmem.perBankWrBursts::11 8755 # Per bank write bursts +system.physmem.perBankWrBursts::12 9657 # Per bank write bursts +system.physmem.perBankWrBursts::13 9381 # Per bank write bursts +system.physmem.perBankWrBursts::14 9483 # Per bank write bursts +system.physmem.perBankWrBursts::15 9632 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5144265948500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5152314469500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184401 # Read request sizes (log2) +system.physmem.readPktSize::6 184260 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148992 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 169976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149096 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,112 +156,114 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 73109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.681517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.230147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.360710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28156 38.51% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17755 24.29% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7676 10.50% 73.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4351 5.95% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2926 4.00% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2405 3.29% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1356 1.85% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1112 1.52% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7372 10.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 73109 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.343238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.383377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7268 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73146 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.483225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.242867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.005738 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28143 38.48% 38.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17778 24.30% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7759 10.61% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4281 5.85% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2977 4.07% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2397 3.28% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1373 1.88% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1102 1.51% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7336 10.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73146 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.261872 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.739811 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7285 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7269 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7269 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.494153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.676401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.977803 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6209 85.42% 85.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 177 2.43% 87.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.43% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 190 2.61% 90.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 15 0.21% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.08% 93.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 110 1.51% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 9 0.12% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.29% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 27 0.37% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 236 3.25% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 36 0.50% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.07% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.21% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7269 # Writes before turning the bus around for reads -system.physmem.totQLat 2113024695 # Total ticks spent queuing -system.physmem.totMemAccLat 5567243445 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 921125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11469.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7286 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.461158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.651895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.024155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6243 85.68% 85.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 165 2.26% 87.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 39 0.54% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 177 2.43% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.30% 91.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 151 2.07% 93.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 1.45% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.15% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.33% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 33 0.45% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.10% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 220 3.02% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.05% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 9 0.12% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.40% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.08% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.25% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7286 # Writes before turning the bus around for reads +system.physmem.totQLat 2105191048 # Total ticks spent queuing +system.physmem.totMemAccLat 5556297298 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 920295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11437.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30219.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30187.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s @@ -271,298 +273,298 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.39 # Average write queue length when enqueuing -system.physmem.readRowHits 150283 # Number of row buffer hits during reads -system.physmem.writeRowHits 109804 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 15430035.87 # Average gap between requests -system.physmem.pageHitRate 78.05 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 271774440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 148289625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 716609400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 481638960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133079069070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2969819271000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3440514616095 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.806670 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4940481054222 # Time in different power states -system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing +system.physmem.readRowHits 150243 # Number of row buffer hits during reads +system.physmem.writeRowHits 109749 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.61 # Row buffer hit rate for writes +system.physmem.avgGap 15455892.41 # Average gap between requests +system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 269634960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147122250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 705213600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 484704000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 132970948335 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2974744703250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3445846141035 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.796378 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4948677575724 # Time in different power states +system.physmem_0.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32006683778 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31589843276 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 280929600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 153285000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 720337800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 483699600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 133106515425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2969795195250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3440537926275 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4940433568236 # Time in different power states -system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states +system.physmem_1.actEnergy 283348800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 154605000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 730438800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 481334400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 133265512935 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2974486313250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3445925367825 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811755 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4948236275986 # Time in different power states +system.physmem_1.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32047173014 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32026607764 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86512376 # Number of BP lookups -system.cpu.branchPred.condPredicted 86512376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844809 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79880541 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77944216 # Number of BTB hits +system.cpu.branchPred.lookups 86360408 # Number of BP lookups +system.cpu.branchPred.condPredicted 86360408 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844738 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79711483 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77808056 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.575974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1537356 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178131 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.612104 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1540361 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177639 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465431904 # number of cpu cycles simulated +system.cpu.numCycles 465551291 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27316222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 427457339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86512376 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79481572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433294653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1774328 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 174290 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 61780 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 197089 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 797 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8939505 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 424296 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5201 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 461932056 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826209 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.017418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27284501 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426653476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86360408 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79348417 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433446162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1774418 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 139394 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 62229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198576 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 774 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8943748 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426371 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4516 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 462018901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.822492 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.015475 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297044979 64.30% 64.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2134462 0.46% 64.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72126640 15.61% 80.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1546779 0.33% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2100235 0.45% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2289900 0.50% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1474676 0.32% 81.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1857009 0.40% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81357376 17.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297432046 64.38% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2127313 0.46% 64.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72010980 15.59% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1540927 0.33% 80.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2092821 0.45% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2281981 0.49% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1471602 0.32% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1847080 0.40% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81214151 17.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 461932056 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185875 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.918410 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23107773 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281695317 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147794197 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8447605 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887164 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 835787144 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 887164 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26441875 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229504552 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14337084 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152214834 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 38546547 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 832466923 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458085 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12798467 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 221946 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22321415 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 994552862 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1807469855 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1111168371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 379 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963838514 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30714343 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460142 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463176 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43334873 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17067493 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10022220 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1319734 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1116337 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827242342 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1181786 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 822485271 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 216558 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22465018 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33877646 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 141871 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 461932056 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.780533 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400914 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 462018901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185501 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.916448 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22519839 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281050355 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150243576 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7317922 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887209 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834205750 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 887209 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25305856 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229987183 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14520771 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154096496 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37221386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 830901673 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 454414 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12058066 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 208457 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22294259 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 992600987 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1804085973 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109069164 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 286 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 961883524 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30717461 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460427 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463529 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38187587 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17040256 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10018392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1266986 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1072258 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825691253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1151613 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820808364 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 215045 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22448205 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33824600 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 141893 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462018901 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.776569 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278202681 60.23% 60.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13844974 3.00% 63.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9781174 2.12% 65.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7532969 1.63% 66.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73227075 15.85% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4827596 1.05% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72754467 15.75% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1183000 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578120 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278841075 60.35% 60.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13664119 2.96% 63.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9689206 2.10% 65.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6979280 1.51% 66.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74151695 16.05% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4284933 0.93% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72644295 15.72% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1183606 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 580692 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 461932056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462018901 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2482095 76.42% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 605940 18.66% 95.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160087 4.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1922566 72.06% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 586085 21.97% 94.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159449 5.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284904 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 794458238 96.59% 96.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149904 0.02% 96.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126188 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 113 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18188915 2.21% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9277009 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284230 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 792921370 96.60% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149961 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126332 0.02% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18051625 2.20% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9274757 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 822485271 # Type of FU issued -system.cpu.iq.rate 1.767144 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3248122 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2110366769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 850901074 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818087590 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 508 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 586 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 178 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 825448239 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1862376 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820808364 # Type of FU issued +system.cpu.iq.rate 1.763089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2668100 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2106518335 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 849303097 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816525348 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 438 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823192025 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1863548 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081864 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14686 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14021 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1600056 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3085191 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14446 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1597044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2207186 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2095832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68625 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887164 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205274699 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15795611 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 828424128 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 165882 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17067493 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10022220 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 692366 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 393655 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14549719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14021 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 476392 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506422 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 982814 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 820971747 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17818623 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1389098 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 887209 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 206158213 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15645218 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826842866 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 165190 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17040277 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10018392 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 682629 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 383889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14436572 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 477389 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506444 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 983833 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819298071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17680302 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1386078 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26886211 # number of memory reference insts executed -system.cpu.iew.exec_branches 83147027 # Number of branches executed -system.cpu.iew.exec_stores 9067588 # Number of stores executed -system.cpu.iew.exec_rate 1.763892 # Inst execution rate -system.cpu.iew.wb_sent 820497311 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818087768 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639862073 # num instructions producing a value -system.cpu.iew.wb_consumers 1048693225 # num instructions consuming a value +system.cpu.iew.exec_refs 26745461 # number of memory reference insts executed +system.cpu.iew.exec_branches 82993620 # Number of branches executed +system.cpu.iew.exec_stores 9065159 # Number of stores executed +system.cpu.iew.exec_rate 1.759845 # Inst execution rate +system.cpu.iew.wb_sent 818824421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816525502 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638690631 # num instructions producing a value +system.cpu.iew.wb_consumers 1046712832 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.757696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610152 # average fanout of values written-back +system.cpu.iew.wb_rate 1.753889 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610187 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22343285 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1039914 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 855258 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458562995 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.757576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.649246 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22323770 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1009720 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 855337 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458653605 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.753817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.647498 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 287777749 62.76% 62.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11132608 2.43% 65.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3641047 0.79% 65.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74579710 16.26% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2448796 0.53% 82.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1627078 0.35% 83.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1001834 0.22% 83.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70969693 15.48% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5384480 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 288196518 62.84% 62.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11088839 2.42% 65.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3639702 0.79% 66.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74471288 16.24% 82.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2429938 0.53% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1624365 0.35% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000566 0.22% 83.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70851536 15.45% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5350853 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458562995 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407746267 # Number of instructions committed -system.cpu.commit.committedOps 805959101 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458653605 # Number of insts commited each cycle +system.cpu.commit.committedInsts 406948645 # Number of instructions committed +system.cpu.commit.committedOps 804394656 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22407791 # Number of memory references committed -system.cpu.commit.loads 13985627 # Number of loads committed -system.cpu.commit.membars 468163 # Number of memory barriers committed -system.cpu.commit.branches 82155343 # Number of branches committed +system.cpu.commit.refs 22376433 # Number of memory references committed +system.cpu.commit.loads 13955085 # Number of loads committed +system.cpu.commit.membars 448031 # Number of memory barriers committed +system.cpu.commit.branches 82000673 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734813827 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155420 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171757 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783115943 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144574 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 733377152 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155590 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171815 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 781582591 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144575 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121813 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -589,230 +591,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13983042 1.73% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8422164 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13952498 1.73% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8421348 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 805959101 # Class of committed instruction -system.cpu.commit.bw_lim_events 5384480 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1281402583 # The number of ROB reads -system.cpu.rob.rob_writes 1659991505 # The number of ROB writes -system.cpu.timesIdled 284256 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3499848 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823097505 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407746267 # Number of Instructions Simulated -system.cpu.committedOps 805959101 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.141474 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.141474 # CPI: Total CPI of All Threads -system.cpu.ipc 0.876060 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.876060 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1090398458 # number of integer regfile reads -system.cpu.int_regfile_writes 654801015 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.cc_regfile_reads 415698435 # number of cc regfile reads -system.cpu.cc_regfile_writes 321644299 # number of cc regfile writes -system.cpu.misc_regfile_reads 264872577 # number of misc regfile reads +system.cpu.commit.op_class_0::total 804394656 # Class of committed instruction +system.cpu.commit.bw_lim_events 5350853 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1279942872 # The number of ROB reads +system.cpu.rob.rob_writes 1656820485 # The number of ROB writes +system.cpu.timesIdled 287895 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3532390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9839075158 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 406948645 # Number of Instructions Simulated +system.cpu.committedOps 804394656 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.144005 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.144005 # CPI: Total CPI of All Threads +system.cpu.ipc 0.874122 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.874122 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088092002 # number of integer regfile reads +system.cpu.int_regfile_writes 653524498 # number of integer regfile writes +system.cpu.fp_regfile_reads 154 # number of floating regfile reads +system.cpu.cc_regfile_reads 414883395 # number of cc regfile reads +system.cpu.cc_regfile_writes 320972082 # number of cc regfile writes +system.cpu.misc_regfile_reads 264296844 # number of misc regfile reads system.cpu.misc_regfile_writes 400155 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1656886 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18963252 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657398 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.441580 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656669 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.992170 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18961321 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657181 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.441913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy 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cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925080500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925080500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076546 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076546 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034531 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034531 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858283 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858283 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077185 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077185 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14773.886207 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14773.886207 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66061.978121 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66061.978121 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16922.504763 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16922.504763 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26623.715741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26623.715741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24267.368341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24267.368341 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 162206.626505 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162206.626505 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188473.778994 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188473.778994 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 162797.827909 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 162797.827909 # average overall mshr uncacheable latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077177 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077177 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14776.592265 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14776.592265 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66077.034672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66077.034672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16875.266797 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16875.266797 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26634.959522 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26634.959522 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24265.296467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24265.296467 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.298853 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.298853 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199895.734427 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199895.734427 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.732301 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.732301 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 86946 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.839570 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 92503 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 86961 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.063730 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 199815711500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.839570 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.989973 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.989973 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 70093 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.821930 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 109512 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70108 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.562047 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821930 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988871 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988871 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 449092 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 449092 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92507 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 92507 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92507 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 92507 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92507 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 92507 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 88026 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 88026 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 88026 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 88026 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 88026 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 88026 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1095128000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1095128000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1095128000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1095128000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1095128000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1095128000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180533 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 180533 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180533 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 180533 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180533 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 180533 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.487590 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.487590 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.487590 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.487590 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.487590 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.487590 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12440.960625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12440.960625 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12440.960625 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12440.960625 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 432670 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 432670 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 109535 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 109535 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 109535 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 109535 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 109535 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 109535 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71200 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71200 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71200 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71200 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71200 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71200 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 922231500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 922231500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 922231500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 922231500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 922231500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 922231500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180735 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 180735 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180735 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 180735 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180735 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 180735 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393947 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393947 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393947 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393947 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393947 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393947 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12952.689607 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12952.689607 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12952.689607 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -821,180 +824,183 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22750 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22750 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 88026 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 88026 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 88026 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 88026 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 88026 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 88026 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1007102000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1007102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1007102000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1007102000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.487590 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.487590 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.487590 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.487590 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11440.960625 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11440.960625 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11440.960625 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21274 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21274 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71200 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71200 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71200 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71200 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71200 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71200 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 851031500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 851031500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 851031500 # number of demand (read+write) MSHR miss cycles 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accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11952.689607 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 979952 # number of replacements -system.cpu.icache.tags.tagsinuse 509.399185 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 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references to valid blocks. +system.cpu.icache.tags.warmup_cycle 150383300500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.169987 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id 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number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1046827 # number of overall misses -system.cpu.icache.overall_misses::total 1046827 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15679887484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15679887484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15679887484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15679887484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15679887484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15679887484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8939495 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8939495 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8939495 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8939495 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8939495 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8939495 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117101 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.117101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.117101 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.117101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.117101 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.117101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14978.489745 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14978.489745 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14978.489745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14978.489745 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14978.489745 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 13392 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 457 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.304158 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 9921613 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9921613 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7899726 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7899726 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7899726 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7899726 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7899726 # number of overall hits +system.cpu.icache.overall_hits::total 7899726 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1044015 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1044015 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1044015 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1044015 # number of demand (read+write) misses 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(read+write) accesses +system.cpu.icache.demand_accesses::total 8943741 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8943741 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8943741 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116731 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116731 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116731 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15040.908878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15040.908878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15040.908878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15040.908878 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15272 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 489 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.231084 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 91.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66288 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66288 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66288 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66288 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66288 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66288 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980539 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980539 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980539 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980539 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980539 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980539 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13806283989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13806283989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13806283989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13806283989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13806283989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13806283989 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14080.300721 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14080.300721 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14080.300721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14080.300721 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 977286 # number of writebacks +system.cpu.icache.writebacks::total 977286 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 977872 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 977872 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 977872 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 977872 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 977872 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 977872 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13831418488 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13831418488 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13831418488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13831418488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13831418488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13831418488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109336 # mshr miss rate for ReadReq accesses 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miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14144.405902 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 19284 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.025119 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 17613 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 19298 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 0.912685 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5119738953000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.025119 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376570 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376570 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 13564 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.033276 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24089 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 13580 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.773859 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.033276 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.377080 # Average percentage of cache occupancy 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task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 91534 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 91534 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24087 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24087 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 17620 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 17620 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 17620 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 17620 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 20167 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 20167 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 20167 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 20167 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 20167 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 20167 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 233184000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 233184000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 233184000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 233184000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 233184000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 233184000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37785 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 37785 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24089 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24089 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24089 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24089 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14452 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14452 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14452 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14452 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14452 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14452 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176436500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176436500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176436500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 176436500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176436500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 176436500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38539 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38539 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 37787 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 37787 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.533730 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.533730 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.533702 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.533702 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.533702 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.533702 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11562.651857 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11562.651857 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11562.651857 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11562.651857 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11562.651857 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38541 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38541 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38541 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38541 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374997 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374997 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374977 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.374977 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374977 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.374977 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12208.448658 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12208.448658 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12208.448658 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12208.448658 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12208.448658 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12208.448658 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1003,183 +1009,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3197 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3197 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 20167 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 20167 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 20167 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 20167 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 20167 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 20167 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 213017000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 213017000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 213017000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 213017000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 213017000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 213017000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.533730 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.533730 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.533702 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.533702 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.533702 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.651857 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10562.651857 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10562.651857 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2638 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2638 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14452 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14452 # number of ReadReq MSHR misses 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miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161984500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.374997 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.374997 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.374977 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.374977 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11208.448658 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111670 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64798.131266 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4919632 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175949 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.960557 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111860 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64806.586551 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4895189 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176141 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.791309 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50517.509380 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.940071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139536 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3193.810391 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11075.731889 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.770836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50665.329006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 16.461622 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139358 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3133.882078 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.774487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.773092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048734 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988741 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64279 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 676 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3413 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5955 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54192 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980820 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43682151 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43682151 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1585410 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1585410 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 346 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 346 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155314 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155314 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 964131 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 964131 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 75809 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 15497 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332951 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1424257 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 75809 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 15497 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 964131 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1488265 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2543702 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 75809 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 15497 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 964131 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1488265 # number of overall hits -system.cpu.l2cache.overall_hits::total 2543702 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1462 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1462 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132872 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132872 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16267 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16267 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 62 # number of ReadSharedReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047819 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167706 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.988870 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64281 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 693 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6102 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980850 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43507450 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43507450 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1582877 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1582877 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 976140 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 976140 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155489 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155489 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 961542 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 961542 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64982 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12040 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332604 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1409626 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64982 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12040 # number of demand (read+write) hits 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ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15659734500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2012557000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2012557000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 615000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4444414500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4453627500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8598000 # number of demand (read+write) MSHR miss cycles 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+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90977838000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90977838000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2619015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2619015000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93596853000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93596853000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808628 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808628 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024496 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067764 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000817 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067764 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71457.250342 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71457.250342 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117798.377386 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117798.377386 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124290.764879 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124290.764879 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125900 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125272.347816 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125293.465496 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137403.225806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124290.764879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119381.102101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119819.180638 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149706.611577 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149706.611577 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176972.878548 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176972.878548 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150320.300302 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150320.300302 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818687 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818687 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460694 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016554 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026079 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024736 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068142 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068142 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71525.135870 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71525.135870 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117898.380564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117898.380564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124347.049737 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124347.049737 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124549.223742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124566.539871 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.225613 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.225613 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.238671 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.238671 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.222926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.222926 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5491514 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2726446 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 94920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1211 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1211 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5440647 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2708460 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1238 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 602897 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3061240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13882 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1734407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1095490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2269 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 980539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1478351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3006256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1731980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 976140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288324 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 977872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1455461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2939753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6208049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 41124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 194511 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9383437 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207643157 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1196736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 6311744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 277897109 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 226924 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6316816 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.030269 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.203509 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2931742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6148479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31127 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 166003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9277351 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125047680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207509531 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 939712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5524480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 339021403 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 218907 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3519115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019900 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.161788 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6163711 97.58% 97.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 115005 1.82% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 38100 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3460821 98.34% 98.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 46556 1.32% 99.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 11738 0.33% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6316816 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4646513967 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3519115 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5581131973 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 659789 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 669284 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1472350908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1468639319 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3097364534 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3067775714 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 30265969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 21694467 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 132091893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 106870358 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 222097 # Transaction distribution -system.iobus.trans_dist::ReadResp 222097 # Transaction distribution -system.iobus.trans_dist::WriteReq 57711 # Transaction distribution -system.iobus.trans_dist::WriteResp 57711 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.trans_dist::ReadReq 212021 # Transaction distribution +system.iobus.trans_dist::ReadResp 212021 # Transaction distribution +system.iobus.trans_dist::WriteReq 57726 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1647 # Transaction distribution +system.iobus.trans_dist::MessageResp 1647 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 420172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 400004 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1384,21 +1395,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 464358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 562906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 542788 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 210086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 200002 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1408,67 +1419,67 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 238456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3272852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3921096 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3262802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3986644 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8775000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10458500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 146500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 1029000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 58500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 210087000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 300003000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1174000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 24569000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 241306768 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 241170809 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1085500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 453367000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50170000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.116041 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.140720 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999338704000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116041 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007253 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007253 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999394542000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.140720 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008795 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008795 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1482,14 +1493,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 909 system.iocache.demand_misses::total 909 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses system.iocache.overall_misses::total 909 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144457672 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144457672 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6056832096 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6056832096 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144457672 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144457672 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144457672 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144457672 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150240673 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 150240673 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6073165136 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6073165136 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 150240673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 150240673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 150240673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 150240673 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1506,19 +1517,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158919.331133 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129641.097945 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129641.097945 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158919.331133 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158919.331133 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158919.331133 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165281.268427 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129990.692123 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129990.692123 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 165281.268427 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 165281.268427 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1090 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 52 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 104 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.615385 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.480769 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1532,14 +1543,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99007672 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3720832096 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3720832096 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99007672 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99007672 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99007672 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104790673 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3737165136 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3737165136 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104790673 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104790673 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1548,77 +1559,77 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108919.331133 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79641.097945 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79641.097945 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108919.331133 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 108919.331133 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115281.268427 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79990.692123 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79990.692123 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 602897 # Transaction distribution -system.membus.trans_dist::ReadResp 655826 # Transaction distribution -system.membus.trans_dist::WriteReq 13882 # Transaction distribution -system.membus.trans_dist::WriteResp 13882 # Transaction distribution -system.membus.trans_dist::Writeback 148992 # Transaction distribution -system.membus.trans_dist::CleanEvict 9700 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2190 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1729 # Transaction distribution -system.membus.trans_dist::ReadExReq 132608 # Transaction distribution -system.membus.trans_dist::ReadExResp 132605 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52937 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.trans_dist::ReadReq 573460 # Transaction distribution +system.membus.trans_dist::ReadResp 626303 # Transaction distribution +system.membus.trans_dist::WriteReq 13902 # Transaction distribution +system.membus.trans_dist::WriteResp 13902 # Transaction distribution +system.membus.trans_dist::WritebackDirty 149096 # Transaction distribution +system.membus.trans_dist::CleanEvict 9693 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2236 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1746 # Transaction distribution +system.membus.trans_dist::ReadExReq 132555 # Transaction distribution +system.membus.trans_dist::ReadExResp 132550 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52847 # Transaction distribution +system.membus.trans_dist::MessageReq 1647 # Transaction distribution +system.membus.trans_dist::MessageResp 1647 # Transaction distribution +system.membus.trans_dist::BadAddressError 4 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 464358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769200 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1717730 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1862834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 238456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538397 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18322112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20098965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730488 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484035 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1803876 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460973 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319744 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20009115 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23120585 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1616 # Total snoops (count) -system.membus.snoop_fanout::samples 1012128 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001625 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040282 # Request fanout histogram +system.membus.pkt_size::total 23030743 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1647 # Total snoops (count) +system.membus.snoop_fanout::samples 982714 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001676 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040904 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1010483 99.84% 99.84% # Request fanout histogram -system.membus.snoop_fanout::2 1645 0.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 981067 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 1012128 # Request fanout histogram -system.membus.reqLayer0.occupancy 355014500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 982714 # Request fanout histogram +system.membus.reqLayer0.occupancy 338956500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 388301500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 369067500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3986356 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1012808227 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1013629759 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 5500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2339356 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2201176288 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2140696281 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 86060868 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85836693 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 41cabb250..aa0c99096 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.225369 # Number of seconds simulated -sim_ticks 5225368810000 # Number of ticks simulated -final_tick 5225368810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.221365 # Number of seconds simulated +sim_ticks 5221365015000 # Number of ticks simulated +final_tick 5221365015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187606 # Simulator instruction rate (inst/s) -host_op_rate 364338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6433833901 # Simulator tick rate (ticks/s) -host_mem_usage 1111300 # Number of bytes of host memory used -host_seconds 812.17 # Real time elapsed on the host -sim_insts 152367765 # Number of instructions simulated -sim_ops 295904443 # Number of ops (including micro ops) simulated +host_inst_rate 248453 # Simulator instruction rate (inst/s) +host_op_rate 482434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8587928983 # Simulator tick rate (ticks/s) +host_mem_usage 826144 # Number of bytes of host memory used +host_seconds 607.99 # Real time elapsed on the host +sim_insts 151056354 # Number of instructions simulated +sim_ops 293314765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11604096 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 11604096 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9356928 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 9356928 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 181314 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 181314 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 146202 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 146202 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 2220723 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 2220723 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1790673 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1790673 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 4011396 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 4011396 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 181314 # Number of read requests accepted -system.mem_ctrls.writeReqs 146202 # Number of write requests accepted -system.mem_ctrls.readBursts 181314 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 146202 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 11574784 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 29312 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 9353152 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 11604096 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 9356928 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 458 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 37 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11629312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 11629312 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9426176 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 9426176 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 181708 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 181708 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 147284 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 147284 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 2227255 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 2227255 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1805309 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1805309 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 4032564 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 4032564 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 181708 # Number of read requests accepted +system.mem_ctrls.writeReqs 147284 # Number of write requests accepted +system.mem_ctrls.readBursts 181708 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 147284 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 11602944 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 26368 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 9422144 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 11629312 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 9426176 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 412 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 33 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 11244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 11728 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 11414 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11249 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 11189 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 11530 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 10984 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 10623 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 11116 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 11643 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 12156 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 12345 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 11109 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 10877 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11117 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 10532 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 9114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 9153 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 9190 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 9432 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 9109 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 9160 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 8858 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 8355 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 8936 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 9402 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 9134 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 9662 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 9149 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 9001 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 9507 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8981 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 11315 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 10810 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10914 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 11597 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 11232 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11930 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 10887 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 12498 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 12229 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 11811 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 12012 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 11054 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 10768 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10809 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 10667 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 10064 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 9276 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 8835 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 9280 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9017 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9023 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 9283 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 8385 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 9360 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 9330 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9168 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 9776 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 9055 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 9211 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 9312 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 8846 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5225368708000 # Total gap between requests +system.mem_ctrls.totGap 5221364905500 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 181314 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 181708 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 146202 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 180784 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 72 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 147284 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 181190 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 106 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -135,39 +135,39 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2042 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2789 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 8700 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 9297 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 8795 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 9401 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 9400 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8618 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 9266 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 9253 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 8672 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 8773 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 8544 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8651 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 8275 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 8310 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 8383 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 8185 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 136 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 112 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 98 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 69 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 65 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 30 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2024 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2744 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 8771 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 9315 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 8851 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 9482 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 9472 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 8660 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 9268 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 9345 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 8736 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 8808 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 8668 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 8747 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 8343 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 8394 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 8477 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 8268 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 120 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 118 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 92 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 78 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 67 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 52 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 21 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see @@ -184,349 +184,355 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 59375 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 352.469423 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 208.459416 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 350.191620 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19259 32.44% 32.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 13965 23.52% 55.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6118 10.30% 66.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3675 6.19% 72.45% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2603 4.38% 76.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1985 3.34% 80.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1578 2.66% 82.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1346 2.27% 85.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 8846 14.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 59375 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 8143 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 22.209014 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 312.827272 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-1023 8137 99.93% 99.93% # Reads before turning the bus around for writes +system.mem_ctrls.bytesPerActivate::samples 59927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 350.843927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 206.536657 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 350.281857 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 19886 33.18% 33.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 13813 23.05% 56.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6078 10.14% 66.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3680 6.14% 72.52% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 2560 4.27% 76.79% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2039 3.40% 80.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1649 2.75% 82.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1406 2.35% 85.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 8816 14.71% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 59927 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 8212 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 22.072577 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 311.491456 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-1023 8206 99.93% 99.93% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 8143 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 8143 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.947071 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.618146 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 3.900856 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6047 74.26% 74.26% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 20 0.25% 74.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 162 1.99% 76.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 25 0.31% 76.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 47 0.58% 77.38% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 486 5.97% 83.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 180 2.21% 85.56% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 58 0.71% 86.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 619 7.60% 93.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 107 1.31% 95.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 5 0.06% 95.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 26 0.32% 95.57% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 281 3.45% 99.02% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 5 0.06% 99.16% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.21% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.30% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::33 4 0.05% 99.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.36% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::35 2 0.02% 99.39% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 5 0.06% 99.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::37 7 0.09% 99.53% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::38 4 0.05% 99.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::39 8 0.10% 99.68% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::40 5 0.06% 99.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::41 1 0.01% 99.75% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::42 2 0.02% 99.78% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::44 4 0.05% 99.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::46 3 0.04% 99.95% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::48 1 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 8143 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 1912369249 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5303419249 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 904280000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10573.99 # Average queueing delay per DRAM burst +system.mem_ctrls.rdPerTurnAround::total 8212 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 8212 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.927545 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.596423 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 3.937922 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 6145 74.83% 74.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 16 0.19% 75.02% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 149 1.81% 76.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.24% 77.08% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 39 0.47% 77.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 481 5.86% 83.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 195 2.37% 85.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 59 0.72% 86.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 612 7.45% 93.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 113 1.38% 95.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 6 0.07% 95.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 13 0.16% 95.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 284 3.46% 99.03% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 4 0.05% 99.07% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 6 0.07% 99.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 4 0.05% 99.20% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::32 7 0.09% 99.28% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 5 0.06% 99.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.35% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::35 1 0.01% 99.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::36 6 0.07% 99.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.49% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::38 2 0.02% 99.51% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::39 6 0.07% 99.59% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::40 1 0.01% 99.60% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::41 8 0.10% 99.70% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::42 3 0.04% 99.73% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::43 2 0.02% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::44 6 0.07% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::45 4 0.05% 99.88% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::46 1 0.01% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::48 3 0.04% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::50 1 0.01% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::51 4 0.05% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 8212 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1926712996 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5326012996 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 906480000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10627.44 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29323.99 # Average memory access latency per DRAM burst +system.mem_ctrls.avgMemAccLat 29377.44 # Average memory access latency per DRAM burst system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1.79 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1.79 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.23 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 146726 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 120897 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.13 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 82.71 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 15954544.84 # Average gap between requests -system.mem_ctrls.pageHitRate 81.84 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 218060640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 118981500 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 701688000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 468964080 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 341295633120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 139733284410 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 3012647859750 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 3495184471500 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 668.887692 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 5011696826000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 174486520000 # Time in different power states +system.mem_ctrls.avgWrQLen 25.95 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 146991 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 121598 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 81.08 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 82.58 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 15870795.96 # Average gap between requests +system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 221946480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 121101750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 697686600 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 474096240 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 139619979810 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3010341298500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 3492509834100 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 668.889138 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5007866146000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 174352620000 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 39185363500 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 39146148500 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 230814360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 125940375 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 708981000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 478042560 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 341295633120 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 140499040365 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3011976144000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 3495314595780 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 668.912595 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5010570381500 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 174486520000 # Time in different power states +system.mem_ctrls_1.actEnergy 231101640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 126097125 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 716414400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 479895840 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 341033724720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 139466264490 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3010476136500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3492529634715 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 668.892930 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5008078591499 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 174352620000 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 40311306000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 38927077251 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10450737620 # number of cpu cycles simulated +system.cpu0.numCycles 10442730030 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 133878612 # Number of instructions committed -system.cpu0.committedOps 261396254 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 242945035 # Number of integer alu accesses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.committedInsts 100536790 # Number of instructions committed +system.cpu0.committedOps 194797787 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 182088702 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu0.num_func_calls 2097767 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 24690965 # number of instructions that are conditional controls -system.cpu0.num_int_insts 242945035 # number of integer instructions +system.cpu0.num_func_calls 1786032 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 17861740 # number of instructions that are conditional controls +system.cpu0.num_int_insts 182088702 # number of integer instructions system.cpu0.num_fp_insts 48 # number of float instructions -system.cpu0.num_int_register_reads 449858957 # number of times the integer registers were read -system.cpu0.num_int_register_writes 208812254 # number of times the integer registers were written +system.cpu0.num_int_register_reads 340614933 # number of times the integer registers were read +system.cpu0.num_int_register_writes 155369927 # number of times the integer registers were written system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 139838702 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 101442019 # number of times the CC registers were written -system.cpu0.num_mem_refs 19926036 # number of memory refs -system.cpu0.num_load_insts 12901049 # Number of load instructions -system.cpu0.num_store_insts 7024987 # Number of store instructions -system.cpu0.num_idle_cycles 9874541194.502110 # Number of idle cycles -system.cpu0.num_busy_cycles 576196425.497890 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055135 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944865 # Percentage of idle cycles -system.cpu0.Branches 27504240 # Number of branches fetched -system.cpu0.op_class::No_OpClass 196451 0.08% 0.08% # Class of executed instruction -system.cpu0.op_class::IntAlu 241068901 92.22% 92.30% # Class of executed instruction -system.cpu0.op_class::IntMult 118906 0.05% 92.34% # Class of executed instruction -system.cpu0.op_class::IntDiv 91754 0.04% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatCvt 16 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 92.38% # Class of executed instruction -system.cpu0.op_class::MemRead 12896145 4.93% 97.31% # Class of executed instruction -system.cpu0.op_class::MemWrite 7024987 2.69% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 104545094 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 75102328 # number of times the CC registers were written +system.cpu0.num_mem_refs 18441277 # number of memory refs +system.cpu0.num_load_insts 11598406 # Number of load instructions +system.cpu0.num_store_insts 6842871 # Number of store instructions +system.cpu0.num_idle_cycles 9945203438.030096 # Number of idle cycles +system.cpu0.num_busy_cycles 497526591.969905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047643 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952357 # Percentage of idle cycles +system.cpu0.Branches 20259437 # Number of branches fetched +system.cpu0.op_class::No_OpClass 186593 0.10% 0.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 175972173 90.34% 90.43% # Class of executed instruction +system.cpu0.op_class::IntMult 117562 0.06% 90.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 85263 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatCvt 16 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.54% # Class of executed instruction +system.cpu0.op_class::MemRead 11594262 5.95% 96.49% # Class of executed instruction +system.cpu0.op_class::MemWrite 6842871 3.51% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 261397160 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.op_class::total 194798740 # Class of executed instruction system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10450371427 # number of cpu cycles simulated +system.cpu1.numCycles 10442397548 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18489153 # Number of instructions committed -system.cpu1.committedOps 34508189 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 33584697 # Number of integer alu accesses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 50519564 # Number of instructions committed +system.cpu1.committedOps 98516978 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 91922994 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu1.num_func_calls 723193 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2490900 # number of instructions that are conditional controls -system.cpu1.num_int_insts 33584697 # number of integer instructions +system.cpu1.num_func_calls 994306 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9151225 # number of instructions that are conditional controls +system.cpu1.num_int_insts 91922994 # number of integer instructions system.cpu1.num_fp_insts 48 # number of float instructions -system.cpu1.num_int_register_reads 67969193 # number of times the integer registers were read -system.cpu1.num_int_register_writes 27166606 # number of times the integer registers were written +system.cpu1.num_int_register_reads 171998955 # number of times the integer registers were read +system.cpu1.num_int_register_writes 78483891 # number of times the integer registers were written system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 18719213 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 11481778 # number of times the CC registers were written -system.cpu1.num_mem_refs 7779481 # number of memory refs -system.cpu1.num_load_insts 4611241 # Number of load instructions -system.cpu1.num_store_insts 3168240 # Number of store instructions -system.cpu1.num_idle_cycles 10364265637.965616 # Number of idle cycles -system.cpu1.num_busy_cycles 86105789.034384 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008239 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991761 # Percentage of idle cycles -system.cpu1.Branches 3500131 # Number of branches fetched -system.cpu1.op_class::No_OpClass 130271 0.38% 0.38% # Class of executed instruction -system.cpu1.op_class::IntAlu 26481859 76.74% 77.12% # Class of executed instruction -system.cpu1.op_class::IntMult 73611 0.21% 77.33% # Class of executed instruction -system.cpu1.op_class::IntDiv 48640 0.14% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatCvt 16 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 77.47% # Class of executed instruction -system.cpu1.op_class::MemRead 4606243 13.35% 90.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3168240 9.18% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 52229827 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 37031962 # number of times the CC registers were written +system.cpu1.num_mem_refs 8648347 # number of memory refs +system.cpu1.num_load_insts 5505950 # Number of load instructions +system.cpu1.num_store_insts 3142397 # Number of store instructions +system.cpu1.num_idle_cycles 10281439289.330288 # Number of idle cycles +system.cpu1.num_busy_cycles 160958258.669712 # Number of busy cycles +system.cpu1.not_idle_fraction 0.015414 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.984586 # Percentage of idle cycles +system.cpu1.Branches 10509152 # Number of branches fetched +system.cpu1.op_class::No_OpClass 118845 0.12% 0.12% # Class of executed instruction +system.cpu1.op_class::IntAlu 89646727 91.00% 91.12% # Class of executed instruction +system.cpu1.op_class::IntMult 68401 0.07% 91.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 39477 0.04% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatCvt 16 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 91.23% # Class of executed instruction +system.cpu1.op_class::MemRead 5501755 5.58% 96.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 3142397 3.19% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 34508880 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 907238 # Transaction distribution -system.iobus.trans_dist::ReadResp 907238 # Transaction distribution -system.iobus.trans_dist::WriteReq 37562 # Transaction distribution -system.iobus.trans_dist::WriteResp 37562 # Transaction distribution -system.iobus.trans_dist::MessageReq 1829 # Transaction distribution -system.iobus.trans_dist::MessageResp 1829 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3426 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes) +system.cpu1.op_class::total 98517618 # Class of executed instruction +system.iobus.trans_dist::ReadReq 883857 # Transaction distribution +system.iobus.trans_dist::ReadResp 883857 # Transaction distribution +system.iobus.trans_dist::WriteReq 36766 # Transaction distribution +system.iobus.trans_dist::WriteResp 36766 # Transaction distribution +system.iobus.trans_dist::MessageReq 1833 # Transaction distribution +system.iobus.trans_dist::MessageResp 1833 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 712 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 74 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 943400 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 178 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 21370 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 831224 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 811270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 178 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1807714 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4706 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 32826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 674 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 32826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 5996 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 68 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4602 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 82118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1893258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3372 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4059 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1754122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 31650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 31738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12896 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 70 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 87372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1844912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3472 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6836 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 356 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 37 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 471700 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 89 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2844 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 10685 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1662442 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7234 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1622534 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 356 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2157234 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2653 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 202 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16413 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1348 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 16413 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 2998 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9201 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 49372 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2213458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2100077 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 326 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1352 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15869 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 52465 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2159378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9139000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9039000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 158000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 159000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 936500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 945000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 21911000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 21127500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 471701000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 458718000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1769984 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1770984 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 33004000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 31828500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20528000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20526000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -534,24 +540,24 @@ system.iobus.reqLayer16.occupancy 9500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 420342217 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 410368779 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 7349150 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 7668139 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 1592000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2491416 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2481464 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 2005792963 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1948163500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 55581972 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 60411500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -561,48 +567,48 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 11126779 # delay histogram for all message -system.ruby.delayHist::mean 0.431812 # delay histogram for all message -system.ruby.delayHist::stdev 1.814704 # delay histogram for all message -system.ruby.delayHist | 10527775 94.62% 94.62% | 6617 0.06% 94.68% | 590092 5.30% 99.98% | 473 0.00% 99.98% | 1712 0.02% 100.00% | 18 0.00% 100.00% | 91 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 11126779 # delay histogram for all message +system.ruby.delayHist::samples 11180744 # delay histogram for all message +system.ruby.delayHist::mean 0.431770 # delay histogram for all message +system.ruby.delayHist::stdev 1.809571 # delay histogram for all message +system.ruby.delayHist | 10577839 94.61% 94.61% | 2056 0.02% 94.63% | 600268 5.37% 99.99% | 190 0.00% 100.00% | 314 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 11180744 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 200336264 -system.ruby.outstanding_req_hist::mean 1.000143 -system.ruby.outstanding_req_hist::gmean 1.000099 -system.ruby.outstanding_req_hist::stdev 0.011958 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 200307614 99.99% 99.99% | 28650 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 200336264 +system.ruby.outstanding_req_hist::samples 197955014 +system.ruby.outstanding_req_hist::mean 1.000129 +system.ruby.outstanding_req_hist::gmean 1.000089 +system.ruby.outstanding_req_hist::stdev 0.011356 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929484 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 197955014 system.ruby.latency_hist::bucket_size 128 system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 200336263 -system.ruby.latency_hist::mean 1.335134 -system.ruby.latency_hist::gmean 1.041246 -system.ruby.latency_hist::stdev 5.048100 -system.ruby.latency_hist | 200300902 99.98% 99.98% | 26494 0.01% 100.00% | 2841 0.00% 100.00% | 3411 0.00% 100.00% | 1684 0.00% 100.00% | 871 0.00% 100.00% | 17 0.00% 100.00% | 21 0.00% 100.00% | 19 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.latency_hist::total 200336263 +system.ruby.latency_hist::samples 197955013 +system.ruby.latency_hist::mean 1.340863 +system.ruby.latency_hist::gmean 1.042158 +system.ruby.latency_hist::stdev 5.086284 +system.ruby.latency_hist | 197919444 99.98% 99.98% | 26717 0.01% 100.00% | 2924 0.00% 100.00% | 3327 0.00% 100.00% | 1642 0.00% 100.00% | 886 0.00% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00% +system.ruby.latency_hist::total 197955013 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 197654640 +system.ruby.hit_latency_hist::samples 195243076 system.ruby.hit_latency_hist::mean 1 system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 197654640 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 197654640 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243076 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 195243076 system.ruby.miss_latency_hist::bucket_size 128 system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 2681623 -system.ruby.miss_latency_hist::mean 26.036867 -system.ruby.miss_latency_hist::gmean 20.481431 -system.ruby.miss_latency_hist::stdev 35.851511 -system.ruby.miss_latency_hist | 2646262 98.68% 98.68% | 26494 0.99% 99.67% | 2841 0.11% 99.78% | 3411 0.13% 99.90% | 1684 0.06% 99.97% | 871 0.03% 100.00% | 17 0.00% 100.00% | 21 0.00% 100.00% | 19 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.miss_latency_hist::total 2681623 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 17463573 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 1589391 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 19052964 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 149306597 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 484179 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 149790776 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2711937 +system.ruby.miss_latency_hist::mean 25.880928 +system.ruby.miss_latency_hist::gmean 20.371838 +system.ruby.miss_latency_hist::stdev 35.746268 +system.ruby.miss_latency_hist | 2676368 98.69% 98.69% | 26717 0.99% 99.67% | 2924 0.11% 99.78% | 3327 0.12% 99.90% | 1642 0.06% 99.96% | 886 0.03% 100.00% | 9 0.00% 100.00% | 33 0.00% 100.00% | 23 0.00% 100.00% | 8 0.00% 100.00% +system.ruby.miss_latency_hist::total 2711937 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386658 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208703 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595361 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 114457594 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 551051 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 115008645 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -612,13 +618,13 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 10 # cycles for which number of transistions == max transitions -system.ruby.l1_cntrl1.L1Dcache.demand_hits 7462230 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 305828 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 7768058 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 23422240 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 302225 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 23724465 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 14 # cycles for which number of transistions == max transitions +system.ruby.l1_cntrl1.L1Dcache.demand_hits 7947911 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 682965 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 8630876 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 56450913 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 269218 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 56720131 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -628,605 +634,606 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.l2_cntrl0.L2cache.demand_hits 2423981 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 257642 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2681623 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 14 # cycles for which number of transistions == max transitions +system.ruby.l2_cntrl0.L2cache.demand_hits 2479106 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 232831 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2711937 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 0.069248 -system.ruby.network.routers0.msg_count.Control::0 2073570 -system.ruby.network.routers0.msg_count.Request_Control::2 69104 -system.ruby.network.routers0.msg_count.Response_Data::1 2116140 -system.ruby.network.routers0.msg_count.Response_Control::1 1556339 -system.ruby.network.routers0.msg_count.Response_Control::2 1546945 -system.ruby.network.routers0.msg_count.Writeback_Data::0 396332 -system.ruby.network.routers0.msg_count.Writeback_Data::1 202 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1087870 -system.ruby.network.routers0.msg_bytes.Control::0 16588560 -system.ruby.network.routers0.msg_bytes.Request_Control::2 552832 -system.ruby.network.routers0.msg_bytes.Response_Data::1 152362080 -system.ruby.network.routers0.msg_bytes.Response_Control::1 12450712 -system.ruby.network.routers0.msg_bytes.Response_Control::2 12375560 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 28535904 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 14544 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8702960 -system.ruby.network.routers1.percent_links_utilized 0.020197 -system.ruby.network.routers1.msg_count.Control::0 608053 -system.ruby.network.routers1.msg_count.Request_Control::2 63486 -system.ruby.network.routers1.msg_count.Response_Data::1 646525 -system.ruby.network.routers1.msg_count.Response_Control::1 287577 -system.ruby.network.routers1.msg_count.Response_Control::2 279257 -system.ruby.network.routers1.msg_count.Writeback_Data::0 145650 -system.ruby.network.routers1.msg_count.Writeback_Data::1 434 -system.ruby.network.routers1.msg_count.Writeback_Control::0 71246 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+system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1449872 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 680984 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 197230752 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 14236592 +system.ruby.network.routers3.throttle0.link_utilization 0.005611 +system.ruby.network.routers3.throttle0.msg_count.Control::0 181234 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 103288 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 13460 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47555 +system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1449872 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7436736 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 107680 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380440 +system.ruby.network.routers3.throttle1.link_utilization 0.008643 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 182053 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 119833 system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 13080456 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 954008 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 13107816 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 958664 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000259 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 819 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58968 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers4.throttle1.link_utilization 0.000227 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers4.throttle1.link_utilization 0.000228 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47555 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380440 system.ruby.network.routers5.throttle0.link_utilization 0 system.ruby.network.routers5.throttle1.link_utilization 0 -system.ruby.network.routers6.throttle0.link_utilization 0.096045 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 69104 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 2053248 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 1526583 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 552832 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 147833856 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 12212664 -system.ruby.network.routers6.throttle1.link_utilization 0.026791 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 63486 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 586006 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 262162 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 507888 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 42192432 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 2097296 -system.ruby.network.routers6.throttle2.link_utilization 0.060891 -system.ruby.network.routers6.throttle2.msg_count.Control::0 2681623 -system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 227487 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 129144 -system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1826202 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 541982 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 636 -system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1159116 -system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21452984 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 16379064 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1033152 -system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14609616 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 39022704 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 45792 -system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 9272928 -system.ruby.network.routers6.throttle3.link_utilization 0.005550 -system.ruby.network.routers6.throttle3.msg_count.Control::0 180859 -system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 101908 -system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 14542 -system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47550 -system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1446872 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7337376 -system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 116336 -system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers6.throttle0.link_utilization 0.081037 +system.ruby.network.routers6.throttle0.msg_count.Request_Control::2 45501 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::1 1747073 +system.ruby.network.routers6.throttle0.msg_count.Response_Control::1 1155797 +system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::2 364008 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::1 125789256 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::1 9246376 +system.ruby.network.routers6.throttle1.link_utilization 0.043775 +system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 41487 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::1 940552 +system.ruby.network.routers6.throttle1.msg_count.Response_Control::1 636259 +system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 331896 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::1 67719744 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::1 5090072 +system.ruby.network.routers6.throttle2.link_utilization 0.061593 +system.ruby.network.routers6.throttle2.msg_count.Control::0 2711937 +system.ruby.network.routers6.throttle2.msg_count.Response_Data::1 208720 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::1 128788 +system.ruby.network.routers6.throttle2.msg_count.Response_Control::2 1822334 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::0 572032 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Data::1 494 +system.ruby.network.routers6.throttle2.msg_count.Writeback_Control::0 1169770 +system.ruby.network.routers6.throttle2.msg_bytes.Control::0 21695496 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Data::1 15027840 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::1 1030304 +system.ruby.network.routers6.throttle2.msg_bytes.Response_Control::2 14578672 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::0 41186304 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Data::1 35568 +system.ruby.network.routers6.throttle2.msg_bytes.Writeback_Control::0 9358160 +system.ruby.network.routers6.throttle3.link_utilization 0.005611 +system.ruby.network.routers6.throttle3.msg_count.Control::0 181234 +system.ruby.network.routers6.throttle3.msg_count.Response_Data::1 103288 +system.ruby.network.routers6.throttle3.msg_count.Response_Control::1 13460 +system.ruby.network.routers6.throttle3.msg_count.Writeback_Control::0 47555 +system.ruby.network.routers6.throttle3.msg_bytes.Control::0 1449872 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Data::1 7436736 +system.ruby.network.routers6.throttle3.msg_bytes.Response_Control::1 107680 +system.ruby.network.routers6.throttle3.msg_bytes.Writeback_Control::0 380440 system.ruby.network.routers6.throttle4.link_utilization 0.000259 -system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 814 +system.ruby.network.routers6.throttle4.msg_count.Response_Data::1 819 system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers6.throttle4.msg_bytes.Response_Data::1 58968 system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers6.throttle5.link_utilization 0 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6208923 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.706330 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.282369 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5663471 91.22% 91.22% | 1771 0.03% 91.24% | 541397 8.72% 99.96% | 469 0.01% 99.97% | 1705 0.03% 100.00% | 18 0.00% 100.00% | 91 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6208923 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6276073 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.731694 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.309515 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5702895 90.87% 90.87% | 563 0.01% 90.88% | 572045 9.11% 99.99% | 184 0.00% 99.99% | 309 0.00% 100.00% | 12 0.00% 100.00% | 62 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6276073 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4785266 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.087581 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.822703 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4729884 98.84% 98.84% | 1830 0.04% 98.88% | 2212 0.05% 98.93% | 2634 0.06% 98.98% | 48164 1.01% 99.99% | 531 0.01% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4785266 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4817683 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.048845 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.619508 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4787335 99.37% 99.37% | 621 0.01% 99.38% | 650 0.01% 99.40% | 843 0.02% 99.41% | 27983 0.58% 99.99% | 240 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4817683 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 132590 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000272 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.023301 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 132572 99.99% 99.99% | 0 0.00% 99.99% | 18 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 132590 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 86988 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000184 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.019179 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 86980 99.99% 99.99% | 0 0.00% 99.99% | 8 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 86988 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 128 system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15790582 -system.ruby.LD.latency_hist::mean 2.812687 -system.ruby.LD.latency_hist::gmean 1.304256 -system.ruby.LD.latency_hist::stdev 8.986997 -system.ruby.LD.latency_hist | 15775646 99.91% 99.91% | 12869 0.08% 99.99% | 830 0.01% 99.99% | 776 0.00% 100.00% | 352 0.00% 100.00% | 97 0.00% 100.00% | 3 0.00% 100.00% | 7 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 15790582 +system.ruby.LD.latency_hist::samples 15432046 +system.ruby.LD.latency_hist::mean 2.853578 +system.ruby.LD.latency_hist::gmean 1.313269 +system.ruby.LD.latency_hist::stdev 9.014347 +system.ruby.LD.latency_hist | 15417213 99.90% 99.90% | 12849 0.08% 99.99% | 809 0.01% 99.99% | 750 0.00% 100.00% | 322 0.00% 100.00% | 89 0.00% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.latency_hist::total 15432046 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 14360870 +system.ruby.LD.hit_latency_hist::samples 13998284 system.ruby.LD.hit_latency_hist::mean 1 system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 14360870 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 14360870 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998284 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13998284 system.ruby.LD.miss_latency_hist::bucket_size 128 system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1429712 -system.ruby.LD.miss_latency_hist::mean 21.020380 -system.ruby.LD.miss_latency_hist::gmean 18.799074 -system.ruby.LD.miss_latency_hist::stdev 22.967453 -system.ruby.LD.miss_latency_hist | 1414776 98.96% 98.96% | 12869 0.90% 99.86% | 830 0.06% 99.91% | 776 0.05% 99.97% | 352 0.02% 99.99% | 97 0.01% 100.00% | 3 0.00% 100.00% | 7 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1429712 +system.ruby.LD.miss_latency_hist::samples 1433762 +system.ruby.LD.miss_latency_hist::mean 20.950658 +system.ruby.LD.miss_latency_hist::gmean 18.787895 +system.ruby.LD.miss_latency_hist::stdev 22.661921 +system.ruby.LD.miss_latency_hist | 1418929 98.97% 98.97% | 12849 0.90% 99.86% | 809 0.06% 99.92% | 750 0.05% 99.97% | 322 0.02% 99.99% | 89 0.01% 100.00% | 3 0.00% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1433762 system.ruby.ST.latency_hist::bucket_size 128 system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 9817325 -system.ruby.ST.latency_hist::mean 3.175435 -system.ruby.ST.latency_hist::gmean 1.140318 -system.ruby.ST.latency_hist::stdev 17.634571 -system.ruby.ST.latency_hist | 9803433 99.86% 99.86% | 8125 0.08% 99.94% | 1485 0.02% 99.96% | 2325 0.02% 99.98% | 1191 0.01% 99.99% | 723 0.01% 100.00% | 13 0.00% 100.00% | 12 0.00% 100.00% | 15 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.ST.latency_hist::total 9817325 +system.ruby.ST.latency_hist::samples 9612989 +system.ruby.ST.latency_hist::mean 3.237181 +system.ruby.ST.latency_hist::gmean 1.143928 +system.ruby.ST.latency_hist::stdev 17.959095 +system.ruby.ST.latency_hist | 9598428 99.85% 99.85% | 8674 0.09% 99.94% | 1607 0.02% 99.96% | 2294 0.02% 99.98% | 1185 0.01% 99.99% | 751 0.01% 100.00% | 6 0.00% 100.00% | 22 0.00% 100.00% | 16 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist::total 9612989 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9465664 +system.ruby.ST.hit_latency_hist::samples 9259406 system.ruby.ST.hit_latency_hist::mean 1 system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9465664 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9465664 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259406 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9259406 system.ruby.ST.miss_latency_hist::bucket_size 128 system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 351661 -system.ruby.ST.miss_latency_hist::mean 61.731653 -system.ruby.ST.miss_latency_hist::gmean 39.083293 -system.ruby.ST.miss_latency_hist::stdev 71.591745 -system.ruby.ST.miss_latency_hist | 337769 96.05% 96.05% | 8125 2.31% 98.36% | 1485 0.42% 98.78% | 2325 0.66% 99.44% | 1191 0.34% 99.78% | 723 0.21% 99.99% | 13 0.00% 99.99% | 12 0.00% 99.99% | 15 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 351661 +system.ruby.ST.miss_latency_hist::samples 353583 +system.ruby.ST.miss_latency_hist::mean 61.823054 +system.ruby.ST.miss_latency_hist::gmean 38.699181 +system.ruby.ST.miss_latency_hist::stdev 72.148162 +system.ruby.ST.miss_latency_hist | 339022 95.88% 95.88% | 8674 2.45% 98.34% | 1607 0.45% 98.79% | 2294 0.65% 99.44% | 1185 0.34% 99.77% | 751 0.21% 99.99% | 6 0.00% 99.99% | 22 0.01% 99.99% | 16 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 353583 system.ruby.IFETCH.latency_hist::bucket_size 128 system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 173515241 -system.ruby.IFETCH.latency_hist::mean 1.084205 -system.ruby.IFETCH.latency_hist::gmean 1.013120 -system.ruby.IFETCH.latency_hist::stdev 1.878946 -system.ruby.IFETCH.latency_hist | 173509156 100.00% 100.00% | 5109 0.00% 100.00% | 498 0.00% 100.00% | 299 0.00% 100.00% | 130 0.00% 100.00% | 45 0.00% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 173515241 +system.ruby.IFETCH.latency_hist::samples 171728776 +system.ruby.IFETCH.latency_hist::mean 1.087723 +system.ruby.IFETCH.latency_hist::gmean 1.013813 +system.ruby.IFETCH.latency_hist::stdev 1.876064 +system.ruby.IFETCH.latency_hist | 171723049 100.00% 100.00% | 4816 0.00% 100.00% | 477 0.00% 100.00% | 266 0.00% 100.00% | 120 0.00% 100.00% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 171728776 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 172728837 +system.ruby.IFETCH.hit_latency_hist::samples 170908507 system.ruby.IFETCH.hit_latency_hist::mean 1 system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 172728837 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 172728837 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908507 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 170908507 system.ruby.IFETCH.miss_latency_hist::bucket_size 128 system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 786404 -system.ruby.IFETCH.miss_latency_hist::mean 19.579326 -system.ruby.IFETCH.miss_latency_hist::gmean 17.745067 -system.ruby.IFETCH.miss_latency_hist::stdev 20.864873 -system.ruby.IFETCH.miss_latency_hist | 780319 99.23% 99.23% | 5109 0.65% 99.88% | 498 0.06% 99.94% | 299 0.04% 99.98% | 130 0.02% 99.99% | 45 0.01% 100.00% | 1 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 786404 +system.ruby.IFETCH.miss_latency_hist::samples 820269 +system.ruby.IFETCH.miss_latency_hist::mean 19.365461 +system.ruby.IFETCH.miss_latency_hist::gmean 17.675024 +system.ruby.IFETCH.miss_latency_hist::stdev 20.029392 +system.ruby.IFETCH.miss_latency_hist | 814542 99.30% 99.30% | 4816 0.59% 99.89% | 477 0.06% 99.95% | 266 0.03% 99.98% | 120 0.01% 99.99% | 39 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 820269 system.ruby.RMW_Read.latency_hist::bucket_size 128 system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 523939 -system.ruby.RMW_Read.latency_hist::mean 4.129191 -system.ruby.RMW_Read.latency_hist::gmean 1.527796 -system.ruby.RMW_Read.latency_hist::stdev 10.162632 -system.ruby.RMW_Read.latency_hist | 523754 99.96% 99.96% | 145 0.03% 99.99% | 18 0.00% 100.00% | 9 0.00% 100.00% | 8 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 523939 +system.ruby.RMW_Read.latency_hist::samples 500824 +system.ruby.RMW_Read.latency_hist::mean 4.015684 +system.ruby.RMW_Read.latency_hist::gmean 1.504004 +system.ruby.RMW_Read.latency_hist::stdev 10.245462 +system.ruby.RMW_Read.latency_hist | 500634 99.96% 99.96% | 144 0.03% 99.99% | 19 0.00% 99.99% | 11 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 500824 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 452465 +system.ruby.RMW_Read.hit_latency_hist::samples 434823 system.ruby.RMW_Read.hit_latency_hist::mean 1 system.ruby.RMW_Read.hit_latency_hist::gmean 1 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 452465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 452465 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 434823 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 434823 system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 71474 -system.ruby.RMW_Read.miss_latency_hist::mean 23.938481 -system.ruby.RMW_Read.miss_latency_hist::gmean 22.350533 -system.ruby.RMW_Read.miss_latency_hist::stdev 17.398088 -system.ruby.RMW_Read.miss_latency_hist | 71289 99.74% 99.74% | 145 0.20% 99.94% | 18 0.03% 99.97% | 9 0.01% 99.98% | 8 0.01% 99.99% | 4 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 71474 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.latency_hist::samples 344588 -system.ruby.Locked_RMW_Read.latency_hist::mean 3.637196 -system.ruby.Locked_RMW_Read.latency_hist::gmean 1.457387 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.622051 -system.ruby.Locked_RMW_Read.latency_hist | 344325 99.92% 99.92% | 246 0.07% 100.00% | 10 0.00% 100.00% | 2 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 344588 +system.ruby.RMW_Read.miss_latency_hist::samples 66001 +system.ruby.RMW_Read.miss_latency_hist::mean 23.883396 +system.ruby.RMW_Read.miss_latency_hist::gmean 22.130353 +system.ruby.RMW_Read.miss_latency_hist::stdev 18.490127 +system.ruby.RMW_Read.miss_latency_hist | 65811 99.71% 99.71% | 144 0.22% 99.93% | 19 0.03% 99.96% | 11 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 66001 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.latency_hist::samples 340189 +system.ruby.Locked_RMW_Read.latency_hist::mean 3.322441 +system.ruby.Locked_RMW_Read.latency_hist::gmean 1.405056 +system.ruby.Locked_RMW_Read.latency_hist::stdev 8.375867 +system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 90 0.03% 99.92% | 233 0.07% 99.99% | 1 0.00% 99.99% | 4 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 340189 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 302216 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 302216 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 302216 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 128 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 42372 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.446852 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 21.392577 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 14.183059 -system.ruby.Locked_RMW_Read.miss_latency_hist | 42109 99.38% 99.38% | 246 0.58% 99.96% | 10 0.02% 99.98% | 2 0.00% 99.99% | 3 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 42372 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 301867 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38322 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 21.616591 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 20.468877 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.672180 +system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 90 0.23% 99.33% | 233 0.61% 99.93% | 1 0.00% 99.94% | 4 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38322 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 344588 +system.ruby.Locked_RMW_Write.latency_hist::samples 340189 system.ruby.Locked_RMW_Write.latency_hist::mean 1 system.ruby.Locked_RMW_Write.latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 344588 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 344588 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 340189 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 344588 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 340189 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 1 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 344588 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 344588 -system.ruby.Directory_Controller.Fetch 180859 0.00% 0.00% -system.ruby.Directory_Controller.Data 101908 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 181314 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 146202 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 340189 +system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00% +system.ruby.Directory_Controller.Data 103288 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 147284 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 819 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 14542 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 180859 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 455 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 44294 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 455 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 44294 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 99107 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_READ 359 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 2442 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 14542 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 180859 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 99107 0.00% 0.00% -system.ruby.Directory_Controller.M_DRD.Data 359 0.00% 0.00% -system.ruby.Directory_Controller.M_DRDI.Memory_Ack 359 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 2442 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2442 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.ReadRequest::total 814 +system.ruby.Directory_Controller.CleanReplacement 13460 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 181234 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 474 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 43996 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 474 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 43996 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 100203 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_READ 345 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 2740 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 13460 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 181234 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 100203 0.00% 0.00% +system.ruby.Directory_Controller.M_DRD.Data 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DRDI.Memory_Ack 345 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 2740 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 2740 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.ReadRequest::total 819 system.ruby.DMA_Controller.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.WriteRequest::total 46736 -system.ruby.DMA_Controller.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.Data::total 814 +system.ruby.DMA_Controller.Data | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.Data::total 819 system.ruby.DMA_Controller.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.Ack::total 46736 -system.ruby.DMA_Controller.READY.ReadRequest | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.READY.ReadRequest::total 814 +system.ruby.DMA_Controller.READY.ReadRequest | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.READY.ReadRequest::total 819 system.ruby.DMA_Controller.READY.WriteRequest | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.READY.WriteRequest::total 46736 -system.ruby.DMA_Controller.BUSY_RD.Data | 814 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.DMA_Controller.BUSY_RD.Data::total 814 +system.ruby.DMA_Controller.BUSY_RD.Data | 819 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.DMA_Controller.BUSY_RD.Data::total 819 system.ruby.DMA_Controller.BUSY_WR.Ack | 46736 100.00% 100.00% | 0 0.00% 100.00% system.ruby.DMA_Controller.BUSY_WR.Ack::total 46736 -system.ruby.L1Cache_Controller.Load | 11499254 72.82% 72.82% | 4291328 27.18% 100.00% -system.ruby.L1Cache_Controller.Load::total 15790582 -system.ruby.L1Cache_Controller.Ifetch | 149790779 86.33% 86.33% | 23724467 13.67% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 173515246 -system.ruby.L1Cache_Controller.Store | 7553710 68.48% 68.48% | 3476730 31.52% 100.00% -system.ruby.L1Cache_Controller.Store::total 11030440 -system.ruby.L1Cache_Controller.Inv | 29958 53.68% 53.68% | 25849 46.32% 100.00% -system.ruby.L1Cache_Controller.Inv::total 55807 -system.ruby.L1Cache_Controller.L1_Replacement | 2028024 78.37% 78.37% | 559829 21.63% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2587853 -system.ruby.L1Cache_Controller.Fwd_GETX | 15400 51.07% 51.07% | 14755 48.93% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 30155 -system.ruby.L1Cache_Controller.Fwd_GETS | 23742 50.92% 50.92% | 22882 49.08% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 46624 +system.ruby.L1Cache_Controller.Load | 10196157 66.07% 66.07% | 5235889 33.93% 100.00% +system.ruby.L1Cache_Controller.Load::total 15432046 +system.ruby.L1Cache_Controller.Ifetch | 115008649 66.97% 66.97% | 56720132 33.03% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 171728781 +system.ruby.L1Cache_Controller.Store | 7399204 68.55% 68.55% | 3394987 31.45% 100.00% +system.ruby.L1Cache_Controller.Store::total 10794191 +system.ruby.L1Cache_Controller.Inv | 18502 52.28% 52.28% | 16889 47.72% 100.00% +system.ruby.L1Cache_Controller.Inv::total 35391 +system.ruby.L1Cache_Controller.L1_Replacement | 1730094 65.23% 65.23% | 922339 34.77% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2652433 +system.ruby.L1Cache_Controller.Fwd_GETX | 12336 51.16% 51.16% | 11775 48.84% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 24111 +system.ruby.L1Cache_Controller.Fwd_GETS | 14659 53.34% 53.34% | 12823 46.66% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 27482 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 1737 59.71% 59.71% | 1172 40.29% 100.00% -system.ruby.L1Cache_Controller.Data::total 2909 -system.ruby.L1Cache_Controller.Data_Exclusive | 1207088 91.86% 91.86% | 106979 8.14% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1314067 -system.ruby.L1Cache_Controller.DataS_fromL1 | 22882 49.07% 49.07% | 23746 50.93% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 46628 -system.ruby.L1Cache_Controller.Data_all_Acks | 821541 64.40% 64.40% | 454109 35.60% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1275650 -system.ruby.L1Cache_Controller.Ack | 20322 47.96% 47.96% | 22047 52.04% 100.00% -system.ruby.L1Cache_Controller.Ack::total 42369 -system.ruby.L1Cache_Controller.Ack_all | 22059 48.72% 48.72% | 23219 51.28% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 45278 -system.ruby.L1Cache_Controller.WB_Ack | 1484202 87.25% 87.25% | 216896 12.75% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1701098 -system.ruby.L1Cache_Controller.NP.Load | 1255942 89.89% 89.89% | 141182 10.11% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1397124 -system.ruby.L1Cache_Controller.NP.Ifetch | 483731 61.58% 61.58% | 301770 38.42% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 785501 -system.ruby.L1Cache_Controller.NP.Store | 289373 71.05% 71.05% | 117901 28.95% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 407274 -system.ruby.L1Cache_Controller.NP.Inv | 6783 68.15% 68.15% | 3170 31.85% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 9953 -system.ruby.L1Cache_Controller.I.Load | 16474 50.55% 50.55% | 16114 49.45% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 32588 -system.ruby.L1Cache_Controller.I.Ifetch | 448 49.61% 49.61% | 455 50.39% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 903 -system.ruby.L1Cache_Controller.I.Store | 7275 45.88% 45.88% | 8582 54.12% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 15857 -system.ruby.L1Cache_Controller.I.L1_Replacement | 14373 54.06% 54.06% | 12212 45.94% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 26585 -system.ruby.L1Cache_Controller.S.Load | 942765 61.54% 61.54% | 589150 38.46% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1531915 -system.ruby.L1Cache_Controller.S.Ifetch | 149306597 86.44% 86.44% | 23422240 13.56% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 172728837 -system.ruby.L1Cache_Controller.S.Store | 20327 47.97% 47.97% | 22049 52.03% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 42376 -system.ruby.L1Cache_Controller.S.Inv | 22933 51.00% 51.00% | 22033 49.00% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 44966 -system.ruby.L1Cache_Controller.S.L1_Replacement | 529449 61.55% 61.55% | 330721 38.45% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 860170 -system.ruby.L1Cache_Controller.E.Load | 2977799 80.56% 80.56% | 718721 19.44% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3696520 -system.ruby.L1Cache_Controller.E.Store | 117327 77.49% 77.49% | 34087 22.51% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 151414 -system.ruby.L1Cache_Controller.E.Inv | 35 14.29% 14.29% | 210 85.71% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 245 -system.ruby.L1Cache_Controller.E.L1_Replacement | 1087870 93.85% 93.85% | 71246 6.15% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1159116 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 218 60.56% 60.56% | 142 39.44% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 360 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1426 54.02% 54.02% | 1214 45.98% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2640 -system.ruby.L1Cache_Controller.M.Load | 6306274 69.05% 69.05% | 2826161 30.95% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 9132435 -system.ruby.L1Cache_Controller.M.Store | 7119408 68.37% 68.37% | 3294111 31.63% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10413519 -system.ruby.L1Cache_Controller.M.Inv | 202 31.76% 31.76% | 434 68.24% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 636 -system.ruby.L1Cache_Controller.M.L1_Replacement | 396332 73.13% 73.13% | 145650 26.87% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 541982 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 15182 50.95% 50.95% | 14613 49.05% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 29795 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 22316 50.74% 50.74% | 21668 49.26% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 43984 +system.ruby.L1Cache_Controller.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% +system.ruby.L1Cache_Controller.Data::total 1630 +system.ruby.L1Cache_Controller.Data_Exclusive | 840504 62.87% 62.87% | 496438 37.13% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1336942 +system.ruby.L1Cache_Controller.DataS_fromL1 | 12823 46.65% 46.65% | 14663 53.35% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 27486 +system.ruby.L1Cache_Controller.Data_all_Acks | 893218 67.59% 67.59% | 428349 32.41% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1321567 +system.ruby.L1Cache_Controller.Ack | 12681 52.16% 52.16% | 11631 47.84% 100.00% +system.ruby.L1Cache_Controller.Ack::total 24312 +system.ruby.L1Cache_Controller.Ack_all | 13209 50.92% 50.92% | 12733 49.08% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 25942 +system.ruby.L1Cache_Controller.WB_Ack | 1129907 64.87% 64.87% | 611895 35.13% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1741802 +system.ruby.L1Cache_Controller.NP.Load | 881473 62.40% 62.40% | 531116 37.60% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1412589 +system.ruby.L1Cache_Controller.NP.Ifetch | 550888 67.18% 67.18% | 269077 32.82% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 819965 +system.ruby.L1Cache_Controller.NP.Store | 298756 70.81% 70.81% | 123170 29.19% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 421926 +system.ruby.L1Cache_Controller.NP.Inv | 5771 62.78% 62.78% | 3422 37.22% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 9193 +system.ruby.L1Cache_Controller.I.Load | 10081 47.61% 47.61% | 11092 52.39% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 21173 +system.ruby.L1Cache_Controller.I.Ifetch | 163 53.62% 53.62% | 141 46.38% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 304 +system.ruby.L1Cache_Controller.I.Store | 5712 48.96% 48.96% | 5955 51.04% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11667 +system.ruby.L1Cache_Controller.I.L1_Replacement | 9111 53.32% 53.32% | 7975 46.68% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 17086 +system.ruby.L1Cache_Controller.S.Load | 850617 63.10% 63.10% | 497429 36.90% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1348046 +system.ruby.L1Cache_Controller.S.Ifetch | 114457594 66.97% 66.97% | 56450913 33.03% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 170908507 +system.ruby.L1Cache_Controller.S.Store | 12681 52.16% 52.16% | 11632 47.84% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 24313 +system.ruby.L1Cache_Controller.S.Inv | 12466 48.73% 48.73% | 13117 51.27% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 25583 +system.ruby.L1Cache_Controller.S.L1_Replacement | 591076 66.15% 66.15% | 302469 33.85% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 893545 +system.ruby.L1Cache_Controller.E.Load | 2398204 64.14% 64.14% | 1340570 35.86% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3738774 +system.ruby.L1Cache_Controller.E.Store | 120081 73.14% 73.14% | 44106 26.86% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 164187 +system.ruby.L1Cache_Controller.E.Inv | 72 60.00% 60.00% | 48 40.00% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 120 +system.ruby.L1Cache_Controller.E.L1_Replacement | 718896 61.46% 61.46% | 450874 38.54% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1169770 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 233 64.01% 64.01% | 131 35.99% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 364 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1000 46.06% 46.06% | 1171 53.94% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2171 +system.ruby.L1Cache_Controller.M.Load | 6055782 67.95% 67.95% | 2855682 32.05% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8911464 +system.ruby.L1Cache_Controller.M.Store | 6961974 68.44% 68.44% | 3210124 31.56% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10172098 +system.ruby.L1Cache_Controller.M.Inv | 193 39.07% 39.07% | 301 60.93% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 494 +system.ruby.L1Cache_Controller.M.L1_Replacement | 411011 71.85% 71.85% | 161021 28.15% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 572032 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 12103 50.97% 50.97% | 11644 49.03% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23747 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 13659 53.96% 53.96% | 11652 46.04% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 25311 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 1207088 91.86% 91.86% | 106979 8.14% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1314067 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 22882 49.07% 49.07% | 23746 50.93% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 46628 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 526625 61.56% 61.56% | 328796 38.44% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 855421 -system.ruby.L1Cache_Controller.IM.Data | 1737 59.71% 59.71% | 1172 40.29% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 2909 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 294916 70.18% 70.18% | 125313 29.82% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 420229 -system.ruby.L1Cache_Controller.SM.Inv | 5 71.43% 71.43% | 2 28.57% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 7 -system.ruby.L1Cache_Controller.SM.Ack | 20322 47.96% 47.96% | 22047 52.04% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 42369 -system.ruby.L1Cache_Controller.SM.Ack_all | 22059 48.72% 48.72% | 23219 51.28% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 45278 -system.ruby.L1Cache_Controller.M_I.Ifetch | 3 60.00% 60.00% | 2 40.00% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 840504 62.87% 62.87% | 496438 37.13% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1336942 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 12823 46.65% 46.65% | 14663 53.35% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 27486 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 589278 66.24% 66.24% | 300325 33.76% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 889603 +system.ruby.L1Cache_Controller.IM.Data | 528 32.39% 32.39% | 1102 67.61% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1630 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 303940 70.36% 70.36% | 128024 29.64% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431964 +system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.Inv::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 12681 52.16% 52.16% | 11631 47.84% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 24312 +system.ruby.L1Cache_Controller.SM.Ack_all | 13209 50.92% 50.92% | 12733 49.08% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 25942 +system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00% system.ruby.L1Cache_Controller.M_I.Ifetch::total 5 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1484202 87.25% 87.25% | 216896 12.75% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1701098 -system.ruby.L2Cache_Controller.L1_GET_INSTR 786404 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1430091 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 423139 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 42377 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1701098 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 98966 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 14683 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 180859 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 116450 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 44624 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2640 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 2261 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 7632 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 46628 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1779574 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 5602 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15956 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 33107 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 131796 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 770425 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 69021 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 3068 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 42369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 213 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7168 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 19 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1280960 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 258119 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 98446 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7182 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 2554 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1129907 64.87% 64.87% | 611895 35.13% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1741802 +system.ruby.L2Cache_Controller.L1_GET_INSTR 820269 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1434154 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 433597 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 24313 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1741802 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 100151 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 13512 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 181234 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 116748 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 25809 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2171 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1865 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 7090 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 27486 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1794848 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 6170 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15428 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32321 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 133485 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 804811 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 69338 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1923 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 24312 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 291 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6674 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 5 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1304621 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 274075 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 99609 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6704 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 2851 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 46624 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 30155 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1701098 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 307 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 333 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 241 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 116450 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 2554 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 495 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 53 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 241 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 141 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 192 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2043 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 7168 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 218 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 219 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 33107 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 15956 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 131796 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 233 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 45437 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 146 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1734137 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 43981 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2640 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 46621 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 27482 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 24111 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1741802 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 251 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 134 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 229 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 116748 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 2851 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 442 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 38 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 229 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 52 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 82 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1570 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6674 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 295 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 296 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 5 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32321 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15428 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 133485 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 235 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 26235 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 157 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1768613 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 25310 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2170 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 27480 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4fb206696..d9f455151 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.141985 # Number of seconds simulated -sim_ticks 5141984685500 # Number of ticks simulated -final_tick 5141984685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.140310 # Number of seconds simulated +sim_ticks 5140310078000 # Number of ticks simulated +final_tick 5140310078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264541 # Simulator instruction rate (inst/s) -host_op_rate 525842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5597553756 # Simulator tick rate (ticks/s) -host_mem_usage 1010248 # Number of bytes of host memory used -host_seconds 918.61 # Real time elapsed on the host -sim_insts 243010444 # Number of instructions simulated -sim_ops 483045307 # Number of ops (including micro ops) simulated +host_inst_rate 269101 # Simulator instruction rate (inst/s) +host_op_rate 534933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5691143534 # Simulator tick rate (ticks/s) +host_mem_usage 1043812 # Number of bytes of host memory used +host_seconds 903.21 # Real time elapsed on the host +sim_insts 243055556 # Number of instructions simulated +sim_ops 483158347 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 439936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4996672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 212288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2043456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 288960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3313664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 444224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 355648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3199424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11325056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 439936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 212288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 288960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 941184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9131200 # Number of bytes written to this memory -system.physmem.bytes_written::total 9131200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11343552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 444224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 355648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 957376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9153408 # Number of bytes written to this memory +system.physmem.bytes_written::total 9153408 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6874 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 31929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 51776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49991 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176954 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142675 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142675 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177243 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143022 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143022 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 85558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 971740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 397406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 56196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 644433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2202468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 85558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 56196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 183039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1775812 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1775812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 69188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 622418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2206784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 69188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1780711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1780711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 85558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 971740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 397406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 56196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 644433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3978280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 91559 # Number of read requests accepted -system.physmem.writeReqs 81706 # Number of write requests accepted -system.physmem.readBursts 91559 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 81706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5853184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 5229184 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5859776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5229184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 86420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 69188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 622418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3987495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 86962 # Number of read requests accepted +system.physmem.writeReqs 83127 # Number of write requests accepted +system.physmem.readBursts 86962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83127 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5558208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 5320128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5565568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5320128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 24142 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5703 # Per bank write bursts -system.physmem.perBankRdBursts::1 4852 # Per bank write bursts -system.physmem.perBankRdBursts::2 5373 # Per bank write bursts -system.physmem.perBankRdBursts::3 5511 # Per bank write bursts -system.physmem.perBankRdBursts::4 5930 # Per bank write bursts -system.physmem.perBankRdBursts::5 4999 # Per bank write bursts -system.physmem.perBankRdBursts::6 5647 # Per bank write bursts -system.physmem.perBankRdBursts::7 5865 # Per bank write bursts -system.physmem.perBankRdBursts::8 5509 # Per bank write bursts -system.physmem.perBankRdBursts::9 5229 # Per bank write bursts -system.physmem.perBankRdBursts::10 5185 # Per bank write bursts -system.physmem.perBankRdBursts::11 5201 # Per bank write bursts -system.physmem.perBankRdBursts::12 6216 # Per bank write bursts -system.physmem.perBankRdBursts::13 6911 # Per bank write bursts -system.physmem.perBankRdBursts::14 6949 # Per bank write bursts -system.physmem.perBankRdBursts::15 6376 # Per bank write bursts -system.physmem.perBankWrBursts::0 5797 # Per bank write bursts -system.physmem.perBankWrBursts::1 4843 # Per bank write bursts -system.physmem.perBankWrBursts::2 5036 # Per bank write bursts -system.physmem.perBankWrBursts::3 5163 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 4815 # Per bank write bursts -system.physmem.perBankWrBursts::6 4988 # Per bank write bursts -system.physmem.perBankWrBursts::7 5321 # Per bank write bursts -system.physmem.perBankWrBursts::8 4852 # Per bank write bursts -system.physmem.perBankWrBursts::9 4657 # Per bank write bursts -system.physmem.perBankWrBursts::10 4410 # Per bank write bursts -system.physmem.perBankWrBursts::11 4367 # Per bank write bursts -system.physmem.perBankWrBursts::12 5498 # Per bank write bursts -system.physmem.perBankWrBursts::13 5314 # Per bank write bursts -system.physmem.perBankWrBursts::14 5778 # Per bank write bursts -system.physmem.perBankWrBursts::15 5504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 33935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5197 # Per bank write bursts +system.physmem.perBankRdBursts::1 4660 # Per bank write bursts +system.physmem.perBankRdBursts::2 5410 # Per bank write bursts +system.physmem.perBankRdBursts::3 5303 # Per bank write bursts +system.physmem.perBankRdBursts::4 5131 # Per bank write bursts +system.physmem.perBankRdBursts::5 4781 # Per bank write bursts +system.physmem.perBankRdBursts::6 5593 # Per bank write bursts +system.physmem.perBankRdBursts::7 5451 # Per bank write bursts +system.physmem.perBankRdBursts::8 5257 # Per bank write bursts +system.physmem.perBankRdBursts::9 4895 # Per bank write bursts +system.physmem.perBankRdBursts::10 5205 # Per bank write bursts +system.physmem.perBankRdBursts::11 5208 # Per bank write bursts +system.physmem.perBankRdBursts::12 5485 # Per bank write bursts +system.physmem.perBankRdBursts::13 6574 # Per bank write bursts +system.physmem.perBankRdBursts::14 6603 # Per bank write bursts +system.physmem.perBankRdBursts::15 6094 # Per bank write bursts +system.physmem.perBankWrBursts::0 5588 # Per bank write bursts +system.physmem.perBankWrBursts::1 5124 # Per bank write bursts +system.physmem.perBankWrBursts::2 5267 # Per bank write bursts +system.physmem.perBankWrBursts::3 4836 # Per bank write bursts +system.physmem.perBankWrBursts::4 5431 # Per bank write bursts +system.physmem.perBankWrBursts::5 5206 # Per bank write bursts +system.physmem.perBankWrBursts::6 5103 # Per bank write bursts +system.physmem.perBankWrBursts::7 5105 # Per bank write bursts +system.physmem.perBankWrBursts::8 5093 # Per bank write bursts +system.physmem.perBankWrBursts::9 5184 # Per bank write bursts +system.physmem.perBankWrBursts::10 5317 # Per bank write bursts +system.physmem.perBankWrBursts::11 5091 # Per bank write bursts +system.physmem.perBankWrBursts::12 4613 # Per bank write bursts +system.physmem.perBankWrBursts::13 5363 # Per bank write bursts +system.physmem.perBankWrBursts::14 5354 # Per bank write bursts +system.physmem.perBankWrBursts::15 5452 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5140984417000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5136428746000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 91559 # Read request sizes (log2) +system.physmem.readPktSize::6 86962 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 81706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 86389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 743 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83127 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -161,1114 +161,1119 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4099 # What write queue length does an incoming req see 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does an incoming req see -system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.476998 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.125046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 300.303961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15966 39.83% 39.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9813 24.48% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4306 10.74% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2350 5.86% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1723 4.30% 85.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1131 2.82% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 740 1.85% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 595 1.48% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3460 8.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40084 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.316984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.117398 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4096 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39704 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.985896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.719261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.548634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16089 40.52% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9815 24.72% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4115 10.36% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2259 5.69% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1546 3.89% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1077 2.71% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 717 1.81% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 581 1.46% 91.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3505 8.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39704 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4014 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.636024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.585773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4011 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.938019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.673577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.950142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 4 0.10% 1.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.07% 1.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.10% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3475 84.80% 86.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 74 1.81% 88.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.68% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 103 2.51% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 14 0.34% 92.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 88 2.15% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 1.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.12% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.20% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.20% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.10% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 126 3.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 13 0.32% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.05% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.37% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4098 # Writes before turning the bus around for reads -system.physmem.totQLat 1118460500 # Total ticks spent queuing -system.physmem.totMemAccLat 2833260500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 457280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12229.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4014 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4014 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.709268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.149216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.865339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3286 81.86% 83.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 102 2.54% 86.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.77% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 110 2.74% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 16 0.40% 90.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 107 2.67% 92.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 56 1.40% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.50% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 148 3.69% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.07% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.25% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4014 # Writes before turning the bus around for reads +system.physmem.totQLat 1058164225 # Total ticks spent queuing +system.physmem.totMemAccLat 2686545475 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 434235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12184.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30979.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30934.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.88 # Average write queue length when enqueuing -system.physmem.readRowHits 73104 # Number of row buffer hits during reads -system.physmem.writeRowHits 59973 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.40 # Row buffer hit rate for writes -system.physmem.avgGap 29671222.79 # Average gap between requests -system.physmem.pageHitRate 76.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 146323800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79666125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 342256200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 267792480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96409908585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2240143266750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587784324100 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.897651 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3686083069500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing +system.physmem.readRowHits 68775 # Number of row buffer hits during reads +system.physmem.writeRowHits 61495 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes +system.physmem.avgGap 30198476.95 # Average gap between requests +system.physmem.pageHitRate 76.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145461960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79191750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 323902800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 269956800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96312598470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240118682500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587633207560 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.890236 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686035921978 # Time in different power states +system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19995411750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19846503022 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156711240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 371092800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 261662400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250395110160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96741256995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2232099467250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2580110601720 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.145421 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685614437250 # Time in different power states -system.physmem_1.memoryStateTime::REF 128013860000 # Time in different power states +system.physmem_1.actEnergy 154700280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 84191250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 353503800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 268706160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96598721655 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233305647250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581148883675 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.102542 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685636098978 # Time in different power states +system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20427995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20213469772 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069587616 # number of cpu cycles simulated +system.cpu0.numCycles 1072285216 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72296493 # Number of instructions committed -system.cpu0.committedOps 147472982 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 135372886 # Number of integer alu accesses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu0.committedInsts 71949475 # Number of instructions committed +system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134558001 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 990052 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14329607 # number of instructions that are conditional controls -system.cpu0.num_int_insts 135372886 # number of integer instructions +system.cpu0.num_func_calls 963710 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134558001 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 248231827 # number of times the integer registers were read -system.cpu0.num_int_register_writes 116398223 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246915369 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115616478 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 84256506 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 56232303 # number of times the CC registers were written -system.cpu0.num_mem_refs 13832544 # number of memory refs -system.cpu0.num_load_insts 10299641 # Number of load instructions -system.cpu0.num_store_insts 3532903 # Number of store instructions -system.cpu0.num_idle_cycles 1014098909.517961 # Number of idle cycles -system.cpu0.num_busy_cycles 55488706.482039 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051879 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948121 # Percentage of idle cycles -system.cpu0.Branches 15685270 # Number of branches fetched -system.cpu0.op_class::No_OpClass 94460 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 133436032 90.48% 90.55% # Class of executed instruction -system.cpu0.op_class::IntMult 61341 0.04% 90.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 50787 0.03% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::MemRead 10297804 6.98% 97.60% # Class of executed instruction -system.cpu0.op_class::MemWrite 3532903 2.40% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55920141 # number of times the CC registers were written +system.cpu0.num_mem_refs 13826864 # number of memory refs +system.cpu0.num_load_insts 10217566 # Number of load instructions +system.cpu0.num_store_insts 3609298 # Number of store instructions +system.cpu0.num_idle_cycles 1017808473.109560 # Number of idle cycles +system.cpu0.num_busy_cycles 54476742.890440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles +system.cpu0.Branches 15573120 # Number of branches fetched +system.cpu0.op_class::No_OpClass 93860 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132602493 90.43% 90.50% # Class of executed instruction +system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 49730 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction 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mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr 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MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22174 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22174 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 176943 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 349338 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 526281 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 176943 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 349338 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 526281 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 176943 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 349338 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 526281 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2525467000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4769426473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7294893473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2525467000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4769426473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7294893473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2525467000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4769426473 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7294893473 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004014 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004014 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004475 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108917 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004014 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13861.213825 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14272.771457 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13652.755993 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13861.213825 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 862079 # number of writebacks +system.cpu0.icache.writebacks::total 862079 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24042 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24042 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24042 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24042 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24042 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24042 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163640 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376357 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539997 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 163640 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376357 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539997 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 163640 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376357 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539997 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2260578000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5251926966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7512504966 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2260578000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5251926966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7512504966 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260578000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5251926966 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7512504966 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004145 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004145 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004145 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608369012 # number of cpu cycles simulated +system.cpu1.numCycles 2606017772 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35935781 # Number of instructions committed -system.cpu1.committedOps 69853480 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64823976 # Number of integer alu accesses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 35434797 # Number of instructions committed +system.cpu1.committedOps 68967057 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63950611 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 488968 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6599189 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64823976 # number of integer instructions +system.cpu1.num_func_calls 471158 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6540301 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63950611 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120030856 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55861909 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118144126 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55187106 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36569866 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27235503 # number of times the CC registers were written -system.cpu1.num_mem_refs 4739526 # number of memory refs -system.cpu1.num_load_insts 2929606 # Number of load instructions -system.cpu1.num_store_insts 1809920 # Number of store instructions -system.cpu1.num_idle_cycles 2476291441.144386 # Number of idle cycles -system.cpu1.num_busy_cycles 132077570.855614 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050636 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949364 # Percentage of idle cycles -system.cpu1.Branches 7267259 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35769 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 65023245 93.08% 93.14% # Class of executed instruction -system.cpu1.op_class::IntMult 31643 0.05% 93.18% # Class of executed instruction -system.cpu1.op_class::IntDiv 24977 0.04% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::MemRead 2928241 4.19% 97.41% # Class of executed instruction -system.cpu1.op_class::MemWrite 1809920 2.59% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36132535 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26987071 # number of times the CC registers were written +system.cpu1.num_mem_refs 4484181 # number of memory refs +system.cpu1.num_load_insts 2795215 # Number of load instructions +system.cpu1.num_store_insts 1688966 # Number of store instructions +system.cpu1.num_idle_cycles 2475079667.780020 # Number of idle cycles +system.cpu1.num_busy_cycles 130938104.219980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles +system.cpu1.Branches 7181908 # Number of branches fetched +system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64398957 93.38% 93.42% # Class of executed instruction +system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction +system.cpu1.op_class::MemRead 2793855 4.05% 97.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 1688966 2.45% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69853795 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28595724 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28595724 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 274281 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 25954960 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25419524 # Number of BTB hits +system.cpu1.op_class::total 68967226 # Class of executed instruction +system.cpu2.branchPred.lookups 28923329 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28923329 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 299282 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26177543 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25594622 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.937057 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 541766 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 58217 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155590039 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.773202 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 576797 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63162 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157005453 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9827756 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 141445049 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28595724 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 25961290 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144324316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 577708 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 89529 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 4628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52140 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 25 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1381 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3207378 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 141789 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2491 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.800587 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.004500 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10540975 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142872413 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28923329 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26171419 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144748563 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 631577 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 103277 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 68344 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1893 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3422619 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 155063 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.805087 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.007326 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100285595 64.87% 64.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 850088 0.55% 65.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23359910 15.11% 80.53% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 558025 0.36% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 768716 0.50% 81.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 809103 0.52% 81.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 512827 0.33% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 703407 0.45% 82.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 26750232 17.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100986274 64.82% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 876971 0.56% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23450168 15.05% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 581136 0.37% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798057 0.51% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 839354 0.54% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 536255 0.34% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 727896 0.47% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27000494 17.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154597903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.183789 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909088 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8590820 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95748375 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 20322096 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4023271 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 289506 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 275783905 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 289506 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10203934 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77122652 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4692669 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 22463307 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14202064 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 274713209 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 193941 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5398657 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 70031 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 7189088 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 328421156 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 598952608 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 367856783 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 202 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 317944423 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10476733 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 154897 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 156262 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19984245 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6287198 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3639298 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 400920 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 367403 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 273029174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 403661 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 271361789 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 92310 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7713990 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11716947 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 58327 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154597903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.755275 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.385225 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 155796605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184219 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909984 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9166270 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95860787 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22254534 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3994693 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 316440 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278480395 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 316440 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10781716 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77380942 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5123914 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24366684 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13623085 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277321096 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 194260 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5340054 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70865 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6669514 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331396172 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605049332 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371619608 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 320040545 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11355627 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162880 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 164114 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19801512 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6563978 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3714528 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 447098 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 397095 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275506715 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 407720 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273559358 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 95175 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8352705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12694060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62726 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155796605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755875 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385543 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93164208 60.26% 60.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5135729 3.32% 63.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3649233 2.36% 65.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3187928 2.06% 68.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23055647 14.91% 82.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2154571 1.39% 84.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23598215 15.26% 99.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 439899 0.28% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 212473 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93882329 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5118192 3.29% 63.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3721128 2.39% 65.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3254343 2.09% 68.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23198440 14.89% 82.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2207021 1.42% 84.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23723391 15.23% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 467418 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 224343 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154597903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155796605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1212353 81.77% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 211907 14.29% 96.06% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 58391 3.94% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1207560 81.79% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 207213 14.03% 95.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 61669 4.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 71762 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 261142020 96.23% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 52428 0.02% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48121 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 75 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6661415 2.45% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3385968 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 77609 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263069409 96.17% 96.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56423 0.02% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50250 0.02% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6863260 2.51% 98.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3442333 1.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 271361789 # Type of FU issued -system.cpu2.iq.rate 1.744082 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1482651 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 698896144 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 281150786 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 269884047 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 272772537 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697485 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273559358 # Type of FU issued +system.cpu2.iq.rate 1.742356 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1476442 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005397 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704486629 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284271419 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272061524 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274958042 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 723498 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1044107 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5365 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4726 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 557112 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1134318 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5680 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5091 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 595155 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 749552 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 25864 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 712054 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23601 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 289506 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69224885 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4893125 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 273432835 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 29776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6287198 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3639298 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 235948 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 164149 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4411192 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4726 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 153905 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 164065 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 317970 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 270855594 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6536848 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 455372 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 316440 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69933639 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4486006 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275914435 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 35023 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6563978 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3714528 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 243237 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162474 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4012628 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5091 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167077 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 180895 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347972 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273011944 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6727791 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 497508 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9843230 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27477788 # Number of branches executed -system.cpu2.iew.exec_stores 3306382 # Number of stores executed -system.cpu2.iew.exec_rate 1.740829 # Inst execution rate -system.cpu2.iew.wb_sent 270693369 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 269884157 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 210625616 # num instructions producing a value -system.cpu2.iew.wb_consumers 345602988 # num instructions consuming a value +system.cpu2.iew.exec_refs 10089541 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27708179 # Number of branches executed +system.cpu2.iew.exec_stores 3361750 # Number of stores executed +system.cpu2.iew.exec_rate 1.738869 # Inst execution rate +system.cpu2.iew.wb_sent 272840114 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272061642 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212265363 # num instructions producing a value +system.cpu2.iew.wb_consumers 348191102 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.734585 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609444 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.732817 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609623 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7711989 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 345334 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 277097 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 153447715 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.731657 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.637088 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8350016 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 344994 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 302940 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154548999 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731242 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.636335 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 96780970 63.07% 63.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4222028 2.75% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1231000 0.80% 66.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24221852 15.79% 82.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 924771 0.60% 83.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 693299 0.45% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 425605 0.28% 83.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 22935468 14.95% 98.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2012722 1.31% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 97452573 63.06% 63.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4255618 2.75% 65.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1276058 0.83% 66.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24388972 15.78% 82.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 952831 0.62% 83.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 707614 0.46% 83.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 433779 0.28% 83.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23017420 14.89% 98.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2064134 1.34% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 153447715 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 134778170 # Number of instructions committed -system.cpu2.commit.committedOps 265718845 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154548999 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135671284 # Number of instructions committed +system.cpu2.commit.committedOps 267561730 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8325277 # Number of memory references committed -system.cpu2.commit.loads 5243091 # Number of loads committed -system.cpu2.commit.membars 153740 # Number of memory barriers committed -system.cpu2.commit.branches 27132938 # Number of branches committed +system.cpu2.commit.refs 8549033 # Number of memory references committed +system.cpu2.commit.loads 5429660 # Number of loads committed +system.cpu2.commit.membars 149565 # Number of memory barriers committed +system.cpu2.commit.branches 27339879 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 242753564 # Number of committed integer instructions. -system.cpu2.commit.function_calls 416792 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41984 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 257254606 96.81% 96.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 50787 0.02% 96.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 46205 0.02% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5243061 1.97% 98.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3082186 1.16% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244517945 # Number of committed integer instructions. +system.cpu2.commit.function_calls 438137 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46306 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258863559 96.75% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48345 0.02% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3119373 1.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 265718845 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2012722 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 424836983 # The number of ROB reads -system.cpu2.rob.rob_writes 548017282 # The number of ROB writes -system.cpu2.timesIdled 100227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 992136 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909996040 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 134778170 # Number of Instructions Simulated -system.cpu2.committedOps 265718845 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.154416 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.154416 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.866239 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.866239 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 360832495 # number of integer regfile reads -system.cpu2.int_regfile_writes 216221900 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73134 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 137826475 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106107258 # number of cc regfile writes -system.cpu2.misc_regfile_reads 87959882 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137617 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3552161 # Transaction distribution -system.iobus.trans_dist::ReadResp 3552161 # Transaction distribution -system.iobus.trans_dist::WriteReq 57740 # Transaction distribution -system.iobus.trans_dist::WriteResp 57740 # Transaction distribution -system.iobus.trans_dist::MessageReq 1667 # Transaction distribution -system.iobus.trans_dist::MessageResp 1667 # Transaction distribution +system.cpu2.commit.op_class_0::total 267561730 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2064134 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 428366748 # The number of ROB reads +system.cpu2.rob.rob_writes 553077080 # The number of ROB writes +system.cpu2.timesIdled 112413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1208848 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910585835 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135671284 # Number of Instructions Simulated +system.cpu2.committedOps 267561730 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157249 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157249 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864118 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864118 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363754203 # number of integer regfile reads +system.cpu2.int_regfile_writes 218036965 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138800226 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106739606 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88774953 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143862 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution +system.iobus.trans_dist::WriteReq 57726 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7080234 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066648 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7124546 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7223136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110880 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209436 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3540117 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533324 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13934 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3568475 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6602951 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2194728 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561720 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2378920 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3095000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5419500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 748000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 921000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 140118000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 199977500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 507000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8907000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11026500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 119418499 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144387981 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 295238000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283491000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 23500000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 31080000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 920000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 979000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47573 # number of replacements -system.iocache.tags.tagsinuse 0.105025 # Cycle average of tags in use +system.iocache.tags.replacements 47579 # number of replacements +system.iocache.tags.tagsinuse 0.099877 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000694858009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.105025 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006564 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006564 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000697713509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.099877 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006242 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006242 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428652 # Number of tag accesses -system.iocache.tags.data_accesses 428652 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses -system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.tags.tag_accesses 428706 # Number of tag accesses +system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses +system.iocache.ReadReq_misses::total 914 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses -system.iocache.demand_misses::total 908 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses -system.iocache.overall_misses::total 908 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17834920 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17834920 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3008484579 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3008484579 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 17834920 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17834920 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 17834920 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17834920 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses +system.iocache.demand_misses::total 914 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses +system.iocache.overall_misses::total 914 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880276 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 126880276 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631346705 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3631346705 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 126880276 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 126880276 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 126880276 # number of overall miss cycles +system.iocache.overall_miss_latency::total 126880276 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1277,323 +1282,327 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 19641.982379 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 64393.933626 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 64393.933626 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 19641.982379 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 19641.982379 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138818.682713 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138818.682713 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 745 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 69 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.797101 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 150 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 23200 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 23200 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 150 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 150 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 150 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 150 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10334920 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1848484579 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10334920 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10334920 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10334920 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.165198 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.496575 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.165198 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.165198 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.165198 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68899.466667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79676.059440 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 68899.466667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68899.466667 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 756 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 756 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27936 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 27936 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 89080276 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234546705 # number of WriteLineReq MSHR miss cycles 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+system.l2c.tags.sampled_refs 168682 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.502158 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50975.916354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1575.171206 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4997.364493 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 516.989893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1851.248692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 5.076348 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 959.125226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3917.724589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777831 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51005.596123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1646.370611 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4933.032602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 515.170721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1886.198863 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.247587 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 884.114832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3927.326006 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.778284 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.024035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076254 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000077 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.014635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.059780 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.988750 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64046 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3569 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52933 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977264 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41263442 # Number of tag accesses -system.l2c.tags.data_accesses 41263442 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10440 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11603 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6238 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 52514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits -system.l2c.ReadReq_hits::total 110945 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.025122 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.028781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013491 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.059926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.988879 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64078 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6913 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977753 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41426818 # Number of tag accesses +system.l2c.tags.data_accesses 41426818 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20684 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10937 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5737 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 57360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12726 # number of ReadReq hits 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6238 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 173626 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 248539 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 52514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 344819 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 656469 # number of demand (read+write) hits -system.l2c.demand_hits::total 2427659 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19237 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10442 # number of overall hits -system.l2c.overall_hits::cpu0.inst 323982 # number of overall hits -system.l2c.overall_hits::cpu0.data 569277 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11603 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6238 # number of overall hits -system.l2c.overall_hits::cpu1.inst 173626 # number of overall hits -system.l2c.overall_hits::cpu1.data 248539 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 52514 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits -system.l2c.overall_hits::cpu2.inst 344819 # number of overall hits -system.l2c.overall_hits::cpu2.data 656469 # number of overall hits -system.l2c.overall_hits::total 2427659 # number of overall hits +system.l2c.WritebackDirty_hits::writebacks 1548077 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1548077 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 861736 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 861736 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 31 # number of UpgradeReq hits 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-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121557.883630 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117794.030825 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 142977.272727 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126027.353267 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121895.958661 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 120655.342764 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152593.568626 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 149032.145990 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 150730.826829 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171688.649425 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200329.907000 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 182283.269962 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 152946.044577 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 149543.469245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 151173.698242 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 96355 # number of writebacks +system.l2c.writebacks::total 96355 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 1 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 31 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 31 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 151 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 525 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 676 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 24150 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 37534 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 61684 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2461 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5557 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 8018 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 4611 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12720 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 17331 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2461 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 28761 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 31 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5557 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 50254 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 87064 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2461 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 28761 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 31 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5557 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 50254 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 87064 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 4040500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10668000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 37156500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47824500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2805520000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4488029000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7293549000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 296188500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 701637000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 997825500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 559971000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1624421500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2184392500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 296188500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3365491000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 701637000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 6112450500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10479807500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 296188500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3365491000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 701637000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 6112450500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10479807500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28471375500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30579722500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59051098000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 633646000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 578928500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1212574500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29105021500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31158651000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60263672500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000262 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.822884 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.408213 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452781 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378810 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.212834 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021742 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020912 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012854 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033243 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5081876 # Transaction distribution -system.membus.trans_dist::ReadResp 5130307 # Transaction distribution -system.membus.trans_dist::WriteReq 13937 # Transaction distribution -system.membus.trans_dist::WriteResp 13937 # Transaction distribution -system.membus.trans_dist::Writeback 142675 # Transaction distribution -system.membus.trans_dist::CleanEvict 8457 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1667 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1667 # Transaction distribution -system.membus.trans_dist::ReadExReq 129637 # Transaction distribution -system.membus.trans_dist::ReadExResp 129637 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48432 # Transaction distribution -system.membus.trans_dist::MessageReq 1667 # Transaction distribution -system.membus.trans_dist::MessageResp 1667 # Transaction distribution -system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.trans_dist::ReadReq 5063565 # Transaction distribution +system.membus.trans_dist::ReadResp 5112222 # Transaction distribution +system.membus.trans_dist::WriteReq 13898 # Transaction distribution +system.membus.trans_dist::WriteResp 13898 # Transaction distribution +system.membus.trans_dist::WritebackDirty 143022 # Transaction distribution +system.membus.trans_dist::CleanEvict 8552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1672 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1672 # Transaction distribution +system.membus.trans_dist::ReadExReq 129713 # Transaction distribution +system.membus.trans_dist::ReadExResp 129713 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48657 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7124546 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3067080 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10653122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142139 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10798595 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3568475 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6134157 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17466624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27169256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3035200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30211124 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 409 # Total snoops (count) -system.membus.snoop_fanout::samples 5475610 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000304 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017446 # Request fanout histogram +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10617373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10762648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17501760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27151569 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30183297 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 664 # Total snoops (count) +system.membus.snoop_fanout::samples 5457993 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5473943 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5456349 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5475610 # Request fanout histogram -system.membus.reqLayer0.occupancy 227177500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457993 # Request fanout histogram +system.membus.reqLayer0.occupancy 219248500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 301308000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1840000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2377080 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 538434425 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 547350354 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 920000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1398080 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1326481306 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1208209380 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 41176558 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52355698 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1815,60 +1822,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5040257 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546109 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 319 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1148 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5045321 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2544604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1171 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1171 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5235870 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7440960 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13939 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13939 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1628762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 950991 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1645 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1645 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289206 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 857150 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1347950 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 920 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 23200 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2570707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15105454 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 66396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204903 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17947460 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54857344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213491432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 241048 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 697376 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269287200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 238040 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10439686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.005090 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.071166 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5213952 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7425084 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1631207 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861736 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 94941 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1656 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1656 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289822 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862602 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349057 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072185 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70382 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 205946 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17935440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110356800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581265 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 259408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748104 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324945577 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 226314 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8918759 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005043 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.070832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 10386543 99.49% 99.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 53143 0.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8873785 99.50% 99.50% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 44974 0.50% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10439686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2709674498 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8918759 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3217757998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 251420 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 405376 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 789952436 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 810539408 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1874874404 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1832719254 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23291487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24003478 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 94859175 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87328075 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |